201104801 六、發明說明： 【發明所屬之技術領域】 本發明係有_裝技術’ _是-種“塊結構及其方法。 【先前技術】 由於使用者對於高速化、多功能化、高容量化與輕、薄、短、 小的要求，使得半導體元件的構裝密度越來越高。—般而言，基本的 晶片封裝結構至少包括··-基板；至少—晶片設置於其上^與^板電 性連接α及-封裝㈣覆蓋晶片、電性連接結顺部分基板。於封 裝領域，如何減少製程步驟、降低成核提高缝㈣度是—個無止 盡的目標與重要的課題。 【發明内容】 為了解決上述問題’本發明目的之一係提供一種晶片封裝结構 及其方法’藉由使用賴取代原有基板與職材料來封裝整個封裝 體。 本發明目的之-係提供-種“域結構及其綠，藉由膠膜 ^曰曰片密狀兩牌膜，其職方關單城有效避餅來物影響晶 片0 為了達到上述目的，本發明一實施例之一種晶片封裝結構， ·—第—膠膜’係具有複數個内接點於—上表面與複數個外接 =於-下表面，其中内無與外接·_電性連接；至少_晶片，係咬 =第-膠膜之上表面並與内接點m連接；—第二膠膜，係覆蓋於 =片上並與第-膠卿成—封财間容置晶片；以及複數個導電焊 球’係設置於外接點上。 201104801 本發明另一實施例之一種晶片封裝方法，係包括下列步驟： 提供-第-膠膜，其中第-膠膜係具有複數個内接點於—上表面與複 數個外接點於一下表面，且内接點與外接點係電性連接；設置至少;一 晶片於第一膠膜之上表面並使晶片與内接點電性連接；設置複數個導 電焊球於外接點上；設置H膜於；上；以及糊—沖壓步驟 移除多餘第一膠膜與第二膠膜並使第一膠膜與第二膠膜連接形成一 封閉空間以容置晶片。 【實施方式】 鲁 請參照® 1E，於本實施例中’晶片封裝結構包括：一第一膠 膜10，至> 一晶片20 ’ 一第二膠膜40 ;以及複數個導電焊球3〇。第 膠臈10具有複數個内接點12於-上表面與複數個外接點14於一 下^面，其中内接點12與外接點Μ係祕連接。晶片20係設置於 第一膠膜10之上表面並與内接點12電性連接。第二膠膜4〇係覆蓋 於晶片20上並與第一膠膜10形成一封閉空間容置晶片20。導電焊球 30係設置於外接點14上。 於實鈀例中，内接點12與外接點14可利用第一膠膜内1〇之 • 金屬線路（圖上未示）互相電性連接。於一實施例中，晶片2〇具有 ，數個銅凸塊（圖上未示）與内接點12電性連接。於一實施例中， 曰片封裝結構可设置複數個晶片2〇。於一實施例中，晶片 I互相堆疊設置’如圖2所示。於一實施例中，晶片20亦可 並排設置（圖上未示）。 月“.、圖1A圖1B、圖ic、圖id與圖1E，於本實施例中晶 褒方法包括下列步驟。如圖1A所示，提供一第一膠膜10， ^ 膠膜1G係具有複數個内接點12於—上表面與複數個外接點 於—下表面，且内接點12與外接點14係電性連接。設置至少一晶 於第朦膜10之上表面並使晶片2〇與内接點12電性連接，如 201104801 圖1B所不。晶片20可利用複數個銅凸塊（圖上未示）與内接點 12電性連接。參照圖1C，設置複數個導電焊球3〇於外接點14上。 設置一第二膠膜40於晶片20上並利用一沖壓步驟移除多餘第一膠膜 1〇與第一膠膜40。使第一膠膜10與第二膠膜40連接形成一封閉空 間以容置晶片2G ’如圖1D與圖1E所示。 於—實施例中’沖壓步驟時更可同時提供一加熱步驟幫助 第一膠膜_10與第二膠膜4〇連接。於不同實施例中，複數個晶片扣 互相堆疊。又置（如圖2所示）或並排設置。於一實施例中， 隹k之日曰片2〇可利用石夕穿孔（through-silicon via，TSV )枯 • 術電性連接。 本^明藉由膠膜當作整個封裝技術的核心，並利用重壓（punch) 的=式結合與分段。本發明職之使用可糊既有的捲帶技術。覆蓋 於晶片上之觀是否絲牢非主要要求，僅需隔絕絲物即可。若需 避免膠膜在熱脹冷縮環境下變化過大，可於勝膜内增加細微的小礼減 少膨脹的現象產生以避免膠膜撐破。 紅合上述，本發明藉由使用膠膜取代原有基板與封裝材料來封 裝整個封裝體；藉由膠麟晶4賴於兩牌助，其封裝方法簡單 φ 且能有效避免外來物影響晶片。 以上所述之實施例僅係為說明本發明之技術思想及特點，其目 的在使熟習此碰#之人士賴瞭解本發明之内容並據以實施，當不 能，之限定本㈣之專纖圍，即大驗本發衝揭示之精神所作之 均等變化或修飾，仍應涵蓋在本發明之專利範圍内。 201104801 【圖式簡單說明】 圖1A、圖1B、圖1C、圖1D與圖1E所示為根據本發明一實施例之 示意圖。 圖2所示為根據本發明一實施例之示意圖。 【主要元件符號說明】 10 第一膠膜 12 内接點 14 外接點 20 晶片 30 導電焊球 40 第二膠膜201104801 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a "block structure" and a "block structure" and a method thereof. [Prior Art] Since the user is high-speed, multi-functional, and high-capacity With the requirements of lightness, thinness, shortness, and smallness, the mounting density of semiconductor components is becoming higher and higher. Generally, the basic chip package structure includes at least a substrate; at least, the wafer is disposed thereon and ^ The board is electrically connected to the α and - package (4) to cover the wafer, and the electrical connection is connected to the substrate. In the field of packaging, how to reduce the process steps, reduce the nucleation and improve the seam (four degrees) is an endless goal and an important issue. SUMMARY OF THE INVENTION In order to solve the above problems, one of the objects of the present invention is to provide a chip package structure and method thereof for packaging an entire package by using a substrate instead of a conventional substrate. The object of the present invention is to provide a kind of " The structure of the domain and its green color, by means of a two-layer film of a film and a film, the utility of the employee is effective in preventing the wafer from affecting the wafer. In order to achieve the above object, an embodiment of the present invention The package structure, the first-film has a plurality of internal contacts on the upper surface and a plurality of external connections on the lower surface, wherein no internal connection is made to the external connection; at least _ wafer, system bite = The upper surface of the first film is connected to the inner contact point m; the second film is overlaid on the sheet and is interposed with the first gelatin-filled wafer; and a plurality of conductive solder balls are provided At the external point. 201104801 A wafer packaging method according to another embodiment of the present invention includes the following steps: providing a -first film, wherein the first film has a plurality of inner contacts on the upper surface and a plurality of outer contacts on the lower surface, And the inner contact is electrically connected to the external contact; at least one wafer is disposed on the upper surface of the first adhesive film and electrically connected to the inner contact; the plurality of conductive solder balls are disposed on the external contact; and the H film is disposed And the paste-stamping step removes the excess first film and the second film and connects the first film to the second film to form a closed space to accommodate the wafer. [Embodiment] Referring to ® 1E, in the present embodiment, the 'wafer package structure includes: a first film 10, to > a wafer 20' a second film 40; and a plurality of conductive solder balls 3 . The first capsule 10 has a plurality of inner contacts 12 on the upper surface and a plurality of outer contacts 14 on the lower surface, wherein the inner contacts 12 are connected to the external contacts. The wafer 20 is disposed on the upper surface of the first adhesive film 10 and electrically connected to the inner contact 12 . The second adhesive film 4 is coated on the wafer 20 and forms a closed space accommodating wafer 20 with the first adhesive film 10. The conductive solder balls 30 are disposed on the external contacts 14. In the actual palladium example, the inner contact 12 and the outer contact 14 can be electrically connected to each other by using a metal line (not shown) in the first film. In one embodiment, the wafer 2 has a plurality of copper bumps (not shown) electrically connected to the inner contacts 12. In one embodiment, the die package structure can be provided with a plurality of wafers 2 . In one embodiment, the wafers I are stacked one on another as shown in FIG. In one embodiment, the wafers 20 can also be arranged side by side (not shown). In the present embodiment, the wafer method includes the following steps. As shown in FIG. 1A, a first film 10 is provided, and the film 1G has a film. The plurality of inner contacts 12 are on the upper surface and the plurality of external contacts on the lower surface, and the inner contacts 12 are electrically connected to the outer contacts 14. The at least one crystal is disposed on the upper surface of the second film 10 and the wafer 2 is disposed. 〇 is electrically connected to the inner contact 12, such as 201104801 and FIG. 1B. The wafer 20 can be electrically connected to the inner contact 12 by using a plurality of copper bumps (not shown). Referring to FIG. 1C, a plurality of conductive solders are disposed. The ball 3 is placed on the external contact 14. A second film 40 is disposed on the wafer 20 and the excess first film 1 and the first film 40 are removed by a stamping step. The first film 10 and the second film are provided. The film 40 is connected to form a closed space to accommodate the wafer 2G' as shown in FIG. 1D and FIG. 1E. In the embodiment, the stamping step can simultaneously provide a heating step to assist the first film _10 and the second glue. The film is connected. In various embodiments, a plurality of wafer buckles are stacked on each other, and are placed again (as shown in FIG. 2) or side by side. In the example, the 曰k 曰 〇 〇 〇 〇 〇 〇 〇 〇 〇 〇 石 石 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕(punch) = combination and segmentation. The use of the present invention can be used to paste the existing tape technology. The view on the wafer is not the main requirement for silk tightness, only need to isolate the wire. The film changes too much in the thermal expansion and contraction environment, and can increase the fineness of the film in the film to reduce the swelling phenomenon to avoid the film breakage. In the above, the present invention replaces the original substrate and package by using the film. The material is used to encapsulate the entire package; the coating method is simple φ and can effectively prevent foreign objects from affecting the wafer by using the two brands. The embodiments described above are only for explaining the technical idea and characteristics of the present invention. The purpose of the present invention is to enable the person familiar with the invention to understand the contents of the present invention and to implement it, and if not, to limit the uniformity or modification of the spirit of the (4), that is, the spirit of the inspection. Should still cover the patent of the present invention BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A, Fig. 1B, Fig. 1C, Fig. 1D and Fig. 1E are schematic views showing an embodiment of the present invention. Fig. 2 is a view showing an embodiment of the present invention. [Main component symbol description] 10 First film 12 Internal contact 14 External contact 20 Wafer 30 Conductive solder ball 40 Second film