TWI395290B - Flash memory and method of fabricating the same - Google Patents

Description

Flash memory and manufacturing method thereof

The present invention relates to a memory and a method of fabricating the same, and more particularly to a flash memory and a method of fabricating the same.

Non-volatile memory is widely used in personal computers and electronic devices because it has the characteristics of storing, reading, and erasing data many times, and the stored data does not disappear after power-off. In general, a typical memory component includes a stacked gate structure composed of a floating gate and a control gate. The floating gate is disposed between the control gate and the substrate and is in a floating state, and the control gate is connected to the word line. A tunneling dielectric layer is disposed between the substrate and the floating gate, and a gate dielectric layer is disposed between the floating gate and the control gate.

Generally, the floating gate is disposed between the isolation structures, and the surface of the floating gate is, for example, flush with the surface of the isolation structure. Therefore, removing a portion of the isolation structure between the floating gates can increase the exposed area of the floating gate to increase the contact area between the floating gate and the control gate, thereby increasing the gate coupling ratio ( Gate-coupling ratio, GCR).

However, the memory element includes a memory cell region and a peripheral region, and in order to remove a portion of the isolation structure between the floating gates of the memory cell region, the isolation structure of a portion of the peripheral region is often removed. In the peripheral region, removing too much isolation structure may expose a gate dielectric layer on the substrate between the isolation structures, such that the gate dielectric layer degrades in subsequent etching processes and cleaning processes, and affects peripheral component components. Electrical. Moreover, after removing a portion of the isolation structure, a full interlayer inter-gate dielectric layer is formed on the substrate, and then the inter-gate dielectric layer and the floating gate are removed. If the height difference between the surface of the isolation structure located in the peripheral region and the surface of the floating gate is too large, the etching process for subsequently removing the dielectric layer between the gate and the floating gate of the peripheral region may be due to the spacer effect (spacer) Effect) is not easy to carry out.

Therefore, how to properly remove the isolation structure between the memory cell region and a portion of the peripheral region to improve the gate coupling ratio of the memory device and maintain good electrical conductivity is a very important and urgent problem to be solved.

The invention provides a method for manufacturing a flash memory, which has a high gate coupling ratio and good electrical properties.

The invention provides a method for manufacturing a flash memory. First, a substrate is provided. The substrate includes a memory cell region and a peripheral region. A plurality of isolation structures are formed on the substrate, and a first dielectric layer and a floating gate are formed on the substrate between the isolation structures. Next, a mask layer is formed on the substrate, the mask layer covering the isolation structure of the peripheral region and the isolation structure located in the memory cell region and adjacent to the peripheral region. Then, using the mask layer as a mask, a part of the isolation structure of the memory cell region is removed, so that the surface of the isolation structure located in the peripheral region has a first height difference from the surface of the first dielectric layer, and is located in the memory cell region. And having a first height difference between the surface of the isolation structure adjacent to the peripheral region and the surface of the first dielectric layer, and having a second surface between the surface of the remaining isolation structure located in the memory cell region and the surface of the first dielectric layer a height difference, wherein the first height difference is greater than the second height difference, and the surface of the isolation structure is higher than the surface of the first dielectric layer. Next, remove the mask layer. Then, a dielectric layer between the gates is formed on the substrate. Following this, the inter-gate dielectric layer and the floating gate are removed. Then, a conductor layer is formed on the substrate.

In an embodiment of the invention, after removing the inter-gate dielectric layer and the floating gate of the peripheral region, further comprising removing the first dielectric layer of the peripheral region and the substrate between the isolation structures of the peripheral region A second dielectric layer is formed thereon.

In an embodiment of the invention, the surface of the isolation structure of the peripheral region is higher than the surface of the second dielectric layer, and the surface of the isolation structure of the peripheral region has a third height between the surface of the second dielectric layer and the surface of the second dielectric layer. Poor, wherein the third height difference is greater than the second height difference.

Based on the above, the method for fabricating the flash memory of the present invention utilizes a mask layer to cover the peripheral region to remove a portion of the isolation structure of the memory cell region, such that the surface of the isolation structure of the memory cell region and the surface of the tunnel dielectric layer The height difference is greater than the difference in height between the surface of the isolation structure of the peripheral region and the surface of the gate dielectric layer. In this way, the contact area between the floating gate and the control gate can be increased, and the integrity of the gate dielectric layer of the peripheral region can be maintained, so that the flash memory has a high gate coupling ratio and good electrical properties.

The above described features and advantages of the present invention will be more apparent from the following description.

[First Embodiment]

1A to 1I are schematic cross-sectional views showing the flow of a method of manufacturing a flash memory in accordance with a first embodiment of the present invention.

Referring to FIG. 1A, first, a substrate 100 is provided. The substrate 100 is, for example, a crucible substrate. The substrate 100 includes a memory cell region 102 and a peripheral region 104. Then, a dielectric layer 106 and a mask layer 110 are sequentially formed on the substrate 100. The material of the dielectric layer 106 is, for example, ruthenium oxide, and the formation method thereof is, for example, a thermal oxidation method or a chemical vapor deposition method. The material of the mask layer 110 is, for example, tantalum nitride, and the formation method thereof is, for example, chemical vapor deposition.

Referring to FIG. 1B, a portion of the mask layer 110, the dielectric layer 106, and the substrate 100 are removed to form the trenches 112. The method of removing a portion of the mask layer 110, the dielectric layer 106, and the substrate 100 is, for example, to form a patterned photoresist layer (not shown) on the mask layer 110. Then, an etching process is performed with the patterned photoresist layer as a mask to remove the exposed mask layer 110 and the dielectric layer 106 and the substrate 100 under the mask layer 110. Thereafter, the patterned photoresist layer is removed.

Referring to FIG. 1C, isolation structures 114, 114', 116 are then formed in the trenches 112. The isolation structure 114' is an isolation structure in the memory cell region 102 that is closest to the peripheral region 104. The isolation structures 114, 114', 116 are, for example, shallow trench isolation structures. The material of the isolation structure 114, 114', 116 is, for example, a high-density plasma oxide, which is formed by, for example, forming a layer such as yttrium oxide on the substrate 100 illustrated in FIG. 1B by high-density plasma chemical vapor deposition. The insulating material is then planarized by a chemical mechanical polishing process using the mask layer 110 as a polishing stop layer. Thereafter, the mask layer 110 is removed to expose the dielectric layer 106. The method of removing the mask layer 110 is, for example, an anisotropic etching process.

Referring to FIG. 1D, the dielectric layer 106 is removed, for example, by wet etching, and the tunneling dielectric layer 108 is formed. Then, a conductor material layer (not shown) is formed on the substrate 100, and the material of the conductor material layer is, for example, polysilicon. Subsequently, for example, the isolation structure 114, 114', 116 is used as a polishing stop layer, and a CMP process is performed to planarize the conductor material layer to form the floating gate 120. It is particularly noted that in the present embodiment, the surface of the floating gate 120 is, for example, flush with the surface of the isolation structures 114, 114', 116. In particular, the present invention does not limit the method of forming a flash memory. The process described in FIG. 1A to FIG. 1C is only one of a plurality of processes for performing a flash memory, in other words, those skilled in the art should understand The tunneling dielectric layer 108, the floating gate 120, and the isolation structures 114, 114', 116 shown in FIG. 1D can be fabricated using a variety of methods.

Referring to FIG. 1E, a mask layer 122 is formed on the substrate 100. The mask layer 122 covers the isolation structure 116 of the peripheral region 104 and the isolation structure 114' located in the memory cell region 102 and adjacent to the peripheral region 104. The material of the mask layer 122 is, for example, a photoresist.

Then, with the mask layer 122 as a mask, a portion of the isolation structure 114 located in the memory cell region 102 is removed to form the isolation structure 114a. As such, the surface 124 of the remaining isolation structure 114a of the memory cell 102 is lower than the surface 126 of the isolation structure 116 at the peripheral region 104 except for the isolation structure 114' adjacent the peripheral region 104. In other words, the surfaces 124, 125, 126 of the isolation structures 114a, 114', 116 are higher than the surface 109 of the tunnel dielectric layer 108, and the surface 126 of the isolation structure 116 of the peripheral region 104 and the surface 109 of the tunnel dielectric layer 108 The first height difference H1 between the surface 125 of the isolation structure 114' located in the memory cell region 102 and adjacent to the peripheral region 104 and the surface 109 of the tunnel dielectric layer 108 also have a first height difference H1 between A second height difference H2 that is less than the first height difference H1 is between the surface 124 of the remaining isolation structure 114a of the memory cell 102 and the surface 109 of the tunnel dielectric layer 108.

Referring to FIG. 1F, the mask layer 122 is removed, for example, by an anisotropic etch process. Then, in the present embodiment, for example, the isolation structures 114a, 114', 116 are comprehensively removed to form the isolation structures 114b, 114'a, 116a. Methods of comprehensive removal include wet etching or dry etching. As a result, the surface 124 of the isolation structure 114b located in the memory cell region 102 is still lower than the surface 126 of the isolation structure 116a located in the peripheral region 104 and the surface of the isolation structure 114'a located in the memory cell region 102 and adjacent to the peripheral region 104. 125. In other words, the surfaces 124, 125, 126 of the isolation structures 114b, 114'a, 116a are higher than the surface 109 of the tunneling dielectric layer 108, and are located at the surface 126 of the isolation structure 116a of the peripheral region 104 and the tunneling dielectric layer 108. There is a height difference H3 between the surfaces 109, and the surface 125 of the isolation structure 114'a located in the memory cell region 102 and adjacent to the peripheral region 104 also has a height difference H3 between the surface 109 of the tunneling dielectric layer 108, and is located in the memory. Between the surface 124 of the remaining isolation structure 114b of the cell region 102 and the surface 109 of the tunneling dielectric layer 108, there is a height difference H4 that is less than the height difference H3.

Referring to FIG. 1G, a gate dielectric layer 128 is formed on the substrate 100. The inter-gate dielectric layer 128 is, for example, a composite dielectric layer in which a ruthenium oxide layer, a tantalum nitride layer, and a ruthenium oxide layer are stacked, and the formation method thereof is, for example, a chemical vapor deposition method. Of course, in other embodiments, the inter-gate dielectric layer 128 may also be a single-layer structure of a dielectric material such as hafnium oxide or tantalum nitride.

Referring to FIG. 1G and FIG. 1H simultaneously, the inter-gate dielectric layer 128, the floating gate 120, and the tunneling dielectric layer 108 of the peripheral region 104 are removed. A gate dielectric layer 130 is then formed over the substrate 100 between the isolation structures 116a of the peripheral region 104. The method of removing the inter-gate dielectric layer 128, the floating gate 120, and the tunneling dielectric layer 108 of the peripheral region 104 is, for example, a dry etching process or a wet etching process. The material of the gate dielectric layer 130 is, for example, ruthenium oxide, and the formation method thereof is, for example, a chemical vapor deposition method. The height difference H5 between the surface 126 of the isolation structure 116a of the peripheral region 104 and the surface 132 of the gate dielectric layer 130 is greater than the height difference H4 between the surface 124 of the isolation structure 114b and the surface 109 of the tunnel dielectric layer 108. .

Referring to FIG. 1I, a conductor layer 134 is formed on the substrate 100 to cover the gate dielectric layer 128 of the memory cell region 102 and the gate dielectric layer 130 and the isolation structure 116a of the peripheral region 104. The conductor layer 134 of the memory cell region 102 serves as a control gate, and the conductor layer 134 of the peripheral region 104 serves as a gate. The material of the conductor layer 134 is, for example, a doped polysilicon, which is formed by, for example, forming an undoped polysilicon layer by chemical vapor deposition, and performing an ion implantation step to form it; or in-situ The method of implanting the dopant is formed by chemical vapor deposition. Thereafter, the following steps of the flash memory are performed, such as forming source and drain regions, contact windows and wires, which are well known to those of ordinary skill in the art and will not be described herein.

In this embodiment, the peripheral layer and the memory cell region adjacent to the peripheral region are covered by the mask layer, so that the isolation structure of the memory cell region and the isolation structure of the peripheral region are removed to different extents. In this way, the surface of the isolation structure of the memory cell is lower than the surface of the isolation structure of the peripheral region, that is, the height difference between the surface of the isolation structure of the memory cell and the surface of the tunnel dielectric layer is greater than the isolation of the peripheral region. The difference in height between the surface of the structure and the surface of the gate dielectric layer. In the memory cell region, since more isolation structures are removed, the floating gate exposes more area, so the contact area between the floating gate and the control gate is increased to increase the gate coupling ratio. . In the peripheral region, since less isolation structure is removed, even if the etching or cleaning process is performed multiple times on the peripheral region, the gate dielectric layer is not exposed, and the degradation of the gate dielectric layer can be avoided. Therefore, the memory element can be made to have good electrical properties. Furthermore, since the surface of the isolation structure located in the memory cell region adjacent to the peripheral region is almost flush with the surface of the isolation structure of the peripheral region, when the conductor layer as the control gate is formed, the conductor layer can be prevented from being located in the memory cell. A spacer effect occurs in the area and adjacent to the surrounding area. In other words, the method of fabricating the flash memory of the present invention can increase the contact area between the floating gate and the control gate, and maintain the integrity of the gate dielectric layer of the peripheral region, so that the flash memory has a high gate. Coupling rate and good electrical properties.

[Second embodiment]

2A to 2C are schematic cross-sectional views showing a part of a method of manufacturing a flash memory in accordance with a second embodiment of the present invention. In the present embodiment, the front-end process of the flash memory is similar to that of FIGS. 1A to 1D and the corresponding description in the first embodiment, and therefore only the steps following FIG. 1D will be described below.

Referring to FIG. 1D and FIG. 2A simultaneously, after the stacked tunneling dielectric layer 108 and the floating gate 120 are formed on the substrate 100 between the isolation structures 114, 114', 116, for example, the isolation structures 114, 114' , 116 is subjected to blanket removal to form isolation structures 114a, 114'a, 116a. Wherein, the surfaces 124, 125, 126 of the isolation structures 114a, 114'a, 116a are higher than the surface 109 of the tunneling dielectric layer 108, and the surfaces 124, 125, 126 of the isolation structures 114a, 114', 116 are, for example, flush There is a first height difference H1 between the surface 109 of the tunneling dielectric layer 108. Methods of comprehensive removal include wet etching or dry etching.

Referring to FIG. 2A and FIG. 2B simultaneously, a mask layer 122 is formed on the substrate 100. The mask layer 122 covers the isolation structure 116a of the peripheral region 104 and the isolation structure 114' located in the memory cell region 102 adjacent to the peripheral region 104. a. The material of the mask layer 122 is, for example, a photoresist.

Then, with the mask layer 122 as a mask, a portion of the isolation structure 114a located in the memory cell region 102 is removed to form the isolation structure 114b. As such, the surface 124 of the remaining isolation structure 114b at the memory cell region 102 is lower than the surface 126 of the isolation structure 116a at the peripheral region 104, except for the isolation structure 114'a adjacent the peripheral region 104. That is, there is still a first height difference H1 between the surface 126 of the isolation structure 116a of the peripheral region 104 and the surface 109 of the tunnel dielectric layer 108, and an isolation structure 114' located in the memory cell region 102 and adjacent to the peripheral region 104. There is still a first height difference H1 between the surface 125 of a and the surface 109 of the tunnel dielectric layer 108, but between the surface 124 of the remaining isolation structure 114b of the memory cell region 102 and the surface 109 of the tunnel dielectric layer 108. There is a second height difference H2 that is less than the first height difference H1.

Please refer to FIG. 2C, and then the mask layer 122 is removed. After the cover layer 122 is removed, the rear-end process of the flash memory of the present embodiment is similar to that of the first embodiment in FIGS. 1G to 1I and the corresponding description thereof, and details are not described herein.

In summary, the cover layer is used to cover the peripheral area and the memory cell area adjacent to the peripheral area, so that the isolation structure of the memory cell area and the isolation structure of the peripheral area are removed to different extents. As a result, the difference in height between the surface of the isolation structure of the memory cell and the surface of the tunnel dielectric layer is greater than the difference in height between the surface of the isolation structure of the peripheral region and the surface of the gate dielectric layer. In the memory cell region, since more isolation structures are removed, the contact area between the floating gate and the control gate can be increased to increase the gate coupling ratio. In the peripheral region, since the isolation structure is removed, the gate dielectric layer can be prevented from being degraded by exposure, and the memory device has good electrical properties. In other words, the method of fabricating the flash memory of the present invention can increase the contact area between the floating gate and the control gate, and maintain the integrity of the gate dielectric layer of the peripheral region, so that the flash memory has a high gate. Coupling rate and good electrical properties.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Base

102. . . Memory cell

104. . . Surrounding area

106. . . Dielectric layer

108. . . Tunneling dielectric layer

109. . . surface

110. . . Mask layer

112. . . ditch

114, 114a, 114b, 114', 114'a, 116, 116a. . . Isolation structure

120. . . Floating gate

122. . . Mask layer

124, 125, 126. . . surface

128. . . Dielectric layer

130. . . Gate dielectric layer

132. . . surface

134. . . Conductor layer

H1, H2, H3, H4, H5. . . Height difference

1A to 1I are schematic cross-sectional views showing the flow of a method of manufacturing a flash memory in accordance with a first embodiment of the present invention.

2A to 2C are schematic cross-sectional views showing a part of a method of manufacturing a flash memory in accordance with a second embodiment of the present invention.

100. . . Base

102. . . Memory cell

104. . . Surrounding area

108. . . Tunneling dielectric layer

109. . . surface

114’a, 114b, 116a. . . Isolation structure

120. . . Floating gate

124, 125, 126. . . surface

128. . . Dielectric layer

130. . . Gate dielectric layer

132. . . surface

134. . . Conductor layer

H4, H5. . . Height difference

Claims (14)

A method of manufacturing a flash memory, comprising: providing a substrate, the substrate comprising a memory cell region and a peripheral region, the substrate having a plurality of isolation structures formed thereon, and the substrate between the isolation structures is formed a first dielectric layer and a floating gate; forming a mask layer on the substrate, the mask layer covering the isolation structures of the peripheral region and the same in the memory cell region and adjacent to the peripheral region An isolation structure; the mask layer is used as a mask to remove a portion of the isolation structures of the memory cell region such that a surface of the isolation structures located in the peripheral region and a surface of the first dielectric layer a first height difference, the first height difference between the surface of the isolation structure located in the memory cell region adjacent to the peripheral region and the surface of the first dielectric layer, and the remaining portion of the memory cell region a surface of the isolation structure and a surface of the first dielectric layer have a second height difference, wherein the first height difference is greater than the second height difference, and the surface of the isolation structures is higher than the first dielectric Surface of the layer; remove the cover Layer; forming a gate on the substrate interlayer dielectric; removing the gate between the peripheral region of the dielectric layer and the plurality of floating gate electrodes; and forming a conductive layer on the substrate. The method for manufacturing a flash memory according to claim 1, further comprising performing blanket removal on the isolation structures after removing the mask layer. The method of manufacturing a flash memory according to claim 2, wherein the method of comprehensive removal comprises a wet etching method or a dry etching method. The method for manufacturing a flash memory according to claim 1, further comprising blanket removing the isolation structures before forming the mask layer. The method of manufacturing a flash memory according to claim 4, wherein the method of comprehensive removal comprises a wet etching method or a dry etching method. The method for manufacturing a flash memory according to the first aspect of the invention, after removing the inter-gate dielectric layer of the peripheral region and the floating gates, further comprising removing the portion of the peripheral region A dielectric layer and a second dielectric layer are formed on the substrate between the isolation structures of the peripheral region. The method for manufacturing a flash memory according to claim 6, wherein a surface of the isolation structures of the peripheral region is higher than a surface of the second dielectric layer, and the isolation structures of the peripheral region are There is a third height difference between the surface and the surface of the second dielectric layer, wherein the third height difference is greater than the second height difference. The method of manufacturing a flash memory according to claim 1, wherein the material of the mask layer comprises a photoresist. The flash memory of claim 1, wherein the material of the isolation structure comprises ruthenium oxide. The flash memory of claim 1, wherein the material of the first dielectric layer comprises ruthenium oxide. The flash memory of claim 1, wherein the material of the second dielectric layer comprises ruthenium oxide. The method for fabricating a flash memory according to claim 1, wherein the materials of the floating gates comprise doped polysilicon. The method of manufacturing a flash memory according to claim 1, wherein the material of the inter-gate dielectric layer comprises yttrium oxide/yttria/yttria. The method of fabricating a flash memory according to claim 1, wherein the material of the conductor layer comprises doped polysilicon.