1253749 15934twf.doc/g 九、發明說明： 【發明所屬之技術領域】 NOR 關於—種快閃記憶體，且特別是有關於一種 ，、人仏體⑽R〜type flash memory)及其製造方法。 【先珂技術】 快閃記憶體元件由於具有可多次進行資料之存入、讀 取、抹除等動作’且存人之資料在斷電後也不會消失之優1253749 15934twf.doc/g IX. Description of the invention: [Technical field to which the invention pertains] NOR relates to a kind of flash memory, and particularly relates to a kind, a human body (10) R~type flash memory) and a manufacturing method thereof. [First-hand technology] Flash memory components have the ability to store, read, erase, etc. multiple times, and the data of the depositor will not disappear after power-off.
點，所以已成為個人電腦和電子設備所廣泛採㈣一種非 揮發性記憶體元件。 圖1是習知一種N〇R型快閃記憶體的俯視圖，而圖2 是圖1的II-II，線的剖面示意圖。 請同時參照圖1與圖2，在基底100内有以y方向交錯排 列的擴散區102與隔離結構1〇4，且在基底1〇〇上有以χ方向 3隔排列的控制間極⑽。而記憶胞中的浮置間極(未奢示）與 牙隧介電層（未繪示）則是位於每一個擴散區1〇2與控制閘極 =重疊的區域110中。除此之外，在控制間極1〇6 一側的擴 散區102可作為源極區1〇8a、另一側的擴散區1〇2則可作為 汲極區108b。而且，通常同一行的汲極區1〇肋是藉由多個接 觸窗112外接到一導線(未繪示）。相較下，同一行的源極區 108a則如圖2所示，是先去除源極區1〇8a中的隔離結構1〇4, 再於其中所暴露出的基底100内形成摻雜區114連接同一行的 源極區108a，最後再經由設置在兩隔離結構1〇4間的一源極 拾起線（source pickup line)116及其中之接觸窗丨18外接到 一導線（未繪示），使源極區108a電性導通。 5Point, so it has become widely used in personal computers and electronic devices (4) a non-volatile memory component. 1 is a plan view of a conventional N〇R type flash memory, and FIG. 2 is a cross-sectional view taken along line II-II of FIG. Referring to Fig. 1 and Fig. 2 at the same time, in the substrate 100, there are diffusion regions 102 and isolation structures 1〇4 which are staggered in the y direction, and a control interpole (10) which is arranged in the χ direction 3 on the substrate 1 。. The floating interpole (not shown) and the tunnel dielectric layer (not shown) in the memory cell are located in the region 110 where each diffusion region 1〇2 and the control gate overlap. In addition, the diffusion region 102 on the side of the control interpole 1 〇 6 can serve as the source region 1 〇 8 a and the diffusion region 1 〇 2 on the other side can serve as the drain region 108 b. Moreover, usually, the first rib of the same row of ribs is externally connected to a wire (not shown) by a plurality of contact windows 112. In contrast, the source region 108a of the same row is as shown in FIG. 2, first removing the isolation structure 1〇4 in the source region 1〇8a, and then forming the doping region 114 in the exposed substrate 100 therein. The source regions 108a of the same row are connected, and finally, a source pickup line 116 disposed between the two isolation structures 1 and 4 and a contact window 18 connected thereto are externally connected to a wire (not shown). The source region 108a is electrically turned on. 5
1253749 15934twf.doc/g 然而，因為上述結構具有很多的接觸窗，所以在設計陣 列結構時需要預留很多連接汲極區的接觸窗面積，導致n〇r 型快閃記憶ft之面積無法進一步縮小，而與目前半導體往小型 化發展的趨勢相違背。 【發明内容】 本發明的目的就是在提供一種N〇R型快閃記憶體，以進 -步縮小陣列面積，同時使記憶體中的每個域傳送距離保 相同。 尽啦明的再-目的是提供一種臓型快閃記憶體的势造 纟卿綱她罐出新賴的 本發明提出-種臟频_題，包括基底、數條控 :;維、數條摻雜區(source/drain d〇ping邮⑹、隔離層： =固=結構、多個浮置·、穿隧介電層與閘間介電層 ί方=二1間極以第一方向排列於基底上、推雜區則以第 之門口 Γ料土底内。再者，隔離層是位於控制閑極和摻雜區 ^間，_結構則位於_區及與控_歸疊以外的 介電於隔離層之間的基底與控_極間、Ϊ隨 测極之間、閘間介電層是位於麵 括設2^2的較佳實_所述_型'_記憶體，更包 ===”她蚊_她卿㈣s_/drain 摻雜區相連窗分別和前述源極歧極連接區内的 6 1253749 15934twf.doc/g 依照本發明的較佳實施例所述NOR型快閃記憶體，上述 之控制閘極與浮置閘極包括多晶矽層、上述之閘間介電層的材 質包括介電質-氮化物-介電質 (dielectric-nitride-dielectric)、上述之隔離層包括由高 密度電梁(high density plasma，HDP)製程所形成的材質層。 依照本發明的較佳實施例所述NOR型快閃記憶體，更包 括位於控制閘極頂部的矽化金屬層。另外，還包括數個位於控 制閘極與浮置閘極的侧壁的間隙壁。 本發明再提出一種NOR型快閃記憶體的製造方法，包括於 一基底中形成以一第一方向排列的數條溝渠隔離結構，再於基 底上形成一穿隧介電層、於穿隧介電層上形成以一第二方向排 列的數條第一導體層，且第一導體層橫跨溝渠隔離結構。接 著，去除第一導體層之間的穿隧介電層，以暴露出部分溝渠隔 離結構，再將暴露出的溝渠隔離結構去除，以暴露出這些溝渠 隔離結構底部的基底。隨後，進行一離子植入製程，以於第一 導體層之間暴露出的基底内形成數個摻雜區。然後，於第一導 體層之間填入一隔離層，並露出第一導體層的頂部，再於基底 上形成一閘間介電層覆蓋第一導體層，然後於閘間介電層上形 成一第二導體層。接著，圖案化第二導體層，以形成呈第一方 向排列的數條控制閘極，之後藉由控制閘極作為罩幕，去除閘 間介電層與底下的第一導體層，以形成數個浮置閘極。 依照本發明的較佳實施例所述NOR型快閃記憶體的製造 方法，上述形成第一導體層之步驟包括先於基底上沈積一第一 多晶矽層，再於第一多晶矽層上形成一氮化矽圖案層，然後以 7 1253749 15934twf.doc/g ϋ夕圖案層為罩幕，侧去除露出的第—多㈣層。而且， 月ίι述氮化矽圖案層可在隔離層填入後被去除。 曰 =㈣喃佳實補所述職顯閃記㈣的製造 導體層之職人隔離層之步驟包括先利用高 山又电水衣耘於基底上沈積一材質層，再利 程磨除材質層，直到露出第—導體層的頂部。之 除部分被磨除的材質層’使材質層的頂 ^ ^ coupllng rati；5 方發二的較佳實施例所述職型快閃記憶體的製造 法’上述形成弟二導體層之步驟包括形成一第二多晶石夕層。 方明的較佳實施例所述NQR型朗記㈣的製曰造 八μ 成子置閉極後更可包括於控制間極上形成一石夕化1253749 15934twf.doc/g However, because the above structure has many contact windows, it is necessary to reserve a lot of contact window area connecting the drain regions when designing the array structure, so that the area of the n〇r type flash memory ft cannot be further reduced. However, it is contrary to the current trend of semiconductor development towards miniaturization. SUMMARY OF THE INVENTION It is an object of the present invention to provide an N〇R type flash memory to further reduce the array area while maintaining the same transmission distance for each domain in the memory. The best thing is to provide a kind of 快-type flash memory. The invention is based on the invention. The invention is based on the invention, including the basis, the number of controls:; Doped region (source/drain d〇ping (6), isolation layer: = solid = structure, multiple floating ·, tunneling dielectric layer and gate dielectric layer ί square = two poles arranged in the first direction On the substrate, the doping area is immersed in the bottom of the soil by the first door. Further, the isolation layer is located between the control idler and the doped area, and the _ structure is located outside the _ area and the control_integration The substrate between the substrate and the control layer, the gate electrode, and the dielectric layer between the gates are located in the surface of the dielectric layer. ===” her mosquitoes _ herqing (four) s_/drain doped zone connection window and the aforementioned source-polar junction connection zone respectively 6 1253749 15934twf.doc / g according to a preferred embodiment of the present invention NOR flash memory The control gate and the floating gate comprise a polysilicon layer, and the material of the inter-gate dielectric layer comprises a dielectric-nitride-dielectric, the isolation layer A material layer formed by a high density plasma (HDP) process. The NOR flash memory according to the preferred embodiment of the present invention further includes a deuterated metal layer on top of the control gate. The method further includes a plurality of spacers on the sidewalls of the control gate and the floating gate. The invention further provides a method for fabricating a NOR-type flash memory, comprising forming a number arranged in a first direction in a substrate. The trench isolation structure further comprises a tunneling dielectric layer on the substrate, and a plurality of first conductor layers arranged in a second direction on the tunnel dielectric layer, and the first conductor layer spans the trench isolation structure. Then, the tunneling dielectric layer between the first conductor layers is removed to expose a portion of the trench isolation structure, and the exposed trench isolation structures are removed to expose the substrate at the bottom of the trench isolation structures. Subsequently, an ion is performed. Implanting process to form a plurality of doped regions in the exposed substrate between the first conductor layers. Then, an isolation layer is filled between the first conductor layers, and the top of the first conductor layer is exposed, and then Forming a gate dielectric layer over the substrate to cover the first conductor layer, and then forming a second conductor layer on the inter-gate dielectric layer. Then, patterning the second conductor layer to form a plurality of controls arranged in a first direction a gate, after which the gate dielectric layer and the underlying first conductor layer are removed by controlling the gate as a mask to form a plurality of floating gates. The NOR flash is described in accordance with a preferred embodiment of the present invention. In the method of manufacturing a memory, the step of forming the first conductor layer comprises: depositing a first polysilicon layer on the substrate, and forming a tantalum nitride layer on the first polysilicon layer, and then using 7 1253749 15934 twf .doc/g The enamel pattern layer is the mask, and the side removes the exposed first (four) layers. Moreover, the month ι 矽 矽 矽 pattern layer can be removed after the isolation layer is filled.曰 = (4) 佳佳实补 The job flash (4) The steps of manufacturing the conductor layer of the conductor layer include first using a mountain and electric water jacket to deposit a material layer on the substrate, and then removing the material layer until the exposure The top of the first conductor layer. The method of forming the second conductive layer of the preferred embodiment of the material layer of the preferred embodiment of the material layer of the preferred embodiment of the present invention includes Forming a second polycrystalline layer. The preferred embodiment of Fang Ming's NQR type Longji (4) is made up of 8μ into the closed pole and can be included in the control pole to form a stone
Hi匕夕卜，上边形成浮置間極後還可包括於控制間極與浮 置閘極的側壁形成數個間隙壁。 、 依照本發_較佳實施綱述㈣型蝴記, 上述形成浮置_後更包括形成和摻綱目連的上ς 明因為採用控制閘極和摻雜區交錯配置的職型伊 降低，且能夠使訊號傳送距離保持相同。此外，本^ 屮Γ二方法可與傳統製程相容’因此不需額外的製程即可制作 出祈穎的NOR型快閃記憶體。 衣作 ::襄本發明之上述和其他目的、特徵和 月頒易k，下文特舉較佳實施例，並配合所附圖二更 8 1253749 15934twf.doc/g 作詳細說明如下。 【實施方式】 第一實施例 圖3是依照本發明之第一實施例的N〇R型快閃記憶體的 俯視圖。圖4-1、圖4-Π、圖4_ΠΙ與圖4_IV則分別是圖3 之Ι_Γ線段、Π —ΙΓ線段、III-III，線段與IV-IV’線段 的剖面示意圖。 δ月同日年茶照圖3與圖4-1、圖4-ΙΙ、圖4-ΙΙΙ和圖4-IV， 本實施例之_独閃峨、縣本上Μ絲·、數條控制 閘極302、數條摻雜區3〇4、隔離層3〇6、數個隔離結構3〇8、 多個淨置閘極31G、穿隨介電層312與閘間介電層314所構 成。其中’控制閘極302以第-方向排列於基底3〇〇上，摻雜 區304則以第二方向排列於基底3〇〇 β，且於本實施例之_ 型快閃記憶體中，摻雜區綱是作為源極與沒極之用。再者， 隔離層306是位於控制閘極3〇2和摻雜區3〇4之間，且隔離層 306例如疋由㈣、度電漿(high density咖，腿製程所 形成的材質層，而隔離結構識則在摻雜區綱及與控制閉極 302重疊以外的基底3〇〇中。此外，浮置間極31〇位於隔離層 306之間的基底300與控制閘極3〇2間，且浮置問極剔例如 是多晶石夕層或其它適合的賴層。穿隧介電層312靠於基底 300與汁置閘極310間，而間間介電層314是位於控制閘極3〇2 與序置雜310之間，其中間間介電層31 質-氮化物-介電質，較佐為氧勝氮化純：： (oxide-nitride-oxide ， ΟΝΟ)。 9 1253749 15934twf. doc/g “立此外，上述結構中呈條狀的摻雜區304可從NOR型快閃 圮憶體向外延伸，以便在記憶體以外的區域設置外接電源的接 觸窗。或者，選擇直接在圖3的結構中設置一些源極與汲極連 接區（source/drain connecting region)316，以便供應電流 到作為源極與汲極的各條摻雜區3〇4，如圖3與圖4—v所示， 其中圖4-V為圖3之V—V，線段的剖面示意圖。 请參照圖3與圖4-V，源極與汲極連接區316是設置於兩 • 控制閘極302之間，且可在覆蓋於基底300上的一層介電層 318中^置一個和源極與汲極連接區316内的摻雜區304相連 之接觸窗320，而上述介電層318通常是在於後續製程期間形 成的；舉例來說，介電層318譬如是内層介電層⑽）。 除此之外，前述有關圖4-IV還可以有另一種結構，如圖 5-IV所示。 曰夕了參知圖5-IV，為了提升導電率，可以在控制閘極3〇2 是夕曰日矽層日$，在其頂部加上一層矽化金屬層3四。另外，於 控制間極310與浮置閘極3〇2的侧壁還可設置間隙壁咖。 •帛二實施例 、、本發明之nor型快閃記憶體的製造流程將於後文中詳 述，但其僅是作為本發明的實施例，而非將本發明限制在 方式。另夕卜，以下所使用的「主要元件符號」如與前面各 圖相同者’則代表相通或類似的元件。 立圖糾至圖㈤-1是圖3之Ι—Γ、線段的製造流程刹面示 心圖- = 6Α〜ΙΙ至圖6Ε-ΙΙ是圖3之11-11，線段的製造流程 口J面不思圖。圖6Α—ΠΙ至圖6Ε—Η〗是圖3之in-Hi，線段 1253749 15934twf.doc/gHi, after forming the floating interpole on the upper side, a plurality of spacers may be formed on the sidewalls of the control interpole and the floating gate. According to the fourth embodiment of the present invention, the above-mentioned formation of the floating _ further includes the formation and the superimposition of the top view, because the control gate and the doped region are alternately arranged, and The signal transmission distance can be kept the same. In addition, the method of the second method can be compatible with the conventional process, so that no additional process can be used to create the NOR flash memory of the eagle. The above and other objects, features and advantages of the present invention are described in detail below with reference to the accompanying drawings and drawings. [Embodiment] FIG. 3 is a plan view showing an N〇R type flash memory according to a first embodiment of the present invention. Fig. 4-1, Fig. 4-Π, Fig. 4_ΠΙ and Fig. 4_IV are schematic cross-sectional views of the Ι_Γ line segment, the Π-ΙΓ line segment, the III-III, the line segment and the IV-IV' line segment of Fig. 3, respectively. On the same day of the same day, the tea is shown in Fig. 3 and Fig. 4-1, Fig. 4-ΙΙ, Fig. 4-ΙΙΙ and Fig. 4-IV. In this example, the _ 峨 峨 , , , , , , , , , , , , , , , 302, a plurality of doped regions 3〇4, an isolation layer 3〇6, a plurality of isolation structures 3〇8, a plurality of clean gates 31G, a pass-through dielectric layer 312, and a gate dielectric layer 314. Wherein the control gates 302 are arranged on the substrate 3〇〇 in the first direction, and the doped regions 304 are arranged in the second direction on the substrate 3〇〇β, and are mixed in the _ type flash memory of the embodiment. The miscellaneous area is used as a source and a rarity. Furthermore, the isolation layer 306 is located between the control gate 3〇2 and the doped region 3〇4, and the isolation layer 306 is, for example, a material layer formed by (4), a plasma (high density coffee, a leg process). The isolation structure is in the doped region and the substrate 3〇〇 other than the control closed-pole 302. Further, the floating interpole 31 is located between the substrate 300 and the control gate 3〇2 between the isolation layers 306. And the floating layer is, for example, a polycrystalline layer or other suitable layer. The tunneling dielectric layer 312 is between the substrate 300 and the juice gate 310, and the interlayer dielectric layer 314 is located at the gate. Between 3〇2 and the ordering impurity 310, the intermediate dielectric layer 31 is a mass-nitride-dielectric, which is more preferably an oxide-nitride-oxide (ΟΝΟ). 9 1253749 15934twf Doc/g "In addition, the strip-shaped doped region 304 in the above structure may extend outward from the NOR type flash memory to provide a contact window of an external power source in a region other than the memory. Alternatively, In the structure of FIG. 3, some source/drain connecting regions 316 are provided to supply current to the ground. The respective doped regions 3〇4 of the source and the drain are as shown in FIG. 3 and FIG. 4—v, wherein FIG. 4-V is a cross-sectional view of the line segment of V-V of FIG. 3. Please refer to FIG. 3 In FIG. 4-V, the source and drain connection regions 316 are disposed between the two control gates 302 and can be connected to the source and drain electrodes in a dielectric layer 318 overlying the substrate 300. The doped region 304 in the region 316 is connected to the contact window 320, and the dielectric layer 318 is typically formed during subsequent processing; for example, the dielectric layer 318 is, for example, the inner dielectric layer (10). The above-mentioned related figure 4-IV can also have another structure, as shown in Fig. 5-IV. In order to improve the conductivity, it is possible to control the gate 3〇2 in the evening. Layer day $, a layer of deuterated metal layer 3 is added on top of the layer. In addition, a gap wall can be disposed on the sidewalls of the control interpole 310 and the floating gate 3〇2. The manufacturing process of the nor-type flash memory will be described in detail later, but it is merely an embodiment of the present invention, and the present invention is not limited to the mode. Used under the "primary element symbols" are the same as the previous figures' is representative of communication elements or the like.立图纠到图(五)-1 is the manufacturing process of the 图-Γ, line segment of the Figure 3, the heart diagram - = 6Α~ΙΙ to Figure 6Ε-ΙΙ is the 11-11 of Figure 3, the manufacturing process of the line segment J side Do not think about it. Figure 6Α—ΠΙ to Figure 6Ε—Η is the in-Hi of Figure 3, line segment 1253749 15934twf.doc/g
的製造流程剖面示意圖。圖6A—R至則e—W 線段的製造流程剖面示意圖。 疋圖3之iv—IV 請同時參照圖6A-1至圖6A—Iv， 以第一方向（如圖3所示）排列物条溝;中先形成 基底300上形成-穿隧介電芦 /、_良、，°構咖，再於 且第ί導^排列的數條第-導體層， 且弟¥脰層610檢跨溝渠隔離結構6〇8，而 在基底300上沈積一層多晶矽層，再於 口疋 石夕圖荦声，之德以気a於回也 、日日夕層上形成一氮化 : 後域侧層為罩幕，崎除露出的多晶 接著，請同時參照圖啊至圖 610之間的穿隧介電声，、舌除弟一導體層 爯將吴#+ 、巨9 *路出部分溝渠隔離結構608， 再將恭路出的美隔離結構_去除。此時，遺留 隔離結構即為第一實施例的隔離結構3 二： 溝渠隔離結構_底部的基底· 被去除的 -離子植人制㈣9 會被暴露出來。隨後，進行 離子植入衣& 612,以於第一導體層_ 300内形成數個推雜區綱。而在這-組圖式戶 === 間’圖f之1V—IV’線段的剖面圖則仍如圖6A-IV-樣，只是 =標示為608的整條溝渠隔離結構因為被去除掉一部分:而 成為隔離結構308。 然後，請_參關6C—1至® 6CMII，於第—導體層61〇 之間填入-隔離層3G6，並露出苐—導體層61() _部，曰而埴 入隔离ί層·的方法例如是糊締度電Μ程於基底·、 Λ材貝層’再利用化學機械研磨製程磨除材質層，直到 1253749 15934tvvf.doc/g 露出第-導體層610的頂部。此外，如果在前面形成第一導體 層610的時候有用一層氮化矽圖案層作為罩幕，則可選 =Schematic diagram of the manufacturing process. Fig. 6A is a schematic cross-sectional view showing the manufacturing process of the line segment from the R to the e-W. Referring to FIG. 6A-1 to FIG. 6A-Iv, the strip grooves are arranged in the first direction (as shown in FIG. 3); the first substrate 300 is formed on the substrate 300 to form a tunneling dielectric reed/ , _ 良 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In the mouth of the 夕 夕 夕 荦 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The tunneling dielectric sound between Figure 610, the tongue and the conductor, the conductor layer, and the Wu #+, Ju 9 * road part of the trench isolation structure 608, and then remove the beautiful isolation structure _. At this time, the legacy isolation structure is the isolation structure 3 of the first embodiment. 2: The trench isolation structure _ the bottom substrate · the removed - ion implantation system (4) 9 will be exposed. Subsequently, an ion implant coating & 612 is performed to form a plurality of dummy regions in the first conductor layer _300. In the case of this group of graphs, the sectional view of the 1V-IV' line of Fig. f is still as shown in Fig. 6A-IV, except that the entire trench isolation structure labeled 608 is removed. : becomes the isolation structure 308. Then, please refer to 6C-1 to ® 6CMII, fill the isolation layer 3G6 between the first conductor layer 61〇, and expose the germanium-conductor layer 61() _ portion, and then enter the isolation layer The method is, for example, a paste-to-battery process in which the material layer is removed by a chemical mechanical polishing process until the top of the first conductor layer 610 is exposed to 1253749 15934tvvf.doc/g. Further, if a layer of tantalum nitride pattern is used as a mask when forming the first conductor layer 610 in front, it is optional =
入隔離層306後將其去除。此時，在圖3之my,綠 ^ 面圖則仍如圖6A-IV—樣。 、夕又勺口丨JAfter the isolation layer 306 is inserted, it is removed. At this time, in the my of Fig. 3, the green surface map is still as shown in Fig. 6A-IV. , and the spoon is 丨J
，後，_時參關6ΙΜ至關_IV，如果要增加開極 搞S率(购C0Upling ratio，GCR)，可選擇先移除部分被 除的材質層（亦即隔離層_，使材f層的頂部低於第 層610的頂部。接著，於基底·上形成_閉間介電芦、 覆蓋第-導體層61G，且其步驟例如包括形成氧化物:氮化 物-氧化物層。然後，於閘間介電層314上形成一第辦 602，而形成第二導體層6〇2之步驟例如包括形成一層多晶ς J^y rs / 接著，請同時參照圖6E-II至圖6E-IV，圖案化第卿 層602 ’以形成呈第一方向排列的數條控制問極3〇2，之二 由控制_观作為罩幕，去除閘間介電層314與底下的^ 導體層610 ’以形成數個浮置閘極31〇。此時，在圖3之卜^ 線段的剖面圖則仍如圖6D-I —樣。 ^夕卜’本實施例之製造流程尚有其它選擇性的步驟。舉 =’可參照前面第-實施例的圖5—IV，在形成浮置閘極3ι〇 後’於控_極302上形成-魏^金屬層微，以提升導電率 =，形成浮置閘極310之後也可於控制閘極3〇2與浮置開極 310的側壁形成間隙壁324。 另外，為使說明書簡單明瞭，請參照前面第一實施例的 V，在形成浮置閘極後可在基底300上形成-内層介電層 12 1253749 318，之後於内層介電層3i8中形成與摻雜區3〇4相連的接觸 窗 320。 综上所述，本發明之特點在於採用控制閘極和摻雜區交 錯配置的NOR型快閃記憶體，所以可大幅降低記憶體之陣列面 牙貝而且遂此夠使成號傳送距離保持相同。此外，本發明的製 程可與傳統製程相容，因此不需額外的製程即可製作出本發明 之NOR型快閃記憶體。 —雖然本發明已以較佳實施例揭露如上，然其並非用以限 疋本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍 内，當可作些許之更動與潤飾，因此本發明之保絲圍當視後 附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是習知-種NOR型快閃記憶體的俯視圖。 圖2是圖1的Π-ΙΓ、線的剖面示意圖。 的俯^ (依照本發明之—較佳細_ NQR雜閃記憶體 圖 4—I、圖 4—II、圖 4—ΙΠ 之 I —Γ 線段、II-π，^ 圖3之1-1， 線段與V-V’ 與V-V’線段的剖面示意圖 圖5-IV是圖4-IV 圖6A-1至圖6D-I ;, after, _ 参 ΙΜ ΙΜ ΙΜ ΙΜ ΙΜ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The top of the layer is lower than the top of the first layer 610. Next, an inter-closed dielectric reed is formed on the substrate, covering the first conductor layer 61G, and the steps thereof include, for example, forming an oxide:nitride-oxide layer. A first 602 is formed on the inter-gate dielectric layer 314, and the step of forming the second conductive layer 〇2 includes, for example, forming a layer of polysilicon J^y rs / Next, please refer to FIG. 6E-II to FIG. 6E simultaneously. IV, patterning the second layer 602' to form a plurality of control electrodes 3〇2 arranged in the first direction, and the second is controlled by the control_view to remove the inter-gate dielectric layer 314 and the underlying conductive layer 610. 'To form a plurality of floating gates 31 〇. At this time, the cross-sectional view of the line segment of Fig. 3 is still as shown in Fig. 6D-I. ^ 卜 ' 'The manufacturing process of this embodiment has other options Step = ' can refer to Figure 5 - IV of the previous embodiment - after forming the floating gate 3 〇 , forming a - Wei ^ metal layer micro on the control electrode 302 After the floating gate 310 is formed, the gap 324 may be formed on the sidewalls of the control gate 3〇2 and the floating open pole 310. In addition, for the sake of simplicity, please refer to the foregoing first embodiment. V, after forming the floating gate, an inner dielectric layer 12 1253749 318 may be formed on the substrate 300, and then a contact window 320 connected to the doping region 3〇4 is formed in the inner dielectric layer 3i8. As described above, the present invention is characterized in that the NOR type flash memory for controlling the staggered arrangement of the gate and the doped region is used, so that the array of the memory of the memory can be greatly reduced and the transmission distance of the number can be kept the same. The process of the present invention can be compatible with conventional processes, so that the NOR-type flash memory of the present invention can be fabricated without an additional process. - Although the present invention has been disclosed above in the preferred embodiment, it is not intended to be limiting. In the present invention, those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the present invention is defined by the scope of the patent application. [Figure BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a conventional NOR type flash memory. Fig. 2 is a cross-sectional view of the Π-ΙΓ and line of Fig. 1. (In accordance with the present invention - preferably fine _ NQR flash Memory Figure 4 - I, Figure 4 - II, Figure 4 - I I Γ line segment, II-π, ^ Figure 1-1, line segment and V-V' and V-V' line segment schematic diagram 5-IV is Figure 4-IV Figure 6A-1 to Figure 6D-I;
Hi、圖4-IV與圖4-V則分別是 線段、III-III，線段、IV-IV， 意圖。 圖 6A-II 至圖 6E-II 面示意圖。Hi, Fig. 4-IV and Fig. 4-V are line segments, III-III, line segments, IV-IV, respectively. Figure 6A-II to Figure 6E-II are schematic views.
疋圖3之Π-Π’線段的製造流程剖 1253749 15934twf.doc/g . 圖6A-III至圖6E-III是圖3之III-ΙΙΓ線段的製造流 程剖面示意圖。 圖6A-IV至圖6E-IV是圖3之IV-IV’線段的製造流程剖 面示意圖。 【主要元件符號說明】 100、300 :基底 102 :擴散區 104、308 :隔離結構 106、302 :控制閘極 108a :源極區 108b ·>及極區 112、118、320 :接觸窗 114、304 :摻雜區 116 :源極拾起線 306 :隔離層 310 :浮置閘極 • 312 :穿隧介電層 314 :閘間介電層 316 :源極與汲極連接區 318 :介電層 322 :破化金屬層 324 :間隙壁 602、610 :導體層 608 :溝渠隔離結構 612 :離子植入製程 14Fig. 3 is a cross-sectional view showing the manufacturing process of the ΙΙΓ-Π' line segment of Fig. 3; Fig. 6A-III to Fig. 6E-III are schematic cross-sectional views showing the manufacturing process of the III-ΙΙΓ line segment of Fig. 3. 6A-IV to 6E-IV are schematic cross-sectional views showing the manufacturing flow of the line IV-IV' of Fig. 3. [Main component symbol description] 100, 300: substrate 102: diffusion regions 104, 308: isolation structure 106, 302: control gate 108a: source region 108b · > and polar regions 112, 118, 320: contact window 114, 304: doped region 116: source pick-up line 306: isolation layer 310: floating gate • 312: tunneling dielectric layer 314: gate dielectric layer 316: source and drain connection region 318: dielectric Layer 322: broken metal layer 324: spacers 602, 610: conductor layer 608: trench isolation structure 612: ion implantation process 14