200818407，2i_wfdoc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體結構的製造方法，且特 是有關於一種隔離結構的製造方法。 ' 【先前技術】 在各種非揮發性記憶體產品中，具有可進行多次次 之存入、讀取、抹除等動作，且存人之資料在斷電二 會消失之優點的可電抹除且可程式唯咅骑 (ΕΕΡΚΌΜ)’已成為個人電腦和電子設備廣 種非揮發性記憶體。 K㈣的- 矽且可程式唯讀記憶體係以摻雜的多晶 夕衣作斤置閘極(floatmg gate)與控制閘極(c〇咖i g 一 般來說’浮置閘極與控制閘極之間的閘極耦合率 =舊phng rati0，GCR)愈大，其操作所需之工作電壓 將，低，，而記憶_操作速度與效率會隨之提升。由於 = 置閘極、控制閘極之間的電容值與記憶體 ί率’因此，增加浮置閘極與控制閘極之間的 專效电谷面積，將有助於增加閘極耦合率。 —然而在積體電路持續追求高積集度之趨勢下，記情體 :隨卻因而必須縮減’元件的線寬同 耦人皇Γ公σ 一來，净置閘極與控制閘極之間的閘極 11纽著下降，_發性記龍 ^被迫提高。輯於_揮發性讀 = 的可攜式電子產品職，相當地不利。lb而求 此外由於每個讀胞之間的距離縮短，因此，在操 2008184079 η。84—— 作選定之記憶胞的時候，容易導致選定記憶胞之浮置閘極 與周圍其他記憶胞的浮置閘極產生耦合效應，使得選定記 憶胞的啟使電壓差值提高改變，很容易導致操作上的可土 度下降，影響元件的效能。 # 【發明内容】 有鑑於此，本發明的目的就是在提供一種隔離結 製造方法，可續低較記憶胞之浮置· 的浮置閘極所產生_合效應。 ^己胞200818407, 2i_wfdoc/e IX. Description of the Invention: TECHNICAL FIELD The present invention relates to a method of fabricating a semiconductor structure, and more particularly to a method of fabricating an isolation structure. [Prior Art] Among various non-volatile memory products, there are rewritable devices that can perform multiple times of depositing, reading, erasing, etc., and the data of the depositor disappears in the second power-off. In addition, the program can only be used as a non-volatile memory for personal computers and electronic devices. K(4) - 可 and programmable read-only memory system with doped polycrystalline hood as a floatmg gate and control gate (c〇 ig generally 'floating gate and control gate The greater the gate coupling ratio = the old phng rati0, GCR), the lower the operating voltage required for its operation, and the higher the memory speed and efficiency. Since = the gate and the gate between the control gate and the memory ’ rate, increasing the area of the dedicated valley between the floating gate and the control gate will help increase the gate coupling ratio. - However, in the trend that the integrated circuit continues to pursue high accumulative power, the sensation body: it must therefore reduce the line width of the component with the coupling of the Γ Γ ,, between the net gate and the control gate The gate of the gate 11 is falling, and the _ hair sex dragon ^ is forced to improve. In the portable electronic product category of _ volatile reading =, it is quite unfavorable. In addition, because the distance between each cell is shortened, therefore, in 2008184079 η. 84—— When the selected memory cell is used, it is easy to cause the floating gate of the selected memory cell to have a coupling effect with the floating gates of other memory cells around it, so that the difference in the threshold voltage of the selected memory cell is changed, which is easy. This results in a decrease in the soilability of the operation and affects the performance of the component. In view of the above, it is an object of the present invention to provide a method for fabricating an isolation junction which can continue to produce a _ combining effect which is lower than that of a floating gate of a memory cell. Self
本發明的再-目的是提供—麵雜構的製造， 可以提高記憶胞之閘極耦合率。 、 / ， 本發明提出-種隔離結構的製造方法 基底上設置有一層介電層與一導體層，導== 導Γ、介電層與基底中設置有隔離層。^ 然後，於導體層側壁形成—間隙壁。之 土為罩幕，移除部分隔離 m 頂部具有-凹陷，且隔二 & _結構，隔離結構 之轉角處。接著於形成隔離二4父界 上述隔離結構的製造方、^後雜間隙壁。 陷。 、方去中’凹陷可以是-圓弧狀凹 上述隔離結構的製造方法 部分隔離層的方法包括濕、柄刻法。n為罩幕’移除 上述隔離結構的製造古山 乾式勤j法祕式_法Μ，雜__方法包括 200818407) 2iQ84twfd(K/e 上述隔離結構的製造、 先於基底上形成一間隙^会中，間隙壁的形成方法包括 上述隔離結構的製 的方法包括乾式银刻法 造方法中 料層，留下位於導體層二j料層，然後移除部分間隙壁材 - 曰太之間隙壁材料層。 ’移除部分間隙壁材料層 上述隔離結構的製造 矽。隔離層的材質包括$去中’間隙壁的材質包括氮化 晶矽。 氣化石夕。導體層的材質包括掺雜多A further object of the present invention is to provide a fabrication of a facet structure which can increase the gate coupling ratio of a memory cell. The present invention provides a method for fabricating an isolation structure. A dielectric layer and a conductor layer are disposed on the substrate, and the isolation layer is disposed in the dielectric layer and the substrate. ^ Then, a spacer is formed on the sidewall of the conductor layer. The soil is a mask, and the part of the isolation m is removed. The top of the m is a recessed, and the second and the _ structure are at the corners of the isolation structure. Then, the manufacturing side of the isolation structure and the rear spacer are formed. trap. , the square to the 'depression can be - arc-shaped concave manufacturing method of the above isolation structure Part of the isolation layer method includes wet, shank engraving. n is the mask 'removal of the above-mentioned isolation structure. The ancient mountain dry type j-method _ method, miscellaneous __ method includes 200818407) 2iQ84twfd (K / e above the isolation structure manufacturing, before the substrate to form a gap ^ will The method for forming the spacer wall includes the method for fabricating the above-mentioned isolation structure, including the material layer in the dry silver engraving method, leaving the material layer in the conductor layer, and then removing part of the spacer material - the spacer material of the 曰太Layer. 'Removal of part of the spacer material layer. The above-mentioned isolation structure is manufactured. The material of the isolation layer includes the material of the "going to" spacer. The material of the spacer includes cerium nitride. The material of the conductor layer includes the doping.
的製程丄其中之導體層“===發性記憶體 上述隔離結才冓的製造方法， 包括提供一 从=提出另-種隔離結二製：：tr i介置有—層介電層與—層導體層，導體層位 接—电S」且導體層、介電層與基底中設置有隔離層。 曰ί、=除部分隔離層，使隔離層的頂面低於導體層頂面 體層底面。之後，於基底上形成-層間隙壁材料 a 、、k而移除部分間隙壁材料層，形成位於導體層侧壁之 間隙壁。缺ί么 ^ ^ “、、後’至少移除部分隔離層，形成隔離結構，隔 離、、°構頂部具有一凹陷，且隔離結構覆蓋住導體層盥介電 層交界之轉角處。 … 上述隔離結構的製造方法中，凹陷可以是一圓弧狀凹 陷0 上述隔離結構的製造方法中’間隙壁與隔離層具有不 同的蝕刻選擇比。 上述隔離結構的製造方法中，更包括以間隙壁為罩 200818407> 2i_wfd〇c/e 幕，移除部分隔離層。而σ、 層的方法包括濕式_法。s::縣罩幕’移除部分隔離 上述隔離結構的製41、+ + 矽 之後，移除間隙壁。法中’更包括於形成隔離結構 上述隔離結構的製造方法中’間隙壁的材質包括氮化 略相同的蝕刻選擇比 的步驟中於形成隔離結構 隔離中’同時移除間隙壁與部分 去勺隔製造方法中，形成間隙壁材料層的方 法^以四乙基挪_TEOS)為氣體源，進行化學氣 積法。 上述隔離結構的製造方法中，移除部分間隙壁 層，形成間隙壁的方法包括乾式蝕刻法。 上述隔離結構的製造方法中，隔離層的材質包括氧化 矽。導體層的材質包括摻雜多晶矽。 上述隔離結構的製造方法，適用於非揮發性記憶體的 製程，其中導體層為非揮發性記憶體之浮置閘極。 本發明提出之隔離結構的製造方法，由於移除了部分 隔離層，因此可以加大浮置閘極與後續形成之控制閉極之 間的等效電容面積，進而提高閘極耦合率，以降低記憶體 200818407 21084twf.d〇c/e 的操作電壓。此外，由於降低了㈣浮置閘極之間的 結構高度，還可以減輕浮置閘極之間的耦合效應，縮“ 憶，的啟使電壓差值，進一步提高記憶體的可;度;整二 為讓本發明之上述和其他目的、特徵和優點能更明 易懂，下文特舉實施例，並配合所附圖式，作詳細說明= 下。 【實施方式】 圖1A至圖1D是繪示本發明一實施例之—種隔離結 的製造方法。 明參照圖1A，本實施例所提出之隔離結構的製造方法 是應用於非揮發性記憶體的製造過程，其例如是先提供基 底1〇〇，於基底100上依序形成一層介電層11〇與一層罩 幕層（未繪示）。基底100例如是矽基底。介電層11〇的 材質例如是氧化矽，其形成方法例如是化學氣相沈積法。 罩幕層的材質例如是氮化矽，其形成方法例如是化學氣相 沈積法。 之後’於罩幕層、介電層110與基底100中形成多個 溝渠115。溝渠115的形成方法例如是利用微影蝕刻製程， 移除部分罩幕層、介電層u〇與基底1〇〇而形成溝渠n5。 而後，於溝渠115中填滿隔離層120。隔離層120的 材質例如是氧化矽，其形成方法例如是先以高密度電漿化 學氣相沈積法於基底100上形成一層隔離材料層（未繪 示）’並以罩幕層為終止層，平坦化隔離材料層以形成之。 9 200818407' 21084tw£doc/< 、蓄Μ Ϊ後，移除罩幕層，而於隔離層12G之間的間隙填滿 Vm a 30。導體層13〇的材質例如是摻雜多晶矽，其形 例如是先於基底1〇〇上形成一層共形的導體材料層 (未心不），之後以隔離層12〇為終止層，利用化學機械 研磨製程，平坦化導體材料層。 在-實施例中，也可以以其他方法來形成如圖认之 、、-構例如是先依序形成介電層11()、導體材料層與罩幕 層，然後移除部分罩幕層、導體材料層、介電層n〇與基 底’形成溝渠115。之後再填入隔離層12〇。而後以導 體層m為終止層，移除罩幕層與部分隔離層12G。當然， 上述形成如圖1A之結構的方法，還可以依製程的設計而 有不同，上述實施例並非用以限定本發明。 繼而，請參照圖1B，移除部分隔離層12〇，使隔離層 12〇的頂面低於導體们3〇 了頁面但高於導體| 13〇底面。 移除部分隔離層12〇的方法例如是回蝕刻法，如濕式蝕刻 法，乾式蝕刻法。在一實施例中，導體層13〇的厚度A例 =疋60nm，剩餘之隔離層120的頂面與導體層13〇頂面的 高度差W(即隔離層120所移除的厚度w)例如是4〇nm。 隔離層120被移除的厚度可以是利用濕式蝕刻法，依照蝕 刻的時間來控制。 之後，在基底100上形成一層共形的間隙壁材料層 135。間隙壁材料層135的材質例如是氮化矽、碳化矽、氮 碳化妙等，與隔離層120具有不同蝕刻選擇比的材質。其 形成方法例如是化學氣相沈積法。 、/、 200818407》2i〇84twfd〇c/e 接著，請參照圖lc，移除 形成位於導體層130側壁的 ]隙土材料層135，而 材料層135的方法例如是乾式8蝕14〇。移除部分間隙壁 隔離層120，形成隔離結構為罩幕’移除部分 法，== 液，其對於隔離層二:：口:用氫氟酸等钱刻 130的高度。 料體層130,而維持導體層 曰□;=構150的頂部具有凹陷155，此凹陷155例如 疋圓弧狀的凹陷155，而俅得p雜从 住導髀厣命人使^離結構5〇的侧壁會覆蓋 住V體層13〇與介電層11〇交 可以避免導體# 130 Π心角處故麼一來，也 /㈣日130 (㊉置閘極）發生漏電流的問題。 而後再以乾式兹刻法或濕式姓刻法移除間隙壁 140’裸露出導體層13〇的側壁，以便於進行後續非揮發性 記憶體的其他製程。後續完成非揮發性記憶體的製程應為 熟知本技術領域者所週知，於此不再贅述。 ^ 在一貫施例中，上述導體層13()的高度Α例如是 60nm，移除間隙壁14〇，之後，導體層13〇裸露出的侧壁高 度f例如是4〇nm，而隔離結構頂面中央與基底1〇〇頂面 的高度差D例如為10nm。 與習知技術相比，本實施例中由於移除了部分隔離層 120 ’使得高度B得以增加，則浮置閘極（導體層130)與 11 200818407 2i〇84twfd〇c/e 後縯形成之控咖極之間的等效電容面積也會加大 於閘極_合率的提高；而於隔離結構15G頂部形成凹陷 =5 低高度差D，則可以減輕相鄰之浮置閘極之間的麵 &政應’縮小域胞之啟使電_差值 的可靠度與整财能。 再者，由於本實施例所使用之間隙壁材料層i35，盥 隔離層120具有極佳的侧選擇比，因此在移^部分隔離 層120，形成隔離結構150的步驟中，可以有效地保 # 體層13〇,使導體層130不受侵餘，而得以維持導體芦13〇 (浮置閘極）的高度。 ^ ° 圖2Α至圖2C是緣示依照本發明另一實施例之隔離結 構的製造流程剖面圖。圖2Α至圖2C是接續於上述圖^ 的製程。 、囚ία 請參照圖2Α，於形成導體層130之後，移除部分隔離 層120。移除的方法例如是回蝕刻法，如乾式蝕刻法^濕 式蝕刻法。而在本實施例中，導體層13〇的厚度Α例如是^ 60nm，剩餘之隔離層120’的頂面與導體層13〇&面的高^ 差W’，亦即所移除之隔離層120的厚度W，例如是3〇nm^ 而隔離層120被移除的厚度可以利用濕式蝕刻法，^ 刻的時間來控制。 之後，在基底100上形成一層共形的間隙壁材料声 135。在本貫施例中’間隙壁材料層135,例如是選用氧化 矽等，與隔離層120’具有約略相同或相似之蝕刻選擇比的 材質。在一實施例中，間隙壁材料層135,例如是以四乙美 12 200818407 )21084twf.doc/e 石夕酸酯(TEOS)為氣體源，進行化學氣相沈積製程所形成 的，而所形成的間隙壁材料層的厚度例如是20nm。 繼而，請參照圖2B，移除部分間隙壁材料層135’，而 形成位於導體層130側壁的間隙壁140’。移除部分間隙壁 材料層135’的方法例如是乾式蝕刻法。在一實施例中，間 隙壁140’的高度例如是30nm，而隔離層120,頂面與基底 100頂面之高度差D’例如是30nm。 之後，請參照圖2C，利用回餘刻法移除間隙壁14〇, 與部分隔離層120’，而形成隔離結構150。移除間隙壁14〇, 與部分隔離層120’的方法例如是以氫就酸為姓刻液，進行 濕式蝕刻法。隔離層120’頂部移除之後，其頂面與基底i〇〇 頂面之高度差D’也會隨之降低。 回蝕刻的結果將於隔離結構150頂部形成凹陷155， 此凹陷155可以是呈圓弧狀的，而隔離結構150的側壁會 覆蓋住導體層130與介電層110交界之轉角處。從而得以 降低導體層130 (浮置閘極）發生漏電流的問題。 在一實施例中，上述導體層130的高度A例如是 60nm，導體層130裸露出的側壁高度B例如是40nm，而 隔離結構頂面中央與基底100頂面的高度差D，則為i〇nm。 在本實施例中’由於間隙壁材料層135’的材質與隔離 層120’的材質具有約略相同的蝕刻選擇比，因此，於形成 隔離結構150的步驟中，可以同時移除部分隔離層12〇,以 及間隙壁140’，而可以省去另行移除間隙壁14〇,的步驟。 值得一提的是，上述實施例雖然是以非揮發性記憶體 13 200818407 2i〇84twfd〇c/e 白、衣程為例來說明，然其並非用以限定本發明，此種 結構1製造方法，當然也可㈣在其他半導體製程中^離 綜上所述，本發明提出之隔離結構的製造方法 移除了部分隔_，可以加大浮㈣極與後續形:於 控制閘極之間的等效電容面積，進而提高辭域合率，之 P牛低體的操作電壓。此外，由於凹陷155的形成，乂 低I浮置閘極與浮置閘極之間的隔離結構高度，還可以= 幸二浮置閘極之間的耦合效應，縮小記憶胞的啟使電壓差 值，進一步提高記憶體的可靠度與整體效能。 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明’任何所屬技術領域中具有通常知識者，在不脫離 本發明之精神和範圍内，當可作些許之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 圖1A至圖1D是繪示本發明一實施例之一種隔離結構 的製造流程剖面圖。 圖2A至圖2C是繪示本發明另一實施例之一種隔離結 構的製造流程剖面圖。 【主要元件符號說明】 100 ·基底 no :介電層 115 ·溝渠 120、120’ ：隔離層 200818407 21084twf.doc/e 130 :導體層 135、135’ ：間隙壁材料層 140、140’ ：間隙壁 150 :隔離結構 155 :凹陷 A:導體層高度 B:導體層裸露出的側壁高度 D、D’ ：隔離結構頂面中央與基底頂面的高度差 W、W’ ：隔離層所移除的厚度 15The manufacturing process of the conductor layer "=== hair memory, the above-mentioned isolation method, including providing a slave = another isolation type two system:: tr i interposed with - dielectric layer and - a layer of conductor layers, the conductor layer is connected to the electrical S" and the conductor layer, the dielectric layer and the substrate are provided with an isolating layer.曰ί, = In addition to the partial isolation layer, the top surface of the isolation layer is lower than the bottom surface of the top layer of the conductor layer. Thereafter, a layer of spacer material a, k is formed on the substrate to remove a portion of the spacer material layer to form a spacer on the sidewall of the conductor layer.缺 么 ^ ^ ", after 'removing at least part of the isolation layer, forming an isolation structure, isolation, the top of the structure has a depression, and the isolation structure covers the corner of the junction of the conductor layer and the dielectric layer. In the manufacturing method of the structure, the recess may be a circular arc-shaped recess. 0 In the manufacturing method of the above-mentioned isolation structure, the spacer has a different etching selectivity than the spacer. In the manufacturing method of the above-mentioned isolation structure, the spacer is also covered. 200818407> 2i_wfd〇c/e screen, removing part of the isolation layer. The method of σ, layer includes wet_method. s:: county mask 'removing part of the isolation of the above-mentioned isolation structure 41, + + ,, Removing the spacers. The method is further included in the method of fabricating the isolation structure described above. The material of the spacers includes the step of nitriding the same etching selectivity in the step of forming the isolation structure isolation while removing the spacers. In the partial scooping method, a method of forming a spacer material layer is performed by using tetraethyl fluoro-TEOS as a gas source, and a chemical gas accumulation method is performed. The method for removing a part of the spacer layer and forming the spacer layer comprises a dry etching method. In the method for fabricating the isolation structure, the material of the isolation layer comprises yttrium oxide. The material of the conductor layer comprises doped polysilicon. The manufacturing method of the above isolation structure, The invention is applicable to a process of non-volatile memory, wherein the conductor layer is a floating gate of a non-volatile memory. The method for manufacturing the isolation structure proposed by the present invention can increase the floating gate by removing part of the isolation layer. The equivalent capacitance area between the pole and the subsequently formed controlled closed pole, thereby increasing the gate coupling ratio to reduce the operating voltage of the memory 200818407 21084twf.d〇c/e. In addition, since the (four) floating gate is lowered The structural height between the two can also alleviate the coupling effect between the floating gates, reduce the voltage difference of the threshold, and further improve the memory; the second is to make the above and other purposes of the present invention, The features and advantages will be more apparent and understood. The following detailed description of the embodiments, together with the drawings, will be described in detail below. [Embodiment] Figs. 1A to 1D are views showing a method of manufacturing an isolation junction according to an embodiment of the present invention. Referring to FIG. 1A, the manufacturing method of the isolation structure proposed in this embodiment is applied to a manufacturing process of a non-volatile memory, for example, a substrate 1 is first provided, and a dielectric layer 11 is sequentially formed on the substrate 100. 〇 and a layer of mask (not shown). The substrate 100 is, for example, a crucible substrate. The material of the dielectric layer 11A is, for example, ruthenium oxide, and the formation method thereof is, for example, chemical vapor deposition. The material of the mask layer is, for example, tantalum nitride, and the formation method thereof is, for example, chemical vapor deposition. Thereafter, a plurality of trenches 115 are formed in the mask layer, the dielectric layer 110, and the substrate 100. The trench 115 is formed by, for example, using a photolithography process to remove a portion of the mask layer, the dielectric layer, and the substrate 1 to form a trench n5. The trench 120 is then filled in the trench 115. The material of the isolation layer 120 is, for example, ruthenium oxide, which is formed by, for example, forming a layer of isolation material (not shown) on the substrate 100 by high-density plasma chemical vapor deposition and using the mask layer as a termination layer. The layer of isolating material is planarized to form it. 9 200818407' 21084tw£doc/<, after the Μ, the mask layer is removed, and the gap between the spacers 12G is filled with Vm a 30. The material of the conductor layer 13 is, for example, a doped polysilicon, which is formed, for example, by forming a conformal layer of conductive material on the substrate 1 (uncentered), and then using the isolation layer 12 as a termination layer, using chemical machinery. The polishing process planarizes the layer of conductor material. In the embodiment, the method can also be formed by other methods, for example, the dielectric layer 11 (), the conductive material layer and the mask layer are sequentially formed, and then the partial mask layer is removed. The conductor material layer, the dielectric layer n〇 and the substrate 'form a trench 115. Then fill in the isolation layer 12〇. Then, the conductor layer m is used as the termination layer, and the mask layer and the portion of the isolation layer 12G are removed. Of course, the above-described method of forming the structure of FIG. 1A may also be different depending on the design of the process, and the above embodiments are not intended to limit the present invention. Then, referring to Fig. 1B, a portion of the spacer layer 12 is removed such that the top surface of the spacer layer 12 is lower than the conductors but is higher than the bottom surface of the conductor | 13 . The method of removing a part of the spacer layer 12 is, for example, an etch back method such as a wet etching method or a dry etching method. In one embodiment, the thickness A of the conductor layer 13 例 = 疋 60 nm, and the height difference W between the top surface of the remaining isolation layer 120 and the top surface of the conductor layer 13 (ie, the thickness w removed by the isolation layer 120) is, for example, It is 4〇nm. The thickness at which the spacer layer 120 is removed may be controlled by wet etching according to the time of etching. Thereafter, a layer of conformal spacer material 135 is formed on substrate 100. The material of the spacer material layer 135 is, for example, tantalum nitride, tantalum carbide, niobium carbide, or the like, and has a different etching selectivity ratio from the spacer layer 120. The formation method is, for example, a chemical vapor deposition method. /, 200818407" 2i 〇 84 twfd 〇 c / e Next, referring to Figure lc, the formation of the layer of material 135 on the sidewall of the conductor layer 130 is removed, and the method of the material layer 135 is, for example, a dry etch. Part of the spacer isolation layer 120 is removed to form the isolation structure as a mask 'removal portion method, == liquid, which is for the isolation layer 2:: port: the height of 130 with hydrofluoric acid. The body layer 130, while maintaining the conductor layer ; □; = the top of the structure 150 has a recess 155, such as the 疋 疋 arc-shaped recess 155, and the 杂 p 杂 从 从 从 从 髀厣 髀厣 髀厣 使 使 使 使 使 使The sidewalls cover the V body layer 13 and the dielectric layer 11 can avoid the problem of leakage current at the center of the conductor #130, and / (4) 130 (ten gate). The sidewalls of the spacers 140' exposed conductor layer 13A are then removed by a dry pattern or a wet pattern to facilitate subsequent processing of the non-volatile memory. The subsequent completion of the process of non-volatile memory should be well known to those skilled in the art and will not be described again. ^ In a consistent embodiment, the height Α of the above conductor layer 13 () is, for example, 60 nm, and the spacer 14 移除 is removed, and then the exposed sidewall height f of the conductor layer 13 例如 is, for example, 4 〇 nm, and the isolation structure top The height difference D between the center of the face and the top surface of the substrate 1 is, for example, 10 nm. Compared with the prior art, in this embodiment, since the portion of the isolation layer 120' is removed such that the height B is increased, the floating gate (the conductor layer 130) and the 11 200818407 2i 〇 84 twfd 〇 c / e are formed. The equivalent capacitance area between the control poles is also increased more than the gate _ combination rate; and the depressions at the top of the isolation structure 15G = 5 low height difference D, which can reduce the gap between adjacent floating gates Face & politician 'shrinks the domain cell's power to make the difference _ the reliability of the difference and the whole money. Moreover, due to the spacer material layer i35 used in the embodiment, the germanium isolation layer 120 has an excellent side selection ratio, so in the step of transferring the partial isolation layer 120 to form the isolation structure 150, it can effectively protect # The body layer 13 is such that the conductor layer 130 is not disturbed, and the height of the conductor 13 〇 (floating gate) is maintained. Fig. 2A to Fig. 2C are cross-sectional views showing the manufacturing process of the isolation structure according to another embodiment of the present invention. 2A to 2C are processes subsequent to the above FIG. Referring to FIG. 2A, after the conductor layer 130 is formed, a portion of the isolation layer 120 is removed. The removal method is, for example, an etch back method such as a dry etching method or a wet etching method. In the present embodiment, the thickness 导体 of the conductor layer 13 Α is, for example, 60 nm, and the difference between the top surface of the remaining isolation layer 120 ′ and the height of the conductor layer 13 amp & The thickness W of the layer 120, for example, 3 〇 nm ^ and the thickness at which the spacer layer 120 is removed can be controlled by wet etching. Thereafter, a conformal spacer material sound 135 is formed on the substrate 100. In the present embodiment, the spacer material layer 135 is made of, for example, tantalum oxide or the like, and has a etching selectivity ratio similar to or similar to that of the spacer layer 120'. In one embodiment, the spacer material layer 135 is formed by, for example, a chemical vapor deposition process using SiGemei 12 200818407 ) 21084 twf.doc/e oxalate (TEOS) as a gas source. The thickness of the spacer material layer is, for example, 20 nm. Then, referring to Fig. 2B, a portion of the spacer material layer 135' is removed to form a spacer 140' on the sidewall of the conductor layer 130. A method of removing a portion of the spacer material layer 135' is, for example, a dry etching method. In one embodiment, the height of the gap wall 140' is, for example, 30 nm, and the height difference D' of the spacer layer 120 from the top surface to the top surface of the substrate 100 is, for example, 30 nm. Thereafter, referring to Fig. 2C, the spacers 14 are removed by a refraction method, and a portion of the spacer layer 120' is formed to form the isolation structure 150. The method of removing the spacers 14A and the portion of the spacer layer 120' is, for example, a hydrogen etching method for wet etching. After the top of the spacer layer 120' is removed, the height difference D' between the top surface and the top surface of the substrate i is also reduced. As a result of the etch back, a recess 155 is formed on top of the isolation structure 150. The recess 155 may be arcuate, and the sidewall of the isolation structure 150 may cover the corner of the boundary between the conductor layer 130 and the dielectric layer 110. Thereby, the problem of leakage current of the conductor layer 130 (floating gate) can be reduced. In one embodiment, the height A of the conductor layer 130 is, for example, 60 nm, and the sidewall height B exposed by the conductor layer 130 is, for example, 40 nm, and the height difference D between the center of the top surface of the isolation structure and the top surface of the substrate 100 is i〇 Nm. In the present embodiment, the material of the spacer material layer 135' has approximately the same etching selectivity as the material of the spacer layer 120'. Therefore, in the step of forming the isolation structure 150, a portion of the isolation layer 12 can be simultaneously removed. And the spacer 140', and the step of separately removing the spacer 14〇 can be omitted. It should be noted that although the above embodiment is described by taking the non-volatile memory 13 200818407 2i 〇 84 twfd 〇 c / e white and the clothing process as an example, it is not intended to limit the present invention. And of course, (4) in other semiconductor processes, the manufacturing method of the isolation structure proposed by the present invention removes a part of the spacer _, and can increase the floating (four) pole and the subsequent shape: between the control gates. The equivalent capacitance area, which in turn increases the vocabulary ratio, and the operating voltage of the P-bull low body. In addition, due to the formation of the recess 155, the height of the isolation structure between the floating gate and the floating gate can be lowered, and the coupling effect between the floating gates can be reduced, and the voltage difference between the memory cells can be reduced. To further improve the reliability and overall performance of the memory. The present invention has been disclosed in the above embodiments, and it is not intended to limit the invention to those skilled in the art, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1D are cross-sectional views showing a manufacturing process of an isolation structure according to an embodiment of the present invention. 2A through 2C are cross-sectional views showing a manufacturing process of an isolation structure according to another embodiment of the present invention. [Description of main component symbols] 100 · Substrate no: Dielectric layer 115 · Ditch 120, 120': Isolation layer 200818407 21084twf.doc/e 130 : Conductor layer 135, 135': Gap material layer 140, 140': Clearance wall 150: isolation structure 155: recess A: conductor layer height B: sidewall height exposed by the conductor layer D, D': height difference between the center of the top surface of the isolation structure and the top surface of the substrate W, W': thickness of the isolation layer removed 15