0705007 26514twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電路板及其製造方法，且特別是 有關於一種埋入式電容元件電路板（circuit b〇ard with embedded capacitance component)以及其製造方法。 【先前技術】 在現今的電路板技術中’目前已發展出埋入式電容元 件電路板，而這種電路板本身已具有埋入式電容元件 (embedded capacitance component)，因此埋入式電容元 件電路板可以組裝較少數量的電容元件。 圖1是習知一種埋入式電容元件電路板在組裝晶片 (chip )之後的剖面示意圖。請參閱圖1，習知的埋入式電 容元件電路板100包括二銅線路層ll〇a、ll〇b、二介電層 120a、120b、二防焊層130a、130b、一導電通孔結構 (conductive through hole structure ) 140 以及一埋入式電容 元件150，而埋入式電容元件電路板1〇〇能透過多顆焊球 S1來連接一晶片1〇。 埋入式電容元件150配置於介電層丨2〇3、i2〇b之間， 且介電層120a、120b分別覆蓋埋入式電容元件15〇的相對 二表面。銅線路層11〇。11〇1)分別位於介電層12〇3、12〇1) 上，而導電通孔結構14〇連接於銅線路層n〇a與銅線路層 110b之間。 銅線路層110a包括多條走線（trace) U2a以及多個 0705007 265I4twf.doc/i 接墊（pad) 114a，而銅線路層110b包括多條走線（tmce) 112b。防焊層i3〇a覆蓋這些走線112a，並暴露出這些接 墊U4a，而防焊層130b則覆蓋這些走線n2b。這些焊球 S1連接於這些接墊U4a與晶片10之間，以至於晶片 月&電性連接埋入式電容元件電路板。 埋入式電容元件15〇包括一上電極152a、一下電極 152b以及一陶瓷介電層154,其中上電極152a並未接觸於 下電極152b ’而陶竞介電層154配置於上電極152a與下 電極152b之間。另外，埋入式電容元件電路板1〇〇更包括 一對導電盲孔結構160a、160b，其中導電盲孔結構i60a 連接於其中一個接墊114a與上電極152a之間，而導電盲 孔結構160b連接於另一個接塾U4a與下電極152b之間。 如此，晶片10能與埋入式電容元件15〇電性連接。 關於埋入式電容元件150,其形成方法通常採用以下 步驟。首先，在厚度約為35微米的銅箔上先後印刷一層陶 瓷介電材料以及一層銅膏。由於銅箔的厚度約為35微米， 因此銅箔的質地相當柔軟。接著，將陶瓷介電材料燒結。 如此，陶瓷介電材料得以形成陶瓷介電層154，而埋入式 電容元件150得以形成。 由於銅箔的質地相當柔軟，因此，整體而言，埋入式 電容元件150的質地也是相當柔軟。倘若將埋入式電容元 件150壓合在線路板的外線路層中時，會因為埋入式電容 70件150的質地太過柔軟，以至於陶瓷介電層154難以座 落在正確的位置上，進而產生對準度太低的問題。 0705007 26514twf.doc/a 為了避免產生埋入式電容元件15〇的對準度太低之問 題，目前埋入式電容元件150都是形成在埋入式電容元; 電路板100的内線路層中（如圖！所示），而不會形成在 埋入式電容元件電路板100的外線路層（例如銅線路層 ll〇a、110b)中，因此埋入式電容元件15〇必須透過這^ 導電盲孔結構160a、160b以及這些焊球S1才能連接晶片 10。 曰曰 目前已發現晶片10與埋入式電容元件15〇之間的距 離D1越短，將有助於大幅降低雜訊的干擾，而這種情形 在尚頻汛號傳輸的技術領域中特別明顯。不過，受限於上 述埋入式電容元件150的對準度太低的問題，埋入式電容 =件150必須透過這些導電盲孔結構16〇a、16〇b以及這些 焊球S1才能連接晶片10。如何進一步地縮短晶片1〇與埋 入式電容元件150之間的距離D1，以提高埋入式電容元件 電路板100的訊號傳輸品質，是目前值得探討的議題。 【發明内容】 本發明提供一種埋入式電容元件電路板的製造方 法’其所製造出來的埋入式電容元件電路板能用來電性連 接晶片。 本發明另提供一種埋入式電容元件電路板的製造方 法’以縮短埋入式電容元件電路板與晶片之間的距離。 本發明提供一種埋入式電容元件電路板，其能用來電 性連接晶片。 0705007 26514twf.doc/n 本發明提供一種埋入式電容元件電路板的製1 法，其包括以下步驟。首先，形成一絕緣層於—内層= 基板上，其中内層線路基板具有一表面，並包括一^於 面之内線路層，而絕緣層覆蓋内線路層。接著，形二表 線路層於絕緣層上，其中外線路層包括一第一電極、—外 -電極、至少-連接第-電極之第—接塾以及至少 = 第二電極之第二接墊，而第—電極未接觸第二電極 -電極與第二電極之間存有多條溝渠。接著，形成 於外線路層與喊路層之_導電H纟靖 一介電材料於這些溝渠中。 、 在本發明之-實施例中，上述埋入 的製造方法更包括形成-防焊層，其中防焊層覆= 介電材料，且防焊層暴露第1墊與第二祕广、接觸 法L括制緣層進仃一鑽孔製程 線路層之盲孔。接著，對盲孔H域局。p暴路内 plating)。 孔進仃填孔電鑛製程（via filling 孔。在本發明之—實施例中，上述鑽孔製程包括雷射鑽 在本發明之一實施例中， 構同時形成。 外線路層與導電盲孔結 在本發明之一實施例中， 括印刷-有機介電材料於這些介電材料的方法包 " 例中’上述第—雜與第二電極皆 0705007 26514twf. doc/n 為一梳狀電極。 冰，另提供—種以式電容元件電路板的製造方 立中：：二：步驟。首先’在—基板上形成-線路層’ 二曾：巧板與—配置於承載板上之阻障層’而 ，光叫層的材質不同。線路層形成於阻障層 二雷極極與—第二電極’第—電極未接觸第 二入一人㈣祖，第二電極之間存有多條溝渠。接著， 由一锅二二：足些溝渠中。在填入介電材料之後，藉 線路A板^有^基板於—内層線路基板上方，其中内層 深路基扳具有一表面，並句扭仏士人士 線路層相餘⑽⑽⑽路層，而 ίΓ H 線路層與該内線路層之間的導電盲孔 二t接者’形成至少-連接第—電極之第—接塾盘至少 連接第-雜n墊，其中 及線路剌在輯層的—側。 ㈣接塾以 在本發明之-實施例中，上述填入介電材料的 =電=:陶究介電材料於這些溝渠内。接著，燒結4 膠 片或一樹脂層 在本發明之—實施射，上述絕緣層包括0705007 26514twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board and a method of fabricating the same, and in particular to a circuit board for a capacitive capacitor (circuit b〇ard with Embedded capacitance component) and its manufacturing method. [Prior Art] In today's circuit board technology, a buried capacitive element circuit board has been developed, and such a circuit board itself has an embedded capacitance component, so a buried capacitive element circuit The board can assemble a smaller number of capacitive components. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional embedded capacitor circuit board after assembling a chip. Referring to FIG. 1 , a conventional buried capacitor device circuit board 100 includes a copper circuit layer 11a, 11b, two dielectric layers 120a and 120b, two solder mask layers 130a and 130b, and a conductive via structure. A conductive via hole structure 140 and a buried capacitor element 150, and the buried capacitor device board 1 can connect a wafer 1 through a plurality of solder balls S1. The buried capacitive element 150 is disposed between the dielectric layers 丨2〇3, i2〇b, and the dielectric layers 120a, 120b cover the opposite surfaces of the buried capacitive element 15A, respectively. The copper circuit layer is 11 〇. 11〇1) are respectively located on the dielectric layers 12〇3, 12〇1), and the conductive via structure 14 is connected between the copper wiring layer n〇a and the copper wiring layer 110b. The copper wiring layer 110a includes a plurality of traces U2a and a plurality of 0705007 265I4twf.doc/i pads 114a, and the copper wiring layer 110b includes a plurality of traces (tmce) 112b. The solder resist layer i3〇a covers the traces 112a and exposes the pads U4a, and the solder resist layer 130b covers the traces n2b. The solder balls S1 are connected between the pads U4a and the wafer 10 such that the wafers are electrically connected to the buried capacitor element circuit board. The buried capacitive element 15A includes an upper electrode 152a, a lower electrode 152b, and a ceramic dielectric layer 154. The upper electrode 152a is not in contact with the lower electrode 152b' and the Taoying dielectric layer 154 is disposed on the upper electrode 152a and the lower surface. Between the electrodes 152b. In addition, the buried capacitive component circuit board 1 further includes a pair of conductive blind via structures 160a, 160b, wherein the conductive blind via structure i60a is connected between one of the pads 114a and the upper electrode 152a, and the conductive blind via structure 160b Connected between another interface U4a and the lower electrode 152b. In this way, the wafer 10 can be electrically connected to the buried capacitor element 15 . Regarding the method of forming the buried capacitor element 150, the following steps are generally employed. First, a layer of ceramic dielectric material and a layer of copper paste are printed successively on a copper foil having a thickness of about 35 microns. Since the thickness of the copper foil is about 35 microns, the texture of the copper foil is quite soft. Next, the ceramic dielectric material is sintered. Thus, the ceramic dielectric material is capable of forming the ceramic dielectric layer 154, and the buried capacitive element 150 is formed. Since the texture of the copper foil is relatively soft, the texture of the buried capacitor element 150 is also quite soft as a whole. If the buried capacitor element 150 is pressed into the outer wiring layer of the circuit board, the texture of the buried capacitor 70 is too soft, so that the ceramic dielectric layer 154 is difficult to be seated in the correct position. , which in turn causes a problem that the alignment is too low. 0705007 26514twf.doc/a In order to avoid the problem that the alignment degree of the buried capacitive element 15 is too low, the buried capacitive element 150 is currently formed in the buried capacitor; in the inner circuit layer of the circuit board 100 (shown in Fig.!), and not formed in the outer wiring layer (e.g., copper wiring layers 11a, 110b) of the buried capacitive element circuit board 100, so the buried capacitive element 15 must pass through this ^ The conductive blind via structures 160a, 160b and the solder balls S1 can be connected to the wafer 10.曰曰 It has been found that the shorter the distance D1 between the wafer 10 and the buried capacitive element 15〇, the smaller the interference D1 will be, which will help to greatly reduce the interference of noise, which is particularly obvious in the technical field of frequency transmission. . However, limited by the problem that the alignment degree of the buried capacitive element 150 is too low, the buried capacitor=member 150 must pass through the conductive blind via structures 16〇a, 16〇b and the solder balls S1 to connect the wafer. 10. How to further shorten the distance D1 between the wafer 1 and the buried capacitive element 150 to improve the signal transmission quality of the embedded capacitive element circuit board 100 is currently worthy of discussion. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a buried capacitive element circuit board. The buried capacitive element circuit board manufactured by the present invention can be used to electrically connect a wafer. The present invention further provides a method of fabricating a buried capacitive element circuit board to shorten the distance between the buried capacitive element circuit board and the wafer. The present invention provides a buried capacitive element circuit board that can be used to electrically connect a wafer. 0705007 26514twf.doc/n The present invention provides a method of manufacturing a buried capacitive element circuit board, which comprises the following steps. First, an insulating layer is formed on the inner layer = substrate, wherein the inner layer circuit substrate has a surface and includes a wiring layer within the surface, and the insulating layer covers the inner wiring layer. Next, the circuit board layer is formed on the insulating layer, wherein the outer circuit layer comprises a first electrode, an outer electrode, at least a first interface connecting the first electrode, and a second pad at least = the second electrode. The first electrode is not in contact with the second electrode - there are a plurality of trenches between the electrode and the second electrode. Then, a conductive material is formed in the outer circuit layer and the shouting layer. In the embodiment of the present invention, the embedded manufacturing method further includes forming a solder mask, wherein the solder resist layer is a dielectric material, and the solder resist layer exposes the first pad and the second secret, and the contact method The L edge layer is formed into a blind hole of the drilling process circuit layer. Next, the blind hole H domain bureau. p violent road plating). In the embodiment of the present invention, the above drilling process includes a laser drill in an embodiment of the present invention, and the structure is simultaneously formed. The outer circuit layer and the conductive blind hole In one embodiment of the present invention, a method for printing a dielectric-organic dielectric material in the dielectric material is as follows: 'The above-mentioned first and second electrodes are 0705007 26514 twf. doc/n is a comb electrode Ice, another offer - the manufacture of a type of capacitive component circuit board: 2: Step. First, 'form on the substrate - the circuit layer' Second: the board and the barrier layer on the carrier board' However, the material of the light layer is different. The circuit layer is formed on the barrier layer and the second electrode 'the first electrode is not in contact with the second one (four) ancestors, and there are a plurality of trenches between the second electrodes. Then, From a pot of two or two: in some ditch. After filling the dielectric material, the line A board has a substrate on the inner circuit board, wherein the inner layer of the deep road base has a surface, and the twisted gentleman line Layers are separated by (10) (10) (10) road layers, while Γ The conductive blind hole between the H circuit layer and the inner circuit layer is formed by at least connecting the first electrode of the first electrode to at least the first-heap n-pad, wherein the circuit is at the side of the layer (4) In the embodiment of the present invention, the dielectric material filled in the dielectric material is: the ceramic dielectric material is in the trenches. Then, the sintered 4 film or a resin layer is implemented in the present invention. Shot, the above insulation layer includes
一也Η匕玨▲ ϊ Μ Ί G 本發日狀提供—雜人容元件電触，其一 内層線路基板、-絕緣層、—外線路層、—介 —導電盲孔結構。内層線路基板具有—表面，並包括= 於表面之内線_。絕緣層配置於内線路層上。外線路^ 0705007 26514twf.d〇c/n 並包括-第-電極、-第二電極、至少 二接塾，接墊以及至少—連接第二電極之第 二電極之電極未接觸第二電極，且第—電極與第 3存有多條溝渠。介電材料配置於這些溝渠内 導電盲孔結構連接於外線路層與内祕狀間。/、° git發明之—實施例中，上述第一電極與第二電極皆 位於絕緣層與介電材料之間。 枝白 f本發明之-實施财，上述就式電容元件電路 ===防晴蓋蝴靖料，並暴露 位於防谭層與介電上衫—電極與第二電極皆 基於上述，本發明的埋入式電容元件電路板， 2與晶片之間具有較短的距離。相較於習知技術而言， ^明的埋人式電容元件電路板具有良好的訊號傳輸品 貝0 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實施例’並配合所附圖式，作詳細說明如下。 【實施方式】 【第一實施例】Η匕玨 ϊ ϊ ϊ Μ Ί G This is a daily supply—the inner circuit board, the insulation layer, the outer circuit layer, and the conductive blind hole structure. The inner layer circuit substrate has a surface and includes an inner line _. The insulating layer is disposed on the inner circuit layer. An external line ^ 0705007 26514twf.d〇c/n and comprising - a first electrode, a second electrode, at least two contacts, a pad, and at least - an electrode connecting the second electrode of the second electrode is not in contact with the second electrode, and The first electrode and the third electrode have a plurality of trenches. The dielectric material is disposed in the trenches. The conductive blind via structure is connected between the outer circuit layer and the inner secret layer. In the embodiment, the first electrode and the second electrode are both located between the insulating layer and the dielectric material.枝白f The present invention-implementation, the above-mentioned capacitive element circuit === anti-clear cover, and exposed to the anti-tan layer and the dielectric top-electrode and the second electrode are based on the above, the present invention The buried capacitive component board, 2 has a short distance from the wafer. Compared with the prior art, the buried capacitive element circuit board has a good signal transmission. In order to make the above features and advantages of the present invention more obvious, the preferred embodiment is described below. In conjunction with the drawings, a detailed description will be given below. [Embodiment] [First Embodiment]
圖2A疋本發明第_實施例之一種埋入式電容元件電 路板的俯視示意圖，而圖2B是圖2A中的埋人式電容元件 電路板在組裝晶片後的剖面示意圖，其中圖ZB是從圖2A 0705007 26514twf.doc/n 中的線I-I剖面而得。請參閱圖2A與圖2B，埋入式電容 元件電路板200包括一内層線路基板21〇、一絕緣層22〇、 一外線路層230、一介電材料240以及一導電盲孔結構25〇。 内層線路基板210具有一表面210a，並包括一位於表 面210a之内線路層212。在其他未繪示的實施例中，内層 線路基板210更可以包括内線路層212以外的線路層。或 者，内層線路基板210亦可以僅包括内線路層212，即内 層線路基板210可以是一層線路層。絕緣層220配置於内 線路層212上，而外線路層230配置於絕緣層220上，其 中導電盲孔結構250連接於外線路層230與内線路層212 之間。 外線路層230配置於絕緣層220上’並包括一第一電 極232a、一第二電極232b、一第一接墊234a以及一第二 接墊234b，其中第一接墊234a連接第一電極232a，而第 二接墊234b連接第二電極232b，其中第一電極232a未接 觸第二電極232b。 第一電極232a與第二電極232b可以皆為梳狀電極， 而第一電極232a與第二電極232b之間存有多條溝渠T1， 其中介電材料240配置於這些溝渠τι内。介電材料24〇、 第一電極232a與第二電極232b能構成一電容元件c 1，而 第一電極232a與第二電極232b可以皆位在絕緣層220與 介電材料240之間。 第一接墊234a與第二接墊234b能藉由多個焊料塊S2 (圖2B僅繪示一個）連接一晶片2〇或是其他電子元件（例 1342171 0705007 26514twf.doc/n 如被動元件），其中焊料塊S2例如是焊球。由於第一接 墊234a與第二接墊234b分別連接第—電極23%與第二電 極232b，因此晶片20可以僅透過第—接墊23牝、第二接 墊234b以及這些焊料塊S2來連接電容元件。相較於習 知技術而言（可參閱圖丨），晶片2〇與電容元件C1之間 存有較短的距離D2。因此，埋入式電容元件電路板2〇〇 具有良好的訊號傳輸品質’且適合制在高頻訊號傳輸的 技術領域中。 在本實施例中，埋入式電容元件電路板2⑻更包括一 防焊層260。防焊層260覆蓋並接觸介電材料24〇，以保護 電容元件c卜此外，防烊層260暴露第—接墊234a與第 一接墊234b，以使第一接塾234a以及第二接整234b能夠 連接晶片20。 圖2C是本發明第一實施例之另—種埋入式電容元件 電路板的俯視示意圖。請參閱圖2C，埋入式電容元件電路 板200’與埋入式電容元件電路板200二者剖面結構大體相 同，而埋入式電容元件電路板200’包括一外線路層23〇,。 外線路層230’包括一第一電極232a’、一第二電極 232b’、多個第一接墊234a以及多個第二接墊234b。針對 不同的電路設計與產品需求，第一電極232a，可以連接這 些第接塾234a，而第二電極232b’可以連接這班ί第二接 墊234b。因此，在本發明中，埋入式電容元件電路板可以 包括一個或多個連接第一電極的第一接墊，以及一個或多 個連接第二電極的第二接墊。 12 1342171 0705007 26514twf.doc/n 以上僅介紹本實施例之埋入式電容元件電路板2 〇 〇與 200,的結構，接下來將以圖2B所示的埋入式電容元件電^ 板200為例，並配合圖3A至圖3G，以詳細介紹本實施例 之埋入式電容元件電路板200的製造方法。 、 圖3A至圖3G疋圖2B中埋入式電容元件電路板的製 造方法之流程示意圖。請參閱圖3A，有關埋入式電容元件 電路板200的製造方法’首先，形成絕緣層22〇於内層線 路基板210上’其中絕緣層220覆蓋内層線路基板21〇的 内線路層212,而絕緣層220可以是樹脂層或半固化膠片。 請參閱圖3B ’接著’對絕緣層220進行一鑽孔製程， 以形成一局部暴露内線路層212之盲孔B1，其中鑽孔製程 可以是雷射鑽孔或其他適當的鑽孔製程。在形成盲孔B1 之後，可以將絕緣層220的表面220a粗糙化，並且進行去 膠渣製程，以清潔盲孔B1所暴露的部分内線路層212。 清參閱圖3C，接者，可以形成一遮罩層270於絕緣 層220上，其中遮罩層270局部覆蓋表面22〇a。在形成遮 罩層270之前’可以用無電電鑛法來形成一厚度很薄的電 鑛種子層（未繪示）於絕緣層220的表面220a上以及盲孔 B1中。此外，遮罩層270可以是溼式光阻或是乾膜（dry film)。 請參閱圖3D，接著，形成外線路層23〇於絕緣層22〇 上，其中外線路層230包括第一電極232a、第二電極232b、 第一接塾234a以及第一接塾234b (請參考圖2A )。 由於在形成遮罩層270之前，可以用無電電鍍法來形 13 0705007 26514twf.d〇c/i 成電鍰種子層’因此’藉由該電鍵種子層，外線路層23〇 可以利用電鍍法來形成。此外，透過遮罩層27〇，外線路 層230所包括的第一電極232a與第二電極232b皆可為梳 狀電極（請參考圖2A)。 除了形成外祕層230之外，亦形錢接於外線路屬 23〇與内線路層212之間的導電盲孔結構25〇。在本實施例 中’形成導電盲孔結構，的方法可以是對盲孔m進行 填孔電鑛製程，而藉由前述的電鑛種子層，導電盲孔結構 250可以與外線路層230同時形成。 請參閱圖犯與圖3E，接著，全面性地移除遮罩層 270’以使第-電極232a與第二電極挪之間形成這些溝 渠T1。在全面性地移除遮罩層270之後，可以對外線路層 230進行微蝕刻（micro-etching)，以使第—電極232^ 會與第二電極232b直接電性接觸而造成短路。 請參閱圖3F，接著，填入介電材料24〇於這些溝渠 T1中’其中填入介電材料240的方法可以是印刷一有機^ 電材料於這些溝渠T1心此外’印刷該有機介電材料的 方式可以是鋼板印刷、絲板印刷或其他網印的方式。在填 入介電材料24G之後，基本上-種埋人式電容元件電路板 2〇〇以製造完成。 請參閱圖3G，接著，形成覆蓋介電材料24〇的防焊 層260，其中防焊層260更與介電材料24〇接觸，並暴露 第一接墊234a與第二接墊234b (請參考圖2A)。此外， 圖3G所示的防焊層260之類型為防焊層定義（s〇lder Mask 1342171 0705007 26514twf.doc/n2A is a top plan view of a buried capacitive element circuit board according to a first embodiment of the present invention, and FIG. 2B is a cross-sectional view of the buried capacitive element circuit board of FIG. 2A after assembling a wafer, wherein FIG. Figure 2A shows the line II profile in 0705007 26514twf.doc/n. Referring to FIG. 2A and FIG. 2B, the buried capacitor device circuit board 200 includes an inner circuit substrate 21, an insulating layer 22, an outer circuit layer 230, a dielectric material 240, and a conductive blind via structure 25A. The inner wiring substrate 210 has a surface 210a and includes a wiring layer 212 located inside the surface 210a. In other embodiments not shown, the inner wiring substrate 210 may further include a wiring layer other than the inner wiring layer 212. Alternatively, the inner wiring substrate 210 may include only the inner wiring layer 212, that is, the inner wiring substrate 210 may be a wiring layer. The insulating layer 220 is disposed on the inner wiring layer 212, and the outer wiring layer 230 is disposed on the insulating layer 220, wherein the conductive blind via structure 250 is connected between the outer wiring layer 230 and the inner wiring layer 212. The outer circuit layer 230 is disposed on the insulating layer 220 and includes a first electrode 232a, a second electrode 232b, a first pad 234a and a second pad 234b. The first pad 234a is connected to the first electrode 232a. The second pad 234b is connected to the second electrode 232b, wherein the first electrode 232a does not contact the second electrode 232b. The first electrode 232a and the second electrode 232b may each be a comb electrode, and a plurality of trenches T1 are disposed between the first electrode 232a and the second electrode 232b, wherein the dielectric material 240 is disposed in the trenches τι. The dielectric material 24A, the first electrode 232a and the second electrode 232b can form a capacitive element c1, and the first electrode 232a and the second electrode 232b can be located between the insulating layer 220 and the dielectric material 240. The first pad 234a and the second pad 234b can be connected to a wafer 2 or other electronic components by a plurality of solder bumps S2 (only one is shown in FIG. 2B) (eg, 1342171 0705007 26514twf.doc/n such as passive components) Wherein the solder bump S2 is, for example, a solder ball. Since the first pad 234a and the second pad 234b are respectively connected to the first electrode 23% and the second electrode 232b, the wafer 20 can be connected only through the first pad 23牝, the second pad 234b, and the solder pads S2. Capacitive component. Compared to the prior art (see Fig. 丨), there is a short distance D2 between the wafer 2 and the capacitive element C1. Therefore, the buried capacitive element circuit board 2 has good signal transmission quality and is suitable for the technical field of high frequency signal transmission. In the present embodiment, the buried capacitive element circuit board 2 (8) further includes a solder resist layer 260. The solder resist layer 260 covers and contacts the dielectric material 24A to protect the capacitor element c. In addition, the anti-mite layer 260 exposes the first pad 234a and the first pad 234b to make the first interface 234a and the second connection 234b is capable of connecting the wafer 20. Fig. 2C is a top plan view showing another buried capacitor element circuit board according to the first embodiment of the present invention. Referring to Fig. 2C, the buried capacitive element circuit board 200' and the buried capacitive element circuit board 200 have substantially the same cross-sectional structure, and the buried capacitive element circuit board 200' includes an outer wiring layer 23'. The outer wiring layer 230' includes a first electrode 232a', a second electrode 232b', a plurality of first pads 234a, and a plurality of second pads 234b. For different circuit designs and product requirements, the first electrode 232a can be connected to the first pads 234a, and the second electrode 232b' can be connected to the second pads 234b. Therefore, in the present invention, the buried capacitive element circuit board may include one or more first pads connected to the first electrodes, and one or more second pads connected to the second electrodes. 12 1342171 0705007 26514twf.doc/n The above description only shows the structure of the buried capacitive element circuit board 2 〇〇 and 200 of the present embodiment, and nextly, the buried capacitive element electrical panel 200 shown in FIG. 2B is used. For example, in conjunction with FIGS. 3A to 3G, a method of manufacturing the buried capacitive element circuit board 200 of the present embodiment will be described in detail. 3A to 3G and FIG. 2B is a flow chart showing a method of manufacturing a buried capacitor element circuit board. Referring to FIG. 3A, a method of manufacturing the buried capacitive element circuit board 200 is first formed by forming an insulating layer 22 on the inner layer circuit substrate 210, wherein the insulating layer 220 covers the inner circuit layer 212 of the inner layer circuit substrate 21, and is insulated. Layer 220 can be a resin layer or a semi-cured film. Referring to Figure 3B, the insulating layer 220 is subsequently subjected to a drilling process to form a blind via B1 that partially exposes the inner wiring layer 212, wherein the drilling process can be a laser drilling or other suitable drilling process. After the blind via B1 is formed, the surface 220a of the insulating layer 220 may be roughened, and a desmear process is performed to clean a portion of the inner wiring layer 212 exposed by the blind via B1. Referring to Figure 3C, a mask layer 270 can be formed over the insulating layer 220, wherein the mask layer 270 partially covers the surface 22A. Before the formation of the mask layer 270, a thin layer of an electric ore seed layer (not shown) may be formed on the surface 220a of the insulating layer 220 and in the blind via B1. Further, the mask layer 270 may be a wet photoresist or a dry film. Referring to FIG. 3D, an external circuit layer 23 is formed on the insulating layer 22, wherein the outer circuit layer 230 includes a first electrode 232a, a second electrode 232b, a first interface 234a, and a first interface 234b (please refer to Figure 2A). Since the electroless plating method can be used to form 13 0705007 26514 twf.d〇c/i into an electric seed layer before the formation of the mask layer 270, the outer circuit layer 23 can be electroplated by the electroless seed layer. form. In addition, through the mask layer 27, the first electrode 232a and the second electrode 232b included in the outer circuit layer 230 may be comb electrodes (please refer to FIG. 2A). In addition to forming the outer layer 230, the conductive blind hole structure 25 is also connected between the outer line 23 and the inner circuit layer 212. In the present embodiment, the method of forming the conductive blind via structure may be a hole filling electric ore process for the blind via m, and the conductive blind via structure 250 may be formed simultaneously with the outer wiring layer 230 by the foregoing electric ore seed layer. . Referring to Figure 3E, the mask layer 270' is then removed comprehensively to form the trenches T1 between the first electrode 232a and the second electrode. After the mask layer 270 is completely removed, the outer wiring layer 230 may be micro-etched such that the first electrode 232 is directly in electrical contact with the second electrode 232b to cause a short circuit. Referring to FIG. 3F, a dielectric material 24 is then filled in the trenches T1. The method of filling the dielectric material 240 may be to print an organic material to the trenches T1 and to print the organic dielectric material. The way can be steel plate printing, silk screen printing or other screen printing. After the dielectric material 24G is filled, the substantially buried capacitive element circuit board 2 is manufactured to be completed. Referring to FIG. 3G, a solder resist layer 260 covering the dielectric material 24A is formed, wherein the solder resist layer 260 is further in contact with the dielectric material 24, and exposes the first pad 234a and the second pad 234b (please refer to Figure 2A). In addition, the type of solder resist layer 260 shown in FIG. 3G is a solder mask definition (s〇lder Mask 1342171 0705007 26514twf.doc/n
Define，SMD)，但是在其他未繪示的實施例中，防焊層 260之類型亦可以為非防焊層定義（N〇n_s〇ider Mask Define, NSMD )。 【第二實施例】 圖4是本發明第二實施例之一種埋入式電容元件電路 板的的剖面示意圖。請參閱圖4，本實施例的埋入式電容 元件電路板300亦包括一内層線路基板310、一絕緣層 320、一外線路層330、一介電材料340、一導電盲孔結構 350以及一防焊層360，而外線路層330包括第一電極 332a、第二電極332b、第一接墊334a以及第二接墊（未 繪示）’其中介電材料340、第一電極332a與第二電極332b 能構成一電容元件C2。 埋入式電容元件電路板3〇〇的結構、功效與功能皆與 前述實施項相似，而且以方向V觀看埋入式電容元件電路 板300所得到的俯視示意圖與圖2A、2C大體相同。也就 是說’在本實施例中，當從方向V觀看埋入式電容元件電 路板300時，可以發現第一電極332a與第二電極33沘皆 為梳狀電極。 有關本實施例與第一實施例相同及相似的特徵，以下 不再贅述，而二者差異之處在於：第一電極332a與第二電 極332b皆位於防焊層360與介電材料34〇之間，且第一電 極332a與第二電極332b可以被防焊層360以及介電材料 340所包覆。 圖5A至圖5M是圖4中埋入式電容元件電路板的製 15 0705007 26514twf.doc/n 造方法之流程示意圖。請參閱圖5A，有關埋入式電容元件 電路板300的製造方法’首先，提供一基板4〇〇，其包括 一承載板410與一阻障層420，而阻障層42〇配置於承載 板410上。承載板410的材質與阻障層42〇的材質不同， 其中阻障層420的材質可以是鎳、錫或是其他非銅的金 屬，而承載板410的材質可以是鋼或|呂。 請參閱圖5B，接著，可以形成一遮罩層37〇於阻障 層420上，其中遮罩層370局部覆蓋阻障層42〇的表面 420a。在形成遮罩層370之前’可以先對表面42〇a粗糙化， 接著用無電電鍍法來形成一厚度很薄的電鍍種子層（未繪 示）於表面420a上。此外，遮罩層37〇可以是溼式光阻^ 是乾膜。 請參閱圖5C，接著，在一基板4〇〇上形成—線路層 330|，其中線路層330,是形成於阻障層42〇上，而線路^ 330’包括一第一電極332a與—第二電極33汾。此外，線 路層330’可以利用電鍍法來形成。 °月參閱圖5C與圖5D，接著，全面性地移除遮罩層 3J0 ’以使第一電極332a與第二電極332b之間形成多條^ 渠T2。 請參閱圖5E，接著，填入介電材料34〇於這些溝渠 T2中，其中填入介電材料34〇的方法可以包括以下步驟。 首先，印刷一陶瓷介電材料於這些溝渠T2内。接著，燒 結該陶究介電㈣，⑽齡電材料。由此可知，^ 電材料340可以是由陶究介電材料所形成。此外，印刷該 1342171 0705007 26514twf.doc/n 陶究介電材料的方式可以是鋼板印刷、絲板印刷或其他網 印的方式。 請參閱圖5F ’在形成介電材料34〇之後，藉由絕緣層 320’壓合基板400於内層線路基板31〇上方，其中絕緣層 320可以是半固化膠片或樹脂層。内層線路基板31〇具有 一表面310a，並包括一位於表面31〇a之内線路層312，且 線路層330’相對於内線路層312。 請參閱圖5F與圖5G，接著，移除承載板410，其中 移除承載板410的方法可以採用蝕刻製程，例如是溼式蝕 刻製程。由於承載板410的材質與阻障層420的材質不同， 因此當移除承載板410的方法是採用溼式蝕刻製程時，可 以，用能蝕刻承載板41〇，但卻難以蝕刻阻障層42〇的蝕 刻藥液。如此，阻障層42〇可以保護線路層33〇，以避免被 蝕刻藥液所損傷。此外，由於阻障層420的材質可以是鎳、 錫或是其他非銅的金屬，而承載板41〇的材質可以是銅或 鋁，因此上述蝕刻藥液可以選用鹼性蝕刻液。 s月參閱圖5G與圖5H，接著，移除阻障層420，其中 2阻障層420的方法可以採祕刻製程，例如是渔式餘 刻製程。在全面性地移除阻障層420之後，可以對線路層 =〇進行微蝕刻’以使第一電極332a不會與第二電極332b 直接電性接觸而造成短路。 、，請參閱圖51，接著，對絕緣層32〇進行一鑽孔製程， 以形成—局部暴露内線路層312之盲孔B2,其中該鑽孔製 程可以為雷射鑽孔。 八 17 1342171 0705007 26514twf.doc/n 請參閱圖5J，之後，對盲孔B2進行填孔電鎮製程， 以形成一連接於線路層330,與内線路層312之間的^亡 孔結構350，其中該填孔電鍍製程包括無電電鍵法以及^ 鑛法。 請參閱圖5K，之後，可形成材質與遮罩層37〇 的遮罩層獅’其中遮罩層覆蓋絕緣層挪與 料34〇，並且暴露出導電盲孔結構35〇。 請參閱圖5L’之後，形成至少—連接第—電極迪 之第一接墊334a以及至少一連接第二電極332b之第二接 整（未繪示），其中第一接塾334a、第二接塾以及線:層 330’同在絕緣層320的一側。 請參閱圖5L與圖5M，接著，全面性地移除遮罩層 =〇。如此，基本上一種埋入式電容元件電路板3〇〇已製造 几成。此外，在本實施例中，更可以形成防焊層36〇，其 中防焊層360覆蓋並接觸介電材料34〇，且防焊層36〇暴 路第一接墊334a與第二接墊’以使埋入式電容元件電路板 3〇〇能連接電子元件，其例如是被動元件或晶片。 綜上所述，本發明能使晶片僅透過多個接墊（例如第 ―、一接墊）以及焊料塊來連接埋入式電容元件電路板的 電谷元件。相較於習知技術而言，本發明能大幅縮短晶片 與電容元件之間的距離。因此，本發明的埋入式電容元件 電路板具有良好的訊號傳輸品f，並適合朗在高頻訊號 傳輸的技術領域中。 雖然本發明已以較佳實施例揭露如上，然其並非用以 0705007 26514twf.doc/n 限定本發明，任何所屬技術領域中具有通常知識者，在不 脫離本發明之精神和範圍内，當可作些許之更動與潤飾， 因此本發明之保護範圍當視後附之申請專利範圍所界定者 為準。 【圖式簡單說明】 圖1是習知一種埋入式電容元件電路板在組裝晶片之 後的剖面示意圖。 圖2A是本發明第一實施例之一種埋入式電容元件電 路板的俯視示意圖。 圖2B是圖2A中的埋入式電容元件電路板在組裝晶片 後的剖面示意圖。 圖2C疋本發明第一實施例之另一種埋入式電容元件 電路板的俯視示意圖。 圖3A至圖3G是圖2B中埋入式電容元件電路板的製 造方法之流程示意圖。 圖4是本發明第二實施例之一種埋入式電容元件電路 板的的剖面示意圖。 圖5A至圖5M是圖4中埋入式電容元件電路板的製 造方法之流程示意圖。 【主要元件符號說明】 10、20 :晶片 100、200、200’、300 :埋入式電容元件電路板 1342171 0705007 26514twf.doc/n 110a、110b :銅線路層 114a :接墊 130a、130b、260、360 : 140 :導電通孔結構 152a :上電極 154 :陶瓷介電層 112a、112b :走線 120a、120b :介電層 防焊層 150 :埋入式電容元件 152b :下電極Define, SMD), but in other embodiments not shown, the type of solder resist layer 260 may also be a non-solder mask definition (NSMD). [Second Embodiment] Fig. 4 is a cross-sectional view showing a circuit board of a buried capacitor element according to a second embodiment of the present invention. Referring to FIG. 4 , the buried capacitor device circuit board 300 of the present embodiment further includes an inner layer circuit substrate 310 , an insulating layer 320 , an outer circuit layer 330 , a dielectric material 340 , a conductive blind via structure 350 , and a The solder resist layer 360, and the outer circuit layer 330 includes a first electrode 332a, a second electrode 332b, a first pad 334a, and a second pad (not shown), wherein the dielectric material 340, the first electrode 332a and the second The electrode 332b can constitute a capacitive element C2. The structure, function, and function of the embedded capacitive element circuit board 3 are similar to those of the foregoing embodiment, and the top view of the buried capacitive element circuit board 300 viewed in the direction V is substantially the same as that of Figs. 2A and 2C. That is to say, in the present embodiment, when the buried capacitive element circuit board 300 is viewed from the direction V, it can be found that the first electrode 332a and the second electrode 33 are both comb electrodes. The same and similar features of the present embodiment and the first embodiment are not described below, and the difference between the two is that the first electrode 332a and the second electrode 332b are located between the solder resist layer 360 and the dielectric material 34. Meanwhile, the first electrode 332a and the second electrode 332b may be covered by the solder resist layer 360 and the dielectric material 340. 5A to FIG. 5M are schematic diagrams showing the flow of the method of manufacturing the buried capacitor element circuit board of FIG. Referring to FIG. 5A, a method for manufacturing a buried capacitor device circuit board 300 is first provided with a substrate 4 including a carrier 410 and a barrier layer 420, and the barrier layer 42 is disposed on the carrier. On 410. The material of the carrier plate 410 is different from the material of the barrier layer 42. The material of the barrier layer 420 may be nickel, tin or other non-copper metal, and the material of the carrier plate 410 may be steel or steel. Referring to FIG. 5B, a mask layer 37 may be formed on the barrier layer 420, wherein the mask layer 370 partially covers the surface 420a of the barrier layer 42A. The surface 42A may be roughened prior to the formation of the mask layer 370, and then a very thin plating seed layer (not shown) is formed on the surface 420a by electroless plating. Further, the mask layer 37 may be a wet photoresist or a dry film. Referring to FIG. 5C, a circuit layer 330 is formed on a substrate 4, wherein the circuit layer 330 is formed on the barrier layer 42, and the line 330' includes a first electrode 332a and a The two electrodes are 33 turns. Further, the wiring layer 330' can be formed by electroplating. Referring to Fig. 5C and Fig. 5D, then, the mask layer 3J0' is comprehensively removed to form a plurality of channels T2 between the first electrode 332a and the second electrode 332b. Referring to FIG. 5E, a dielectric material 34 is then filled in the trenches T2, and the method of filling the dielectric material 34A may include the following steps. First, a ceramic dielectric material is printed in these trenches T2. Next, the ceramic dielectric (4), (10) age electrical material is sintered. It can be seen that the electroconductive material 340 can be formed of a ceramic dielectric material. In addition, the method of printing the 1342171 0705007 26514 twf.doc/n ceramic dielectric material may be by means of steel plate printing, silk screen printing or other screen printing. Referring to FIG. 5F', after the dielectric material 34 is formed, the substrate 400 is pressed over the inner wiring substrate 31 by an insulating layer 320', wherein the insulating layer 320 may be a semi-cured film or a resin layer. The inner wiring substrate 31 has a surface 310a and includes a wiring layer 312 located inside the surface 31A, and the wiring layer 330' is opposed to the inner wiring layer 312. Referring to Figures 5F and 5G, the carrier plate 410 is removed, wherein the method of removing the carrier plate 410 may employ an etching process, such as a wet etching process. Since the material of the carrier plate 410 is different from the material of the barrier layer 420, when the carrier plate 410 is removed by a wet etching process, the carrier plate 41 can be etched, but the barrier layer 42 is difficult to be etched. 〇 etching solution. Thus, the barrier layer 42 can protect the wiring layer 33 from being damaged by the etching solution. In addition, since the material of the barrier layer 420 may be nickel, tin or other non-copper metal, and the material of the carrier plate 41〇 may be copper or aluminum, the etching solution may be an alkaline etching solution. Referring to FIG. 5G and FIG. 5H, the barrier layer 420 is removed, and the method of the barrier layer 420 may be performed by a secret engraving process, such as a fishing remnant process. After the barrier layer 420 is completely removed, the wiring layer = 微 may be microetched so that the first electrode 332a does not directly contact the second electrode 332b to cause a short circuit. Referring to Figure 51, a drilling process is then performed on the insulating layer 32 to form a blind hole B2 that partially exposes the inner circuit layer 312, wherein the drilling process can be a laser drilling. 8 17 1342171 0705007 26514twf.doc/n Referring to FIG. 5J, afterwards, the blind via B2 is subjected to a fill-hole electric town process to form a die hole structure 350 connected between the circuit layer 330 and the inner circuit layer 312. The hole filling electroplating process includes an electroless keying method and a method of mining. Referring to Fig. 5K, a mask layer lion' having a material and a mask layer 37A may be formed, wherein the mask layer covers the insulating layer 34 and the conductive blind via structure 35 is exposed. Referring to FIG. 5L′, at least a first pad 334a connecting the first electrode and a second alignment (not shown) connecting at least the second electrode 332b are formed, wherein the first interface 334a and the second connection塾 and line: layer 330' is on the side of insulating layer 320. Referring to Figures 5L and 5M, then, the mask layer = 〇 is removed comprehensively. Thus, basically, a buried capacitive element circuit board 3 has been manufactured. In addition, in the embodiment, the solder resist layer 36 is further formed, wherein the solder resist layer 360 covers and contacts the dielectric material 34A, and the solder resist layer 36 smashes the first pad 334a and the second pad' The embedded capacitive element circuit board 3 can be connected to an electronic component, such as a passive component or a wafer. In summary, the present invention enables a wafer to be connected to a cell element of a buried capacitive element circuit board only through a plurality of pads (e.g., a first pad) and a solder bump. Compared with the prior art, the present invention can greatly shorten the distance between the wafer and the capacitive element. Therefore, the buried capacitive element circuit board of the present invention has a good signal transmission product f and is suitable for use in the technical field of high frequency signal transmission. Although the present invention has been disclosed in the preferred embodiments as described above, it is not intended to be limited to the scope of the present invention. Any one of ordinary skill in the art may, without departing from the spirit and scope of the present invention, The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional embedded capacitor circuit board after assembling a wafer. Fig. 2A is a top plan view showing a buried capacitive element circuit board according to a first embodiment of the present invention. Fig. 2B is a cross-sectional view showing the buried capacitor element circuit board of Fig. 2A after assembling the wafer. Fig. 2C is a top plan view showing another buried capacitive element circuit board of the first embodiment of the present invention. 3A to 3G are schematic flow charts showing a method of manufacturing the buried capacitor element circuit board of Fig. 2B. Fig. 4 is a cross-sectional view showing a circuit board of a buried capacitor element according to a second embodiment of the present invention. 5A to 5M are schematic flow charts showing a method of manufacturing the buried capacitor element circuit board of Fig. 4. [Description of main component symbols] 10, 20: Wafers 100, 200, 200', 300: Buried capacitive component circuit board 13421171 0705007 26514twf.doc/n 110a, 110b: Copper wiring layer 114a: pads 130a, 130b, 260 360: 140: conductive via structure 152a: upper electrode 154: ceramic dielectric layer 112a, 112b: traces 120a, 120b: dielectric layer solder resist layer 150: buried capacitive element 152b: lower electrode
160a、160b、250 ' 350 :導電盲孔結構 210、310 :内層線路基板 210a、220a、310a、420a :表面 212、312 :内線路層 220、320 :絕緣層 234b :第二接蝥160a, 160b, 250' 350: conductive blind via structure 210, 310: inner layer circuit substrate 210a, 220a, 310a, 420a: surface 212, 312: inner wiring layer 220, 320: insulating layer 234b: second interface
410 :承載板 Bl、B2 :盲子L Dl、D2 :距離 S2 :焊料塊 V :方向 230、230’、330 :外線路層 232a、232a’、332a :第一電極 232b、232b’、332b :第二電極 234a、334a :第一接墊 240、340 :介電材料 270、370、380 :遮罩層 400 :基板 420 :阻障層 Cl、C2 :電容元件 S1 :焊球 ΤΙ、T2 :溝渠 20410: carrier plates B1, B2: blind sub-L Dl, D2: distance S2: solder bumps V: directions 230, 230', 330: outer circuit layers 232a, 232a', 332a: first electrodes 232b, 232b', 332b: Second electrode 234a, 334a: first pad 240, 340: dielectric material 270, 370, 380: mask layer 400: substrate 420: barrier layer Cl, C2: capacitive element S1: solder ball ΤΙ, T2: trench 20