200938023 _____________ kVf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電路板及其製造方法，且特別是 有關於一種埋入式電容元件電路板（circuit boatd with embedded capacitance component)以及其製造方法。 【先前技術】 在現今的電路板技術中，目前已發展出埋入式電容元 件電路板，而這種電路板本身已具有埋入式電容元件 (embedded capacitance component)，因此埋入式電容元 件電路板可以組裝較少數量的電容元件。 圖1是習知一種埋入式電容元件電路板在組裝晶片 (chip)之後的剖面示意圖。請參閱圖1，習知的埋入式電 容元件電路板100包括二銅線路層ll〇a、110b、二介電層 120a、120b、二防焊層130a、130b、一導電通孔結構 (conductive through hole structure ) 140 以及一埋入式電容 ❹ 元件150 ’而埋入式電容元件電路板1〇〇能透過多顆焊球 S1來連接一晶片1〇。 埋入式電容元件150配置於介電層120a、120b之間， 且介電層120a、120b分別覆蓋埋入式電容元件150的相對 二表面。銅線路層110a、110b分別位於介電層120a、120b 上’而導電通孔結構140連接於銅線路層n〇a與銅線路層 110b之間。 銅線路層110a包括多條走線（trace) U2a以及多個 5 200938023 ------- — - - ^f.doc/n 接塾（pad) 114a，而銅線路層ll〇b包括多條走線（tmce) 112b。防焊層130a覆蓋這些走線112a，並暴露出這些接 墊114a ’而防焊層i3〇b則覆蓋這些走線112b。這些^球 S1連接於這些接墊114a與晶片10之間’以至於晶片1〇 能電性連接埋入式電容元件電路板1〇〇。 埋入式電谷元件150包括一上電極152a、一下電極 152b以及一陶瓷介電層154’其中上電極152a並未接觸於 ❹ 下電極152b，而陶瓷介電層154配置於上電極i52a與下 電極152b之間。另外，埋入式電容元件電路板1〇〇更包括 一對導電盲孔結構160a、160b，其中導電盲孔結構16〇a 連接於其中一個接墊114a與上電極152a之間，而導電盲 孔結構160b連接於另一個接墊H4a與下電極152b之間。 如此，晶片10能與埋入式電容元件150電性連接。 關於埋入式電容元件150，其形成方法通常採用以下 步驟。首先，在厚度約為35微米的銅箔上先後印刷一層陶 瓷介電材料以及一層銅膏。由於銅箔的厚度約為35微米， ® 因此銅箔的質地相當柔軟。接著，將陶瓷介電材料燒結。 如此，陶瓷介電材料得以形成陶瓷介電層154，而埋入式 電容元件150得以形成。 由於銅箔的質地相當柔軟，因此，整體而言，埋入式 電谷元件150的質地也是相當柔軟。倘若將埋入式電容元 件150壓合在線路板的外線路層中時，會因為埋入式電容 元件150的質地太過柔軟，以至於陶瓷介電層154難以座 落在正確的位置上，進而產生對準度太低的問題。 200938023 _ -_____ …vf-doc/n 為了避免產生埋入式電容元件150的對準产太低之 題，目前埋入式電容元件150都是形成在埋入^電容元件 電路板100的内線路層中（如圖i所示），而不會形成在 埋入式電容元件電路板1GG的外線路層（例如^路層 110a、11Gb)中，因此埋人式電容元件15()必須透過這^ 導電盲孔結構160a、160b以及這些焊球S1才能連接晶片 10。 曰曰 ❹ 目前已發現晶片1G與埋人式電容元件15G之間的距 離D1越短，將有助於大幅降低雜訊的干擾，而這種情形 在高頻訊號傳輸的技術領域中特別明顯。不過，受限於上 述埋入式電容元件150的對準度太低的問題，埋入式電容 元件150必須透過這些導電盲孔結構16〇a、16〇b以及這些 焊球S1才能連接晶片10〇如何進一步地縮短晶片1〇與埋 入式電容元件150之間的距離D1，以提高埋入式電容元件 電路板100的訊號傳輸品質，是目前值得探討的議題。 ❹ 【發明内容】 本發明提供一種埋入式電容元件電路板的製造方 法’其所製造出來的埋入式電容元件電路板能用來電性連 接晶片。 本發明另提供一種埋入式電容元件電路板的製造方 法，以縮短埋入式電容元件電路板與晶片之間的距離。 本發明提供一種埋入式電容元件電路板，其能用來電 性連接晶片。 7 200938023 •vf-doc/n =提供—種埋人式電容元件⑽板的製造方 以下步驟。首先，形成-絕緣層於-内層線路 二之内^中内層線路基板具有—表面，並包括一位於表 線，絕緣層上，外線路=4η 填入 連接第—電極之第—接墊以及至少一連接 二之第一接墊，而第一電極未接觸第二電極，且第 第二電極之間存有多條溝渠。接著，形成一連接 於外線路層與内線路層之間的導電盲孔結構。接著 一介電材料於這些溝渠中。 t發明之—實施财，以埋人式電容元件電路板 ^製仏方法更包括縣-防焊層，其中防焊層覆蓋並接觸 ”電材料’且防焊層暴露第—接墊與第二接塾。 f本發明之-實施财，上述軸導電盲孔結構的方 fj 1絕緣層進行-鑽孔製程，以形成—局部暴露内200938023 _____________ kVf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board and a method of manufacturing the same, and more particularly to a circuit boardd with embedded circuit board Capacitance component) and its manufacturing method. [Prior Art] In today's circuit board technology, a buried capacitive element circuit board has been developed, and such a circuit board itself has an embedded capacitance component, so a buried capacitive element circuit The board can assemble a smaller number of capacitive components. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing a conventional embedded capacitor circuit board after assembling a chip. Referring to FIG. 1 , a conventional buried capacitor device circuit board 100 includes a copper circuit layer 11a, 110b, two dielectric layers 120a and 120b, two solder resist layers 130a and 130b, and a conductive via structure. The through hole structure 140 and the buried capacitor 150 element 150' and the buried capacitor device board 1 can connect a wafer 1 through a plurality of solder balls S1. The buried capacitive element 150 is disposed between the dielectric layers 120a, 120b, and the dielectric layers 120a, 120b cover the opposite surfaces of the buried capacitive element 150, respectively. The copper wiring layers 110a, 110b are respectively located on the dielectric layers 120a, 120b' and the conductive via structures 140 are connected between the copper wiring layers n〇a and the copper wiring layers 110b. The copper circuit layer 110a includes a plurality of traces U2a and a plurality of 5 200938023 ------- - - ^f.doc/n pads 114a, and the copper circuit layer 11b includes Strip (tmce) 112b. The solder resist layer 130a covers the traces 112a and exposes the pads 114a' and the solder resist layer i3〇b covers the traces 112b. The ball S1 is connected between the pads 114a and the wafer 10 so that the wafer 1 can be electrically connected to the buried capacitor device board 1 . The buried cell element 150 includes an upper electrode 152a, a lower electrode 152b, and a ceramic dielectric layer 154'. The upper electrode 152a is not in contact with the lower electrode 152b, and the ceramic dielectric layer 154 is disposed on the upper electrode i52a. Between the electrodes 152b. In addition, the buried capacitive component circuit board 1 further includes a pair of conductive blind via structures 160a, 160b, wherein the conductive blind via structure 16A is connected between one of the pads 114a and the upper electrode 152a, and the conductive blind via The structure 160b is connected between the other pad H4a and the lower electrode 152b. As such, the wafer 10 can be electrically connected to the buried capacitive element 150. Regarding the method of forming the buried capacitor element 150, the following steps are generally employed. First, a layer of ceramic dielectric material and a layer of copper paste are printed successively on a copper foil having a thickness of about 35 microns. Since the thickness of the copper foil is about 35 microns, the texture of the copper foil is quite soft. Next, the ceramic dielectric material is sintered. Thus, the ceramic dielectric material is capable of forming the ceramic dielectric layer 154, and the buried capacitive element 150 is formed. Since the texture of the copper foil is relatively soft, the texture of the buried cell element 150 is also quite soft overall. If the buried capacitor element 150 is pressed into the outer circuit layer of the circuit board, the texture of the buried capacitor element 150 is too soft, so that the ceramic dielectric layer 154 is difficult to be seated in the correct position. This in turn creates the problem of too low alignment. 200938023 _ -_____ ...vf-doc/n In order to avoid the problem that the alignment of the buried capacitive element 150 is too low, the buried capacitive element 150 is formed on the inner circuit of the buried capacitor circuit board 100. In the layer (as shown in FIG. 1), it is not formed in the outer circuit layer (for example, the circuit layers 110a, 11Gb) of the buried capacitive element circuit board 1GG, so the buried capacitive element 15 () must pass through this ^ Conductive blind via structures 160a, 160b and these solder balls S1 can be connected to the wafer 10.曰曰 ❹ It has been found that the shorter the distance D1 between the wafer 1G and the buried capacitive element 15G, the smaller the interference, which will help to greatly reduce noise interference, which is particularly evident in the technical field of high-frequency signal transmission. However, limited by the problem that the alignment degree of the buried capacitive element 150 is too low, the buried capacitive element 150 must pass through the conductive blind via structures 16A, 16B and the solder balls S1 to connect the wafer 10. 〇 How to further shorten the distance D1 between the wafer 1〇 and the buried capacitive element 150 to improve the signal transmission quality of the embedded capacitive element circuit board 100 is a topic worthy of discussion at present. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a buried capacitive element circuit board. The buried capacitive element circuit board manufactured by the present invention can be used to electrically connect a wafer. The present invention further provides a method of fabricating a buried capacitive element circuit board to reduce the distance between the buried capacitive element circuit board and the wafer. The present invention provides a buried capacitive element circuit board that can be used to electrically connect a wafer. 7 200938023 •vf-doc/n=Provided as a manufacturer of buried capacitor elements (10) boards. First, the formation-insulating layer is in the inner layer line 2, the inner layer circuit substrate has a surface, and includes a surface line, an insulating layer, an outer line = 4η filled with a first pad connecting the first electrode, and at least A first pad is connected to the second electrode, and the first electrode is not in contact with the second electrode, and a plurality of trenches are stored between the second electrodes. Next, a conductive blind via structure connected between the outer wiring layer and the inner wiring layer is formed. A dielectric material is then placed in these trenches. The invention of the invention - the implementation of the buried capacitor element circuit board method further includes a county - solder mask, wherein the solder mask covers and contacts the "electric material" and the solder mask exposes the first pad and the second In the present invention, the square fj 1 insulating layer of the above-mentioned shaft conductive blind hole structure is subjected to a drilling process to form a partial exposure.
、、-之目孔。接著，對盲孔進行填孔電鍍製程（viafiuing plating) ° 孔 在本發明之-實施例中，上述鑽孔製程包括雷射鑽 在本發明之一實施例中 構同時形成。 上述外線路層與導電盲孔結 在本發明之-實施例中，上述填入介電材料的方法包 括印刷一有機介電材料於這此盖 在本發明之一實施例中電極與第二電極皆 8 200938023 wf.doc/n 為一梳狀電極。 本發明另提供一種埋入或雪六— 本盆勺扭本峨 式電谷兀件電路板的製造方 法/、匕括以下步驟。首先，在—基板上形成-線路層， =板包括-承載板與-配置於承载板上;：而 障層的材質不同。線路層形成於阻障層 -電極U雷先電:與一第二電極，第一電極未接觸第 -電極，且第-電極與第二電極之間存有多條溝^接著， 填入-介電材料於這些溝渠中。在填入介 =緣層，合基板於一内層線路基板上方…内層曰 面’並包括一位於表面之内線路層，而 ^層相：於内線路層。接著，依序移除承载板與阻障層。 =一連接於線路層與該内線路層之間的導電盲孔 …構。接者’形絲少-連接第—電極之第—接塾盘至 之第二接塾，其中第一接墊、第二接墊以 及線路層同在絕緣層的一側。 在=發明之—實施例中’上述填人介電㈣的方法包 :電：:陶莞介電材料於這些溝渠内。接著，燒崎 一半固化膠 在本發明之一實施例中，上述絕緣層包括 片或一樹脂層。 本發明又提供一種埋入式電容元件電路板，其包括一 線路基板、一絕緣層、一外線路層、—介電：料以及 一導電盲孔結構。内層線路基板具有-表面，並包括—位 於表面之内線路層。絕緣層配置於内線路層上。外線路層 200938023 -—vf.d〇c/n 緣:上’並包括—第-電極、一第二電極、至少 二接参，^極之第—接墊以及至卜連接第二電極之第 二 ’、中第一電極未接觸第二電極，且第一電極與第 之間存有多條溝渠。介電材料配置於這些溝渠内。 %孔結構連接於外線路層與内線路層之間。 在本發明之一實施例中，上述第一電極與第二電極皆 位於絕緣層與介電材料之間。 在本發明之—實施例中，上述埋入式電容元件電路板 匕括一防焊層，而防焊層覆蓋並接觸介電材料，並暴露 第一接墊與第二接塾。 ' 在本發明之一實施例中，上述第一電極與第二電極皆 位於防焊層與介電材料之間。 一基於上述，本發明的埋入式電容元件電路板，其電容 兀件與晶>{之間具有較短的距離。相較於習知技術而言， 本發明的埋人式電容元件電路板具有良好的訊號傳 質。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉較佳實關’並配合所關式，料細說明如下。 【實施方式】 【第一實施例】 圖2Α是本發明第一實施例之一種埋入式電容元件電 路板的俯視示意圖，而圖2Β是圖2Α中的埋入式電容元件 電路板在組裝晶片後的剖面示意圖，其中圖2β是從圖2Α 200938023 v£doc/n 中的線I-I剖面而得。請參閱圖2A與圖2B，埋入式電容 元件電路板200包括一内層線路基板21〇、，絕緣層220、 一外線路層230、一介電材料240以及一導電盲孔結構250。,, - the eye hole. Next, viafiuing plating is performed on the blind vias. In the embodiment of the present invention, the above drilling process includes a laser drill which is simultaneously formed in an embodiment of the present invention. The outer wiring layer and the conductive blind via junction are in the embodiment of the invention, wherein the method of filling the dielectric material comprises printing an organic dielectric material to cover the electrode and the second electrode in an embodiment of the invention. All 8 200938023 wf.doc/n is a comb electrode. The present invention further provides a method for manufacturing a buried or snow-six-potted torsion-type electric grid element circuit board, and includes the following steps. First, a circuit layer is formed on the substrate, and the = plate includes a carrier plate and a - disposed on the carrier plate; and the material of the barrier layer is different. The circuit layer is formed on the barrier layer-electrode U: first and second electrodes, the first electrode is not in contact with the first electrode, and there are a plurality of trenches between the first electrode and the second electrode, and then filled in - Dielectric materials are in these trenches. In the filling of the dielectric layer, the substrate is over an inner wiring substrate, the inner layer, and includes a wiring layer located in the surface, and the layer is in the inner wiring layer. Then, the carrier board and the barrier layer are sequentially removed. = a conductive blind via connected between the circuit layer and the inner circuit layer. The connector has a small number of wires - the first electrode of the first electrode is connected to the second port of the electrode, wherein the first pad, the second pad and the circuit layer are on the same side of the insulating layer. In the invention - in the embodiment, the method of filling the dielectric (4) is as follows: electricity:: Tao Wan dielectric material in these trenches. Next, the sacrificial half-cured adhesive In one embodiment of the invention, the insulating layer comprises a sheet or a resin layer. The invention further provides a buried capacitive element circuit board comprising a circuit substrate, an insulating layer, an outer circuit layer, a dielectric material and a conductive blind hole structure. The inner wiring substrate has a surface and includes a wiring layer located within the surface. The insulating layer is disposed on the inner circuit layer. External circuit layer 200938023 - vf.d 〇 c / n edge: upper 'and includes - the first electrode, a second electrode, at least two contacts, the first pad of the ^ pole and the second electrode of the second electrode The second electrode is not in contact with the second electrode, and there are a plurality of trenches between the first electrode and the first electrode. Dielectric materials are disposed in the trenches. The % hole structure is connected between the outer circuit layer and the inner circuit layer. In an embodiment of the invention, the first electrode and the second electrode are both located between the insulating layer and the dielectric material. In an embodiment of the invention, the buried capacitive component circuit board includes a solder mask layer, and the solder resist layer covers and contacts the dielectric material and exposes the first pad and the second pad. In an embodiment of the invention, the first electrode and the second electrode are both located between the solder resist layer and the dielectric material. Based on the above, the buried capacitive element circuit board of the present invention has a short distance between the capacitance element and the crystal. Compared with the prior art, the buried capacitive element circuit board of the present invention has good signal quality. In order to make the above features and advantages of the present invention more comprehensible, the following is a preferred embodiment of the present invention. [Embodiment] FIG. 2A is a schematic plan view of a buried capacitive element circuit board according to a first embodiment of the present invention, and FIG. 2A is a buried capacitive element circuit board of FIG. A schematic cross-sectional view, in which Figure 2β is obtained from the line II profile in Figure 2Α 200938023 v£doc/n. Referring to FIG. 2A and FIG. 2B, the buried capacitor device circuit board 200 includes an inner circuit substrate 21, an insulating layer 220, an outer circuit layer 230, a dielectric material 240, and a conductive blind via structure 250.
内層線路基板210具有一表面21〇a，益包括一位於表 面210a之内線路層212。在其他未繪示的實施例中’内層 線路基板210更可以包括内線路層212以外的線路層。或 者，内層線路基板210亦可以僅包括内線路層212，即内 層線路基板210可以是一層線路層。絕緣層220配置於内 線路層212上’而外線路層230配置於絕緣層220上，其 中導電盲孔結構250連接於外線路層230與内線路層212 之間。 外線路層230配置於絕緣層220上，並包括一第一電 極232a、一第二電極232b、一第一接墊234a以及一第二 接墊234b，其中第一接墊234a連接第一電極232a，而第 二接墊234b連接第二電極232b，其中第一電極232&未 觸第二電極232b。 第-電極2似與第二電極可以皆為梳狀電極， 而第一電極232a與第二電極232b之間存有多條溝渠丁玉， 其中介電材料24G配置於這些溝渠T1内。介電材料、2如、 第電極232a與第一電極232b能構成一電容元件匚卜 =-電極232a與第二電極232b可以皆位在絕緣層22〇 = 介電材料240之間。 一The inner wiring substrate 210 has a surface 21A, which includes a wiring layer 212 located inside the surface 210a. In other embodiments not shown, the inner wiring substrate 210 may further include a wiring layer other than the inner wiring layer 212. Alternatively, the inner wiring substrate 210 may include only the inner wiring layer 212, that is, the inner wiring substrate 210 may be a wiring layer. The insulating layer 220 is disposed on the inner wiring layer 212, and the outer wiring layer 230 is disposed on the insulating layer 220, wherein the conductive blind via structure 250 is connected between the outer wiring layer 230 and the inner wiring layer 212. The outer circuit layer 230 is disposed on the insulating layer 220 and includes a first electrode 232a, a second electrode 232b, a first pad 234a, and a second pad 234b. The first pad 234a is connected to the first electrode 232a. The second pad 234b is connected to the second electrode 232b, wherein the first electrode 232& does not touch the second electrode 232b. The first electrode 2 and the second electrode may both be comb electrodes, and a plurality of trenches are disposed between the first electrode 232a and the second electrode 232b, wherein the dielectric material 24G is disposed in the trenches T1. The dielectric material, 2, the first electrode 232a and the first electrode 232b can form a capacitive element. The electrode 232a and the second electrode 232b can be positioned between the insulating layer 22 〇 = the dielectric material 240. One
11 200938023 vf.doc/n 如被動S件），其中焊料塊S2例如是焊球。由於第一接 墊234a與第二接墊234b分別連接第—電極232a與第二電 極232b，因此晶片20可以僅透過第—接墊234a、第二接 墊234b以及這些焊料塊S2來連接電容元件c卜相較於習 头技術而s (可參閱圖1)，晶片2〇與電容元件之間 存有較短的距離D2。因此，埋人式電容元件電路板2〇〇 具有良好的喊傳輸品質’且適合應用在高娜號傳輸的 技術領域中。 在本實施例中，埋入式電容元件電路板2⑻更包括一 防=層260。防焊層260覆蓋並接觸介電材料24〇，以保護 電容元件cn。此外，防焊層260暴露第一接墊234a與第 二接墊234b，以使第一接墊234a以及第二接墊23仆能夠 連接晶片20。 圖2C是本發明第一實施例之另—種埋入式電容元件 電路板的俯視示意圖。請參閱圖2C’埋入式電容元件電路 板200’與埋入式電容元件電路板2〇〇二者剖面結構大體相 同，而埋入式電容元件電路板200,包括一外線路層23〇，。 外線路層230’包括一第一電極232a，、一第二電極 232b’、多個第一接墊234a以及多個第二接墊23仆。針對 不同的電路設計與產品需求，第一電極232a，可以連接這 些第一接墊234a，而第二電極232b，可以連接這些第二接 墊234b。因此，在本發明中，埋入式電容元件電路板可以 包括一個或多個連接第一電極的第一接墊，以及一個或多 個連接第二電極的第二接墊。 12 wfdoc/n ❹ ❹ 200938023 奮rif介紹本實施例之埋人式電容元件電路板200與 的⑺構，接下來將以圖2B所示的埋入式電容元件電路 板200為例並配合圖3A至圖3G，以詳細介紹本實施例 之埋入式電容元件電路板200的製造方法。 圖3A至圖3G是圖2B中埋入式電容元件電路板的製 意圖。請參閲圖3A，有關埋入 ?造方法’首先’形成絕緣層220於内層線 内i二J ’其令絕緣層220覆蓋内層線路基板2i〇的 '•主i關国’而絕緣層220可以是樹脂層或半固化膠片。 以带Γ = 接著，對絕緣層220進行一鑽孔製程， 暴露内線路層212之盲孔bi，其中鑽孔製程 =疋^^孔或其他適t的鑽孔製程。在形成盲孔m 絕緣層22〇的表面2施粗輪化，並且進行去 〜it ’以凊潔盲孔B1所暴露的部分内線路層212。 声22^1閱’接著’可以形成—遮罩層270於絕緣 i層270之二遮罩層謂局部覆蓋表面⑽。在形成遮 二子μ r二可以用無電電鐘法來形成—厚度很薄的電 Ζ )於絕緣層22G的表面22〇a上以及盲孔 mmr。遮罩層謂可以是澄式光阻或是乾膜（吻 上，^外Hi ’接考，形成外線路層23G於絕緣層220 上，、中外線路層230包括第一電極232a、第二 第-接墊234a以及第二接墊屬（請參考圖2a)。、 由於在形成遮罩層270之前，可以用無電電鑛法來形 13 200938023 vf.d〇c/n 成電锻種子層’因此，藉由該電鏡種子層，外線路層230 用電鍍法來形成。此外，透過遮罩層270，外線路 曰 所包括的第一電極232a與第二電極232b皆可 狀電極（請參相2A)。 為梳 e nn f 了形成外線路層230之外，亦形成連接於外線路層 二内線路層212之間的導電盲孔結構25〇。在本實施例 ，形成導電盲孔結構250的方法可以是對盲孔B1進行 填孔電鍵製程，喊由前賴紐種子層，導電盲孔結構 250可以與外線路層230同時形成。 請參閱圖3D與圖3E，接著，全面性地移除遮罩層 =〇，以使第一電極232a與第二電極232b之間形成這些^ 木τι。在全面性地移除遮罩層27〇之後可以對外線路層 230進行微蝕刻（micr〇_etching)，以使第一電極汪不 會與第二電極232b直接電性接觸而造成短路。 請參閱圖3F，接著，填入介電材料24〇於這些溝渠 T1中，其中填入介電材料240的方法可以是印刷—有機^ ❹ 電材料於這麟渠T1 N。此外，印刷該有機介電材料的 方式可以是鋼板印刷、絲板印刷或其他網印的方式。在填 入介電材料240之後，基本上一種埋入式電容元件電路板 200以製造完成。 請參閱圖3G，接著，形成覆蓋介電材料240的防焊 層260 ’其中防焊層260更與介電材料24〇接觸，並暴露 第一接墊234a與第二接墊234b (請參考圖2A)。此外， 圖3G所示的防焊層260之類型為防焊層定義（s〇lderMask 200938023 vfdoc/n11 200938023 vf.doc/n as passive S), wherein the solder bump S2 is, for example, a solder ball. Since the first pad 234a and the second pad 234b are respectively connected to the first electrode 232a and the second electrode 232b, the wafer 20 can be connected to the capacitor element only through the first pad 234a, the second pad 234b, and the solder bumps S2. Compared with the head technology (see Figure 1), there is a short distance D2 between the wafer 2 and the capacitive element. Therefore, the buried capacitive element circuit board 2 has good shouting transmission quality and is suitable for use in the technical field of the Gona transmission. In the present embodiment, the buried capacitive element circuit board 2 (8) further includes an anti-layer 260. The solder resist layer 260 covers and contacts the dielectric material 24A to protect the capacitive element cn. In addition, the solder resist layer 260 exposes the first pads 234a and the second pads 234b such that the first pads 234a and the second pads 23 are capable of connecting the wafers 20. Fig. 2C is a top plan view showing another buried capacitor element circuit board according to the first embodiment of the present invention. Referring to FIG. 2C, the buried capacitor element circuit board 200' and the buried capacitor element circuit board 2 have substantially the same cross-sectional structure, and the buried capacitor element circuit board 200 includes an outer circuit layer 23A. . The outer circuit layer 230' includes a first electrode 232a, a second electrode 232b', a plurality of first pads 234a, and a plurality of second pads 23. For the different circuit design and product requirements, the first electrode 232a can be connected to the first pads 234a, and the second electrode 232b can be connected to the second pads 234b. Therefore, in the present invention, the buried capacitive element circuit board may include one or more first pads connected to the first electrodes, and one or more second pads connected to the second electrodes. 12 wfdoc/n ❹ ❹ 200938023 奋rif introduces the buried capacitor element circuit board 200 and (7) structure of the present embodiment, and then takes the buried capacitor element circuit board 200 shown in FIG. 2B as an example and cooperates with FIG. 3A. 3G, a method of manufacturing the buried capacitive element circuit board 200 of the present embodiment will be described in detail. 3A to 3G are schematic views of the buried capacitive element circuit board of Fig. 2B. Referring to FIG. 3A, regarding the embedding method, the insulating layer 220 is first formed in the inner layer line, and the insulating layer 220 covers the inner layer substrate 2i, and the insulating layer 220 is provided. It may be a resin layer or a semi-cured film. Taking the tape Γ = Next, a drilling process is performed on the insulating layer 220 to expose the blind hole bi of the inner circuit layer 212, wherein the drilling process is 疋^^ hole or other suitable drilling process. The surface 2 forming the blind hole m insulating layer 22 is roughened, and a portion of the inner wiring layer 212 which is exposed to the blind hole B1 is removed. The sound 22^1 read 'and then' may be formed - the mask layer 270 is in the insulating i layer 270 and the two mask layers are referred to as partial covering surfaces (10). In forming the mask, the second electrode can be formed by the electroless clock method to form a thin film having a thin thickness on the surface 22a of the insulating layer 22G and the blind hole mmr. The mask layer may be a clear photoresist or a dry film (on the kiss, ^Hi', forming the outer circuit layer 23G on the insulating layer 220, and the middle and outer circuit layer 230 includes the first electrode 232a, the second a pad 234a and a second pad genus (please refer to FIG. 2a). Since the mask layer 270 is formed, the electroless ore method can be used to form 13 200938023 vf.d〇c/n into an electric forging seed layer. Therefore, the outer circuit layer 230 is formed by electroplating by the electron beam seed layer. Further, through the mask layer 270, the first electrode 232a and the second electrode 232b included in the outer circuit port are all electrode-shaped (see phase 2A). In addition to forming the outer wiring layer 230, a conductive blind via structure 25 is formed between the inner wiring layers 212 of the outer wiring layer. In this embodiment, the conductive blind via structure 250 is formed. The method may be to perform a hole-filling key process on the blind hole B1, and the conductive blind hole structure 250 may be formed simultaneously with the outer circuit layer 230. Referring to FIG. 3D and FIG. 3E, then, the overall displacement is performed. The mask layer = 〇 is formed so that these are formed between the first electrode 232a and the second electrode 232b. The wooden circuit layer 230 may be microetched (micr〇_etching) after the mask layer 27 is completely removed, so that the first electrode does not directly contact the second electrode 232b to cause a short circuit. Referring to FIG. 3F, a dielectric material 24 is then filled in the trenches T1. The method of filling the dielectric material 240 may be to print an organic material to the land T1 N. Further, printing the The organic dielectric material may be in the form of steel plate printing, silk screen printing or other screen printing. After filling the dielectric material 240, substantially a buried capacitive element circuit board 200 is manufactured. See Figure 3G. Next, a solder resist layer 260' covering the dielectric material 240 is formed, wherein the solder resist layer 260 is further in contact with the dielectric material 24, and exposes the first pad 234a and the second pad 234b (please refer to FIG. 2A). The type of solder resist layer 260 shown in FIG. 3G is a solder mask definition (s〇lderMask 200938023 vfdoc/n
Define，SMD) ’但是在其他未繪示的實施例中，防焊層 260之類型亦可以為非防焊層定義（Non_s〇lder Mask Define，NSMD )。 【第二實施例】 圖4是本發明第二實施例之一種埋入式電容元件電路 板的的剖面示意圖。請參閱圖4 ’本實施例的埋入式電容 元件電路板300亦包括一内層線路基板31〇、一絕緣層 320、一外線路層330、一介電材料340、一導電盲孔結構 350以及一防焊層360,而外線路層330包括第一電極 332a、第二電極332b、第一接墊334a以及第二接墊（未 繪示）’其中介電材料340、第一電極332a與第二電極332b 能構成一電容元件C2。 埋入式電容元件電路板300的結構、功效與功能皆與 前述實施項相似，而且以方向V觀看埋入式電容元件電路 板300所得到的俯視示意圖與圖2A、2c大體相同。也就 是說’在本實施例中，當從方向V觀看埋入式電容元件電 ❹ 路板30〇時，可以發現第一電極332a與第二電極332b皆 為梳狀電極。 有關本實施例與第一實施例相同及相似的特徵，以下 不再贅述，而二者差異之處在於：第一電極332a與第二電 極332b皆位於防焊層36〇與介電材料34〇之間，且第一電 極332a與第二電極332b可以被防焊層36〇以及介電材料 340所包覆。 〆 圖5A至圖5M是圖4中埋入式電容元件電路板的製 15 vf.doc/n 200938023 造方法之流程示意圖。請參閱圖5A，有關埋入式電容元件 電路板300的製造方法，首先’提供一基板400，其包括 一承載板410與一阻障層420，而阻障層42〇配置於承载 板410上。承載板410的材質與卩且障層420的材質不同， 其中阻障層420的材質巧*以是鎳、錫或是其他非銅的金 屬，而承載板410的材質可以是鋼或銘。 請參閱圖5B，接著，可以形成一遮罩層370於阻障 層420上，其中遮罩層370局部覆蓋阻障層42〇的表面 ® 420a。在形成遮罩層370之知’可以先對表面420a粗鏠化， 接著用無電電鑛法來形成一厚度彳艮薄的電鑛種子層（未繚 示）於表面420a上。此外，遮罩層370可以是溼式光阻或 是乾膜。 請參閱圖5C，接著，在一基板4〇〇上形成一線路層 330’，其中線路層330’是形成於阻障層42〇上，而線路層 330’包括一第一電極332a與一第二電極332b。此外，線 路層330’可以利用電鍍法來形成。 、 〇 明參閱圖5C與圖5D，接著，全面性地移除遮罩層 370 ’以使第一電極332a與第二電極332b之間形成多 渠T2。 ’、丹 請參閱圖5E，接著，填入介電材料34〇於這些溝渠 T2中’其中填入介電材料34〇的方法可以包括以下;驟。' 首先，印刷一陶竟介電材料於這些溝渠T2内。接 結該陶曼介電材料，以形成介電材料340。由此可知，人 電材料340可以是由陶曼介電材料所形成。此外，印刷^ 16 vf.doc/n 200938023 陶甍介電材料的方式可以是鋼板印刷、絲板印刷或其他網 印的方式。 請參閱圖5F ’在形成介電材料340之後，藉由絕緣層 32〇，壓合基板4〇〇於内層線路基板·上方，其中絕緣層 32〇可以是半固化膠片或樹脂層。内層線路基板31〇具有 一表面310a’並包括—位於表面31〇a之内線路層312，且 線路層330’相對於内線路層μ】。Define, SMD) 'But in other embodiments not shown, the type of solder resist layer 260 may also be a non-solder mask definition (NSMD). [Second Embodiment] Fig. 4 is a cross-sectional view showing a circuit board of a buried capacitor element according to a second embodiment of the present invention. Referring to FIG. 4 , the embedded capacitive device circuit board 300 of the present embodiment further includes an inner circuit substrate 31 , an insulating layer 320 , an outer circuit layer 330 , a dielectric material 340 , a conductive blind via structure 350 , and a solder resist layer 360, and the outer circuit layer 330 includes a first electrode 332a, a second electrode 332b, a first pad 334a, and a second pad (not shown), wherein the dielectric material 340, the first electrode 332a and the first The two electrodes 332b can constitute a capacitive element C2. The structure, function, and function of the buried capacitive element circuit board 300 are similar to those of the foregoing embodiment, and the top view of the buried capacitive element circuit board 300 viewed in the direction V is substantially the same as that of Figs. 2A and 2c. That is to say, in the present embodiment, when the buried capacitive element circuit board 30 is viewed from the direction V, it can be found that both the first electrode 332a and the second electrode 332b are comb electrodes. The same and similar features of the present embodiment and the first embodiment are not described below, and the difference between the two is that the first electrode 332a and the second electrode 332b are located on the solder resist layer 36 and the dielectric material 34. Between the first electrode 332a and the second electrode 332b may be covered by the solder resist layer 36 and the dielectric material 340. 〆 FIG. 5A to FIG. 5M are schematic diagrams showing the flow of the method of manufacturing the embedded capacitive element circuit board of FIG. 4 . Referring to FIG. 5A, a method for manufacturing a buried capacitive device circuit board 300 is first provided with a substrate 400 including a carrier 410 and a barrier layer 420, and the barrier layer 42 is disposed on the carrier 410. . The material of the carrier plate 410 is different from that of the barrier layer 420. The material of the barrier layer 420 is nickel, tin or other non-copper metal, and the material of the carrier plate 410 may be steel or inscription. Referring to FIG. 5B, a mask layer 370 may be formed on the barrier layer 420, wherein the mask layer 370 partially covers the surface of the barrier layer 42 ® 420a. The surface 420a may be roughened prior to the formation of the mask layer 370, and then an electroless mineralization method is used to form a thin layer of an electric ore seed layer (not shown) on the surface 420a. Additionally, mask layer 370 can be a wet photoresist or a dry film. Referring to FIG. 5C, a circuit layer 330' is formed on a substrate 4, wherein the circuit layer 330' is formed on the barrier layer 42A, and the circuit layer 330' includes a first electrode 332a and a first layer. Two electrodes 332b. Further, the wiring layer 330' can be formed by electroplating. Referring to Figures 5C and 5D, the mask layer 370' is then removed in its entirety to form a plurality of channels T2 between the first electrode 332a and the second electrode 332b. Referring to FIG. 5E, a method of filling the dielectric material 34 into the trenches T2 and filling the dielectric material 34A may include the following steps; First, a ceramic material is printed in these trenches T2. The Taman dielectric material is bonded to form a dielectric material 340. It can be seen that the human material 340 can be formed of a Tauman dielectric material. In addition, the method of printing ceramic materials can be steel plate printing, silk screen printing or other screen printing methods. Referring to FIG. 5F', after the dielectric material 340 is formed, the substrate 4 is laminated on the inner wiring substrate by the insulating layer 32, wherein the insulating layer 32 may be a semi-cured film or a resin layer. The inner wiring substrate 31 has a surface 310a' and includes a wiring layer 312 located inside the surface 31A, and the wiring layer 330' is opposed to the inner wiring layer.
请參閱圖5F與圖5G，接著，移除承載板41〇，其中 移除承載板彻的方法可以採祕刻製程，例如是溼式餘 刻製程。由於承載板41〇的材質與阻障層42〇的材質不同， 因此當移除承餘41G的方法是採舰式侧製程時，可 以，用忐蝕刻承載板41〇，但卻難以蝕刻阻障層42〇的蝕 刻藥，。如此，阻障層42〇可以保護線路層33〇，以避免 蝕刻藥液所損傷。此外，由於阻障層42〇的材質可以是鎳、 錫或是其他非銅的金屬，而承載板41G的材質可以是鋼或 鋁，因此上述蝕刻藥液可以選用鹼性蝕刻液。 凊參閱圖5G與圖5H，接著，移除阻障層420，其中 移=阻障層的方法可雜祕刻製程，例如是座式餘 刻製程。在全面性地移除阻障層42〇之後，可以對線路屉 330進行微姓刻，以使第一電極332a不會與第二電極9 直接電性接觸而造成短路。 、，請參閱圖51，接著，對絕緣層320進行一鑽孔製程，Referring to Figures 5F and 5G, the carrier plate 41 is removed, wherein the method of removing the carrier plate can be performed by a secret process such as a wet residual process. Since the material of the carrier plate 41〇 is different from the material of the barrier layer 42〇, when the method of removing the residual 41G is a ship-side process, the carrier plate 41 can be etched, but it is difficult to etch the barrier. Layer 42 蚀刻 etching agent. Thus, the barrier layer 42A can protect the wiring layer 33〇 from damage by the etching solution. In addition, since the material of the barrier layer 42A may be nickel, tin or other non-copper metal, and the material of the carrier plate 41G may be steel or aluminum, the etching solution may be an alkaline etching solution. Referring to Figures 5G and 5H, the barrier layer 420 is removed, wherein the method of shifting the barrier layer can be performed by a process such as a paddle process. After the barrier layer 42 is completely removed, the line drawer 330 can be slightly imprinted so that the first electrode 332a does not directly make electrical contact with the second electrode 9 to cause a short circuit. Referring to FIG. 51, a drilling process is performed on the insulating layer 320,
，形成-局部暴露内線路層312之盲孔B2，其中該鑽^ 程可以為雷射鑽孔。 I 17 wf.doc/n 200938023 請參閱圖5J ’之後，對盲孔B2進行填孔 以形成一連接於線路層330,與内線路層312之間的導電盲 孔、、’。構350，其中該填孔電鍍製程包括無電電鍍法以及電 鑛法。 請參閱圖5K，之後’可形成材質與遮罩層37〇相同 的遮罩層380，其中遮罩層38〇覆蓋絕緣層32〇與介電材 料340 ’並且暴露出導電盲孔結構35〇。 斤睛參閱圖5L，之後，形成至少一連接第一電極332a 之第一接墊334a以及至少一連接第二電極332b之第二接 塾（未繪示），其中第-接塾334a、第二接塾以及線^層 330’同在絕緣層320的一側。 言月參閱圖5L與圖5M，接著，全面性地移除遮罩層 380。如此，基本上一種埋入式電容元件電路板3〇〇已製造 完成。此外，在本實施例中，更可以形成防焊層36〇，其 中防焊層360覆蓋並接觸介電材料34〇，且防焊層36〇& 露第一接墊334a與第二接墊，以使埋入式電容元件電路板 〇 300能連接電子元件，其例如是被動元件或晶片。 綜上所述，本發明能使晶片僅透過多個接墊（例如第 一、二接墊）以及焊料塊來連接埋入式電容元件電路板的 電容元件。相較於習知技術而言，本發明能大幅縮短晶片 與電容元件之間的距離。因此，本發明的埋入式電容元件 電路板具有良好的訊號傳輸品質，並適合應用在高頻訊號 傳輸的技術領域中。 雖然本發明已以較佳實施例揭露如上，然其並非用以 18 200938023 vf.doc/n 所屬技術領域中具有通常知識者，在不 和範圍内’當可作些許之更動與潤飾， =本發月之保魏圍當視後附之申請專利範圍所界定者 【圖式簡單說明】 圖1是習知一種埋入式電容元件電路板在組裝晶片之 後的剖面示意圖。 ® ® 2A是本發明第—實關之—種埋人式電容元件電 路板的俯視示意圖。 圖2B是圖2A中的埋入式電容元件電路板在組裝晶片 後的剖面示意圖。 圖2C是本發明第一實施例之另一種埋入式電容元件 電路板的俯視示意圖。 圖3A至圖3G是圖2B中埋入式電容元件電路板的製 造方法之流程不意圖。 〇 圖4疋本發明第二實施例之一種埋入式電容元件電路 板的的剖面示意圖。 圖5A至圖5M是圖4中埋入式電容元件電路板的製 造方法之流程示意圖。 【主要元件符號說明】 10、20 ·晶片 100、200、200’、300 :埋入式電容元件電路板 vf-doc/n 200938023 110a、110b :銅線路層 112a、112b :走線 114a :接墊 120a、120b :介電層 130a、130b、260、360 :防焊層 140 :導電通孔結構 150 :埋入式電容元件 152a :上電極 152b :下電極 154 :陶瓷介電層 160a、160b、250、350 :導電盲孔結構 210、310 :内層線路基板 〇 210a、220a、310a、420a :表面 212、312 :内線路層 220、320 :絕緣層 234b :第二接墊 410 :承載板 B卜B2 :盲孔 Dl、D2 :距離 S2 :焊料塊 V :方向 230、230,、330 :外線路層 232a、232a’、332a :第一電極 232b、232b’、332b :第二電極 234a、334a :第一接墊 240、340 :介電材料 270、370、380 :遮罩層 ❹ 400 :基板 420 :阻障層 cn、C2 :電容元件 si:焊球 ΤΙ、T2 :溝渠 20Forming a blind hole B2 that partially exposes the inner circuit layer 312, wherein the drilling process may be a laser drilling. I 17 wf.doc/n 200938023 Referring to FIG. 5J', the blind via B2 is filled to form a conductive via, which is connected between the wiring layer 330 and the inner wiring layer 312. Structure 350, wherein the fill-hole plating process comprises electroless plating and electro-mineralization. Referring to Fig. 5K, a mask layer 380 having the same material as the mask layer 37 can be formed, wherein the mask layer 38 covers the insulating layer 32 and the dielectric material 340' and exposes the conductive blind via structure 35A. Referring to FIG. 5L, at least one first pad 334a connecting the first electrode 332a and at least one second port (not shown) connecting the second electrode 332b are formed, wherein the first port 334a, the second The interface and the line layer 330' are on the same side of the insulating layer 320. Referring to Figures 5L and 5M, the mask layer 380 is then removed comprehensively. Thus, basically a buried capacitive element circuit board 3 has been manufactured. In addition, in the embodiment, the solder resist layer 36 is further formed, wherein the solder resist layer 360 covers and contacts the dielectric material 34A, and the solder resist layer 36〇& exposes the first pad 334a and the second pad In order to enable the buried capacitive element circuit board 300 to be connected to an electronic component, such as a passive component or a wafer. In summary, the present invention enables a wafer to be connected to a capacitive element of a buried capacitive element circuit board only through a plurality of pads (e.g., first and second pads) and solder bumps. Compared with the prior art, the present invention can greatly shorten the distance between the wafer and the capacitive element. Therefore, the buried capacitive element circuit board of the present invention has good signal transmission quality and is suitable for use in the technical field of high frequency signal transmission. Although the present invention has been disclosed above in the preferred embodiments, it is not intended to be used in the technical field of the prior art, and may be modified and retouched within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a conventional buried capacitor circuit board after assembling a wafer. ® 2A is a top view of the buried-type capacitive element circuit board of the present invention. Fig. 2B is a cross-sectional view showing the buried capacitor element circuit board of Fig. 2A after assembling the wafer. Fig. 2C is a top plan view showing another buried capacitor element circuit board according to the first embodiment of the present invention. 3A to 3G are schematic flowcharts showing a method of manufacturing the buried capacitor element circuit board of Fig. 2B. Figure 4 is a cross-sectional view showing a buried capacitor element circuit board according to a second embodiment of the present invention. 5A to 5M are schematic flow charts showing a method of manufacturing the buried capacitor element circuit board of Fig. 4. [Description of main component symbols] 10, 20 · Wafers 100, 200, 200', 300: Buried capacitive component circuit board vf-doc/n 200938023 110a, 110b: Copper wiring layers 112a, 112b: Trace 114a: pads 120a, 120b: dielectric layer 130a, 130b, 260, 360: solder resist layer 140: conductive via structure 150: buried capacitor element 152a: upper electrode 152b: lower electrode 154: ceramic dielectric layer 160a, 160b, 250 350: conductive blind hole structure 210, 310: inner layer circuit substrate 〇210a, 220a, 310a, 420a: surface 212, 312: inner circuit layer 220, 320: insulating layer 234b: second pad 410: carrier board B b B2 : blind holes D1, D2: distance S2: solder bumps V: directions 230, 230, 330: outer circuit layers 232a, 232a', 332a: first electrodes 232b, 232b', 332b: second electrodes 234a, 334a: a pad 240, 340: dielectric material 270, 370, 380: mask layer ❹ 400: substrate 420: barrier layer cn, C2: capacitive element si: solder ball ΤΙ, T2: trench 20