201220457 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關一種封裝結構及其製法，尤指一種無 核〜板之嵌埋半導體元件之封裝結構及其製法。201220457 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a package structure and a method of fabricating the same, and more particularly to a package structure of a coreless-plate embedded semiconductor component and a method of fabricating the same.
【先前技術J[Prior Art J
[〇〇〇2] 隨著半導體封裝技術的演進，半導體裝置 (Semiconductor device)已開發出不同的封裝型態， 而該半導體裝置主要係在一封裝基板（package sub_ strate)裝置晶片，且將晶片電性連接在該封裝基板上， 接著再以膠體進行封裝；而為降低封裝高度，遂有將晶 片嵌埋在一封裝基板中，而此種封裝件能縮減整體半導 體裝置之體積並提昇電性功能，遂成為一種封裝的趨勢 [〇〇〇3] 凊參閱第1A至1E圖，係為習知嵌埋半導體元件之封 裝結構的剖視示意圖。 [0004] [0005] [0006] 如第1A圖所示’首先’提翁一具有貫穿之開口⑽之 核心板10，於該核心板10之上、下兩側具有内層線路1〇1 ，且於該核心板10中形成貫穿之導電通孔102，以電性連 接上、下兩侧之内層線路1 〇 1。 如第1B圖所示’於該核心板10底側設置一具有介電 材120a之承載板14，以將一具有複數電極塾之半導 體晶片11容置於該開口 100中，且藉由黏著層lla將該半 導體晶片11設於該介電材120a上。 如第1C圖所示，於該核心板1 〇上侧及半導體晶片11 099139081 表單蝙號A0101 第4頁/共24頁 0992068179-0 201220457 上壓合另一介電材120b，以使兩介電材丨2〇a，120b形成 介電層12，且該介電層12填入於該開口 1〇〇之孔壁與半導 體晶片11之間的間隙中，以將該半導體晶片丄j固定於該 開口 100中。接著，移除該承載板14。 [0007] 如第1D圖所示，於該上、下兩側之介電層12上形成 線路層13，且該線路層13具有位於該介電層12中並電性 連接該電極墊110與内層線路1〇1之導電盲孔13〇，又該 Ο [0008] 上側線路層13具有電性接觸墊130a，而下側線路層13具 有植球墊130b» 如第1E圖所示，於該上、下兩側之介電層12及線路 層13上形成防焊層15，且於該防焊層15中形成開孔150 ’以露出電性接觸墊13〇a及植球墊i3〇b» [0009] 〇 惟’習知技術中’需於該核心板10中形成開口 1〇〇， 以將該核心板1 〇兩側之介電層丨2壓擠該半導體晶片11， 導致該半導體晶片11產生偏移（如第1C圖所示，該半導 體晶片11與該開口丨〇〇之孔壁的左右間距分別為t，s，其 中t < s ) ’使該半導體晶片！ 1之成型偏移量約為+ / _ 1 〇 〇 以m，因而不易準確定位於該開口1〇〇中。因此，當該半 導體晶片11產生偏移時，該半導體晶片電極墊11〇不 易與該導電盲孔130精準對應以達成電性連接，如第1]}圖 所示，而容易產生電性連接之品質不良或失效的情況， 導致降低產品的良率。 再者’該半導體晶片11欲埋於該核心板10之開口 中，並無任何導熱及散熱的結構，使該半導體晶片1丨之 099139081 表單編號A0101 第5頁/共24頁 0992068179-0 [0010] 201220457 [0011] [0012] [0013] [0014] [0015] [0016] [0017] [0018] 散熱不易，容易導致該半導體晶月11因過熱而損壞。 又，厚度較薄之半導體晶片11需嵌埋於厚度較厚之 核心板10中，使整體結構之厚度因該核心板10而大幅增 加，導致產品的厚度增加，難以達到薄小化之目的。 另外，需於該核心板10之兩側進行線路製程，因而 需製作該導電通孔1 02以導通兩側内層線路1 01與線路層 13，不僅導致成本增加，且提高製作難度。 因此，如何避免習知技術中之種種缺失，實已成為 目前亟欲解決的課題。 【發明内容】 鑑於上述習知技術之種種缺失，本發明之一目的係 在提供一種對位較準之嵌埋半導體元件之封裝結構及其 製法。 本發明之又一目的係在提供一種提高散熱性之嵌埋 半導體元件之封裝結構及其製法。 本發明之再一目的係在提供一種薄小化之嵌埋半導 體元件之封裝結構及其製法。 本發明之另一目的係在提供一種降低成本之嵌埋半 導體元件之封裝結構及其製法。 為達上述及其他目的，本發明揭露一種嵌埋半導體 元件之封裝結構，係包括：第一介電層，係具有相對之 第一表面及第二表面；半導體晶片，係凸出嵌設於該第 一介電層之第二表面，該半導體晶片具有相對之作用面 099139081 表單編號A0101 第6頁/共24頁 0992068179-0 201220457 及非作用面，且於該作用面上具有位於該第一介電層中 之電極墊，而該非作用面及其相鄰之部分側面係凸出於 該第一介電層之第二表面；第一線路層，係設於該第一 介電層之第一表面上，並於該第一介電層中形成電性連 接該第一線路層與該電極墊之複數第一導電盲孔；增層 結構，係設於該第一介電層之第一表面及該第一線路層 上；以及絕緣保護層，係設於該增層結構上，並於該絕 緣保護層中形成複數開孔，以令該增層結構之部分表面 外露於該開孔中。 Ο [0019] 前述之封裝結構復包括金屬層，係設於該介電層之 第二表面上，且該金屬層具有開口，以令該半導體晶片 位於該開口中，以令該金屬層作為散熱件。又包括承載 層，係設於該金屬層及該半導體晶片之非作用面上，以 令該承載層作為散熱件，且形成該承載層之材質係為銅 〇 [0020] 〇 前述之封裝結構中，該增層結構係具有至少一第二 介電層、設於該第二介電層上之第二線路層、及設於該 第二介電層中且電性連接該第一與第二線路層之第二導 電盲孔，且令該增層結構之部分第二線路層表面外露於 該開孔中。 [0021] 前述之封裝結構復包括表面處理層，係設於該開孔 中之增層結構之外露表面上，且形成該表面處理層之材 料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金（ENIG )、化錄把浸金（ENEPIG)、化學鍍錫（Immersion Tin)及有機保焊劑（0SP)所組成之群組中之其中一者 099139081 表單編號A0101 第7頁/共24頁 0992068179-0 201220457 [0022] [0023] [0024] [0025] 本發明復提供一種嵌埋半導體元件之封裝結構之製 法，係包括：提供一具有相對之兩表面之核心板，且於 該核心板之兩表面上具有承載層；於該承載層上形成具 有開口之金屬層，以令該承載層之部分表面外露於該開 口中；於該開口中之承載層上設置半導體晶片，該半導 體晶片具有相對之作用面及非作用面，於該作用面上具 有電極墊，且該半導體晶片係以該非作用面結合至該開 口中之承載層上；於該金屬層及該半導體晶片上形成第 一介電層，且該第一介電層具有外露之第一表面及結合 至該金屬層上之第二表面；於該第一介電層之第一表面 上形成第一線路層，且於該第一介電層中形成複數電性 連接該第一線路層與該電極墊之第一導電盲孔；於該第 一介電層之第一表面及該第一線路層上形成增層結構； 於該增層結構上形成絕緣保護層，且於該絕緣保護層中 形成複數開孔，以令該增層結構之部分表面外露於該開 孔中；以及移除該核心板，以外露出該承載層。 前述之製法中，該核心板之兩表面與該承載層之間 具有離形層，以藉由該離形層移除該核心板。 前述之製法中，形成該承載層之材質係為銅。 前述之製法中，形成該金屬層之製程係包括··於該 承載層上形成阻層，且於該阻層上形成開口區，以令該 承載層之部分表面外露於該開口區；於該開口區之承載 層上形成該金屬層；以及移除該阻層，以形成該開口。 099139081 表單編號A0101 第8頁/共24頁 0992068179-0 201220457 [0026] 前述之製法中，該增層結構係具有至少一第二介電 層、設於該第二介電層上之第二線路層、及設於該第二 介電層中且電性連接該第一與第二線路層之第二導電盲 孔，以令該增層結構之部分第二線路層表面外露於該開 孔中。 [0027] [0028] Ο [0029] 〇 [0030] 前述之製法中，於移除該核心板之後，該承載層及 該金屬層係作為散熱件。 前述之製法中，於移除該核心板之後，再移除該承 載層及該金屬層，以外露出該介電層之第二表面，且該 非作用面及其相鄰之部分侧面係凸出於該介電層之第二 表面。 前述之製法中，於該開孔中之增層結構之外露表面 上形成表面處理層，且形成該表面處理層之材料係選自 由電鍍鎳/金、化學鍍鎳/金、化鎳浸金（ENIG)、化鎳 I巴浸金（ENEPIG)、化學鍵錫〜（Immersion Tin)及有 機保焊劑（0SP)所組成之群組中之其中一者。 由上可知，本發明嵌埋半導體元件之封裝結構及其 製法，藉由半導體晶片設於該承載層上，可提升對位之 準確性。再者，藉由移除該核心板、及僅需於該第一介 電層之其中一表面上進行線路增層之製程，可降低整體 結構之厚度，以達到薄小化之目的。又，因無需進行貫 穿整體結構兩侧之導電通孔製程，故可降低成本，且使 製程簡易。另外，藉由該半導體晶片凸出於該介電層或 覆蓋金屬層，可提高半導體晶片之散熱性，有效避免該 099139081 表單編號A0101 第9頁/共24頁 0992068179-0 201220457 [0031] [0032] [0033] [0034] [0035] [0036] 半導體晶片過熱而損壞。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方式 ，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 請參閱第2A至2H圖，係為本發明嵌埋半導體元件之 封裝結構的製法之剖視示意圖。 如第2A圖所示，提供一具有相對之兩表面20a之核心 板20，且於該核心板20之兩表面20a上依序具有離形層 200及係為銅材之承載層21。 如第2B圖所示，於該承載層21上形成阻層22後，以 曝光顯影之方式形成開口區220，且該承載層21之部分表 面外露於該阻層22 ;接著，於該承載層21上電鍍形成亦 為銅材之金屬層23。 如第2C圖所示，移除該阻層22，以形成具有開口 230 之金屬層23，且令該承載層21之部分表面外露於該開口 230中，其中，該開口 230係定義為晶片承載區。 如第2D圖所示，於該開口 230中之承載層21上設置半 導體晶片24，該半導體晶片24具有相對之作用面24a及非 作用面24b，於該作用面24a上具有電極墊240，且該半 導體晶片24係以該非作用面24b結合至該開口 230中之承 載層21上。其中，藉由該阻層22之曝光顯影之方式，可 使半導體晶片24之位置準確度等同於曝光對位準確度， 以提高對位之準嫁性（成型偏移量約為+ / -1 0私m )相較 099139081 表單編號A0101 第10頁/共24頁 0992068179-0 201220457 於習知製法明顯提高許多。 [0037] 接著，於該金屬層23及該半導體晶片24上形成第一 介電層25，且該第一介電層25具有外露之第一表面25a及 結合至該金屬層23上之第二表面25b。 [0038] Ο [0039] 如第2E圖所示，於該第一介電層25之第一表面25a上 形成第一線路層26，且於該第一介電層25中形成複數電 性連通該第一線路層26與該電極墊240之第一導電盲孔 260。其中，該第一介電層25之厚度可依欲形成之第一導 電盲孔260之雷射鑽孔之孔徑作調整。 接著，於該第一介電層25之第一表面25a及該第一線 路層26上形成增層結構27，該增層結構27係具有至少一 第二介電層270、設於該第二介電層270上之第二線路層 271、及設於該第二介電層270中且電性連通該第一線路 層26與第二線路層271之第二導電盲孔272。 [0040] Ο [0041] 再於該增層結構27上形成絕緣保護層28，且於該絕 緣保護層28中形成複數開孔280，以令該增層結構27之部 分第二線路層271表面外露於該開孔280中。 又於該開孔280中之第二線路層271之外露表面上形 成表面處理層29，且形成該表面處理層29之材料係選自 由電鑛鎳/金、化學鑛錄/金、化鎮浸金（ENIG)、化錄 把浸金（ENEPIG)、化學鐘錫（Immersion Tin)及有 機保焊劑（0SP)所組成之群組中之其中一者。 如第2F圖所示，藉由該離形層200以移除該核心板20 ，而成為無核心板（coreless)之封裝結構，以降低整 099139081 表單編號A0101 第11頁/共24頁 0992068179-0 [0042] 201220457 [0043] [0044] [0045] [0046] [0047] 體封裝結構之厚度，有效達到薄小化之目的。 如第2G圖所示，移除該承載層21及該金屬層23，以 外露出該第一介電層25之第二表面25b，且該半導體晶片 24之非作用面24b及其相鄰之部分側面係凸出於該第一介 電層25之第二表面2 5b，以提高散熱性，俾能免除該半導 體晶片24過熱而損壞。 再者，電鍍該金屬層23之高度即為該半導體晶片24 凸出該第一介電層25之第二表面25b之高度，故可依需求 藉由該金屬層23之高度控制凸出之高度，使該半導體晶 片24嵌埋深度可自行控制，以便於該第一導電盲孔260之 雷射鑽孔之製程調整參數。 如第2H圖所示，於後續製程中，可於該增層結構27 之第二線路層271之外露表面上形成焊球30，以藉該些焊 球30接置於一印刷電路板31上。 本發明藉由該阻層22之曝光顯影之方式，可使半導 體晶片24之成型偏移量約為+/-10 ，相較於習知技術 中之成型偏移量為+ /-100 ，本發明之準確性明顯提高 〇 再者，本發明係為無核心板（coreless)之封裝結 構，且僅需於該第一介電層25之第一表面25a上進行線路 增層之製程，而不需於該第一介電層25之第二表面25b上 進行線路增層之製程，故相較於習知技術中之於核心板 兩侧進行線路增層之製程，本發明有效降低整體結構之 厚度。 099139081 表單編號A0101 第12頁/共24頁 0992068179-0 201220457 [0048] [0049] [0050] Ο [0051][〇〇〇2] With the evolution of semiconductor packaging technology, semiconductor devices have developed different package types, and the semiconductor devices are mainly used in a package sub_stratate device wafer, and the wafer is Electrically connected to the package substrate, and then encapsulated by a colloid; and to reduce the package height, the chip is embedded in a package substrate, and the package can reduce the volume of the overall semiconductor device and improve the electrical properties. Function, 遂 becomes a kind of package trend [〇〇〇3] 第 Refer to FIGS. 1A to 1E, which are schematic cross-sectional views of a package structure of a conventional embedded semiconductor device. [0006] [0006] As shown in FIG. 1A, 'first', a core board 10 having an opening (10) therethrough, has an inner layer line 1〇1 on the upper and lower sides of the core board 10, and A conductive via 102 is formed in the core board 10 to electrically connect the inner layer lines 1 and 1 on the upper and lower sides. As shown in FIG. 1B, a carrier board 14 having a dielectric material 120a is disposed on the bottom side of the core board 10 to accommodate a semiconductor wafer 11 having a plurality of electrodes 该 in the opening 100, and by an adhesive layer. The semiconductor wafer 11 is provided on the dielectric material 120a. As shown in FIG. 1C, the other dielectric material 120b is press-bonded on the upper side of the core board 1 and the semiconductor wafer 11 099139081, the form bat number A0101, page 4 / 24 pages 0992068179-0 201220457, so that the two dielectric materials are folded. 2〇a, 120b forms a dielectric layer 12, and the dielectric layer 12 is filled in a gap between the hole wall of the opening 1 and the semiconductor wafer 11 to fix the semiconductor wafer 丄j to the opening 100. in. Next, the carrier board 14 is removed. [0007] As shown in FIG. 1D, a wiring layer 13 is formed on the upper and lower dielectric layers 12, and the wiring layer 13 is disposed in the dielectric layer 12 and electrically connected to the electrode pad 110. The conductive via hole 13〇 of the inner layer line 〇1, and the upper circuit layer 13 has an electrical contact pad 130a, and the lower circuit layer 13 has a ball pad 130b» as shown in FIG. 1E. A solder resist layer 15 is formed on the dielectric layer 12 and the circuit layer 13 on the upper and lower sides, and an opening 150 ′ is formed in the solder resist layer 15 to expose the electrical contact pad 13〇a and the ball pad i3〇b » [0009] In the conventional technology, an opening 1〇〇 is formed in the core board 10 to press the dielectric layer 丨2 on both sides of the core board 1 to the semiconductor wafer 11, resulting in the semiconductor The wafer 11 is offset (as shown in FIG. 1C, the left and right pitches of the semiconductor wafer 11 and the opening walls of the opening pupil are respectively t, s, where t < s ) ' makes the semiconductor wafer! The molding offset of 1 is about + / _ 1 〇 〇 in m, so it is not easy to accurately position in the opening 1〇〇. Therefore, when the semiconductor wafer 11 is offset, the semiconductor wafer electrode pad 11 〇 does not easily correspond to the conductive blind hole 130 to achieve electrical connection, as shown in FIG. 1 , which is easy to generate electrical connection. Poor quality or failure, resulting in reduced product yield. Furthermore, the semiconductor wafer 11 is intended to be buried in the opening of the core board 10 without any heat conduction and heat dissipation structure, so that the semiconductor wafer 1丨099139081 Form No. A0101 Page 5 / Total 24 Page 0992068179-0 [0010 [0012] [0016] [0018] [0018] [0018] The heat dissipation is not easy, and the semiconductor crystal 11 is easily damaged due to overheating. Further, the thin semiconductor wafer 11 is required to be embedded in the thick core substrate 10, so that the thickness of the overall structure is greatly increased by the core plate 10, resulting in an increase in the thickness of the product, which makes it difficult to achieve a reduction in thickness. In addition, the line process needs to be performed on both sides of the core board 10. Therefore, the conductive via 102 is required to turn on the inner layer lines 101 and the circuit layer 13 on both sides, which not only causes an increase in cost, but also increases the manufacturing difficulty. Therefore, how to avoid all kinds of defects in the prior art has become a problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above-described deficiencies of the prior art, it is an object of the present invention to provide a package structure for embedding a semiconductor device in alignment and a method of fabricating the same. Still another object of the present invention is to provide a package structure of an embedded semiconductor device which improves heat dissipation and a method of fabricating the same. A further object of the present invention is to provide a package structure for a thinned embedded semiconductor component and a method of fabricating the same. Another object of the present invention is to provide a package structure for a buried semiconductor component with reduced cost and a method of fabricating the same. To achieve the above and other objects, the present invention discloses a package structure for embedding a semiconductor device, comprising: a first dielectric layer having opposite first and second surfaces; and a semiconductor wafer protrudingly embedded in the a second surface of the first dielectric layer, the semiconductor wafer has a relative active surface 099139081, a form number A0101, a sixth page, a total of 24 pages, 0992068179-0 201220457, and an inactive surface, and the first medium is located on the active surface An electrode pad in the electrical layer, wherein the non-active surface and an adjacent portion thereof protrude from the second surface of the first dielectric layer; the first circuit layer is disposed on the first dielectric layer Forming, in the first dielectric layer, a plurality of first conductive blind vias electrically connected to the first circuit layer and the electrode pad; and a build-up structure disposed on the first surface of the first dielectric layer And the first circuit layer; and the insulating protective layer is disposed on the layered structure, and a plurality of openings are formed in the insulating protective layer to expose a part of the surface of the layered structure to the opening. [0019] The foregoing package structure further includes a metal layer disposed on the second surface of the dielectric layer, and the metal layer has an opening so that the semiconductor wafer is located in the opening to make the metal layer serve as a heat dissipation Pieces. Further comprising a carrier layer disposed on the metal layer and the non-active surface of the semiconductor wafer, so that the carrier layer acts as a heat sink, and the material forming the carrier layer is a copper 〇 [0020] 〇 the foregoing package structure The build-up structure has at least one second dielectric layer, a second circuit layer disposed on the second dielectric layer, and is disposed in the second dielectric layer and electrically connected to the first and second layers a second conductive via hole of the circuit layer, and a portion of the surface of the second circuit layer of the buildup structure is exposed in the opening. [0021] The foregoing package structure further comprises a surface treatment layer disposed on the exposed surface of the buildup structure in the opening, and the material forming the surface treatment layer is selected from the group consisting of electroplated nickel/gold, electroless nickel/gold plating One of the groups consisting of ENIG, ENEPIG, Immersion Tin, and Organic Soldering Agent (0SP) 099139081 Form No. A0101 Page 7 / [0025] The present invention provides a method of fabricating a package structure for embedding a semiconductor device, comprising: providing a core plate having opposite surfaces, and The core plate has a bearing layer on both surfaces thereof; a metal layer having an opening is formed on the carrier layer to expose a part of the surface of the carrier layer in the opening; and a semiconductor wafer is disposed on the carrier layer in the opening, The semiconductor wafer has opposite active and non-active surfaces, and has an electrode pad on the active surface, and the semiconductor wafer is bonded to the carrier layer in the opening by the non-active surface; the metal layer and the semiconductor crystal Forming a first dielectric layer thereon, the first dielectric layer having an exposed first surface and a second surface bonded to the metal layer; forming a first circuit layer on the first surface of the first dielectric layer And forming a first conductive via hole electrically connected to the first circuit layer and the electrode pad in the first dielectric layer; forming on the first surface of the first dielectric layer and the first circuit layer a build-up structure; forming an insulating protective layer on the build-up structure, and forming a plurality of openings in the insulating protective layer to expose a part of the surface of the build-up structure in the opening; and removing the core plate, The carrier layer is exposed outside. In the above method, a separation layer is formed between the two surfaces of the core plate and the carrier layer to remove the core plate by the release layer. In the above method, the material forming the bearing layer is copper. In the above method, the process for forming the metal layer includes: forming a resist layer on the carrier layer, and forming an open region on the resist layer to expose a portion of the surface of the carrier layer to the open region; Forming the metal layer on the carrier layer of the open region; and removing the resist layer to form the opening. 099139081 Form No. A0101 Page 8 of 24 0992068179-0 201220457 [0026] In the foregoing method, the build-up structure has at least one second dielectric layer and a second line disposed on the second dielectric layer And a second conductive via hole disposed in the second dielectric layer and electrically connected to the first and second circuit layers, so that a portion of the surface of the second circuit layer of the buildup structure is exposed in the opening . [0028] In the foregoing method, after the core board is removed, the carrier layer and the metal layer serve as heat sinks. In the above method, after removing the core plate, the carrier layer and the metal layer are removed, and the second surface of the dielectric layer is exposed, and the non-active surface and the adjacent side portions thereof are protruded a second surface of the dielectric layer. In the above method, a surface treatment layer is formed on the exposed surface of the build-up structure in the opening, and the material forming the surface treatment layer is selected from the group consisting of electroplated nickel/gold, electroless nickel/gold, and nickel immersion gold ( ENIG), one of a group consisting of nickel immersion gold (ENEPIG), chemical bond tin (Immersion Tin) and organic solder resist (0SP). It can be seen from the above that the package structure of the embedded semiconductor device of the present invention and the method for manufacturing the same can be improved by the alignment of the semiconductor wafer on the carrier layer. Moreover, by removing the core board and performing the circuit build-up process only on one surface of the first dielectric layer, the thickness of the overall structure can be reduced to achieve the purpose of thinning. Moreover, since it is not necessary to perform a conductive via process on both sides of the entire structure, the cost can be reduced and the process can be simplified. In addition, by the semiconductor wafer protruding from the dielectric layer or the covering metal layer, the heat dissipation of the semiconductor wafer can be improved, and the 099139081 form number A0101 page 9/24 pages 0992068179-0 201220457 [0031] [0032] [0036] [0036] The semiconductor wafer is overheated and damaged. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand other advantages and functions of the present invention from the disclosure of the present disclosure. Referring to Figures 2A to 2H, there is shown a cross-sectional view showing a method of fabricating a package structure for embedding a semiconductor device of the present invention. As shown in Fig. 2A, a core plate 20 having opposite surfaces 20a is provided, and a release layer 200 and a copper-bearing carrier layer 21 are sequentially provided on both surfaces 20a of the core plate 20. As shown in FIG. 2B, after the resist layer 22 is formed on the carrier layer 21, the opening region 220 is formed by exposure and development, and a part of the surface of the carrier layer 21 is exposed to the resist layer 22; The metal layer 23 which is also a copper material is formed by plating on 21. As shown in FIG. 2C, the resist layer 22 is removed to form a metal layer 23 having an opening 230, and a portion of the surface of the carrier layer 21 is exposed in the opening 230, wherein the opening 230 is defined as a wafer carrier. Area. As shown in FIG. 2D, a semiconductor wafer 24 is disposed on the carrier layer 21 of the opening 230. The semiconductor wafer 24 has an opposite active surface 24a and an inactive surface 24b. The active surface 24a has an electrode pad 240 thereon. The semiconductor wafer 24 is bonded to the carrier layer 21 in the opening 230 with the non-active surface 24b. Wherein, the positional accuracy of the semiconductor wafer 24 can be equal to the exposure alignment accuracy by the exposure and development of the resist layer 22, so as to improve the alignment of the alignment (the molding offset is about +/-1). 0 private m) compared to 099139081 Form No. A0101 Page 10 / Total 24 pages 0992068179-0 201220457 The conventional method is significantly improved. [0037] Next, a first dielectric layer 25 is formed on the metal layer 23 and the semiconductor wafer 24, and the first dielectric layer 25 has an exposed first surface 25a and a second layer bonded to the metal layer 23. Surface 25b. [0039] As shown in FIG. 2E, a first circuit layer 26 is formed on the first surface 25a of the first dielectric layer 25, and a plurality of electrical connections are formed in the first dielectric layer 25. The first circuit layer 26 and the first conductive blind via 260 of the electrode pad 240. The thickness of the first dielectric layer 25 can be adjusted according to the aperture of the laser drilled hole of the first conductive blind via 260 to be formed. Then, a build-up structure 27 is formed on the first surface 25a of the first dielectric layer 25 and the first circuit layer 26, and the build-up structure 27 has at least one second dielectric layer 270 disposed on the second a second circuit layer 271 on the dielectric layer 270, and a second conductive via 272 disposed in the second dielectric layer 270 and electrically connected to the first circuit layer 26 and the second circuit layer 271. [0040] Further, an insulating protective layer 28 is formed on the build-up structure 27, and a plurality of openings 280 are formed in the insulating protective layer 28 to partially surface the second wiring layer 271 of the build-up structure 27. Exposed in the opening 280. Further, a surface treatment layer 29 is formed on the exposed surface of the second circuit layer 271 in the opening 280, and the material forming the surface treatment layer 29 is selected from the group consisting of electro-mineral nickel/gold, chemical minerals/gold, and chemical immersion. One of the group consisting of gold (ENIG), immersion gold (ENEPIG), chemical tin tin (Immersion Tin) and organic solder resist (0SP). As shown in FIG. 2F, the core layer 20 is removed by the release layer 200 to form a coreless package structure to reduce the whole 099139081 form number A0101 page 11 / page 24 0992068179- [0046] [0047] [0047] [0047] The thickness of the body package structure, effectively achieve the purpose of thinning. As shown in FIG. 2G, the carrier layer 21 and the metal layer 23 are removed, and the second surface 25b of the first dielectric layer 25 is exposed, and the non-active surface 24b of the semiconductor wafer 24 and its adjacent portion are exposed. The side surface protrudes from the second surface 25b of the first dielectric layer 25 to improve heat dissipation, and the semiconductor wafer 24 can be prevented from being overheated and damaged. Moreover, the height of the metal layer 23 is the height of the semiconductor wafer 24 protruding from the second surface 25b of the first dielectric layer 25. Therefore, the height of the metal layer 23 can be controlled according to the height of the metal layer 23. The embedded depth of the semiconductor wafer 24 can be controlled by itself to facilitate the process adjustment parameters of the laser drilling of the first conductive blind via 260. As shown in FIG. 2H, in a subsequent process, solder balls 30 may be formed on the exposed surface of the second circuit layer 271 of the build-up structure 27 to be attached to a printed circuit board 31 by the solder balls 30. . According to the method of exposure and development of the resist layer 22, the semiconductor wafer 24 can be formed with an offset of about +/-10, which is +/-100 compared with the prior art. The accuracy of the invention is significantly improved. Further, the present invention is a coreless package structure, and only the process of circuit build-up is performed on the first surface 25a of the first dielectric layer 25, without The process of circuit build-up is performed on the second surface 25b of the first dielectric layer 25. Therefore, the present invention effectively reduces the overall structure compared to the process of circuit build-up on both sides of the core board in the prior art. thickness. 099139081 Form No. A0101 Page 12 of 24 0992068179-0 201220457 [0049] [0050] [0051]
[0052] 又，因本發明無需進行如習知技術之導電通孔之製 程，不僅降低成本，且使製程簡易。 另外，該半導體晶片24凸出於該第一介電層25之第 二表面25b，以提高散熱性，俾能免除該半導體晶片24過 熱而損壞，有效克服習知技術之半導體晶片散熱不易之 問題。 於另一實施例申，如第2H’圖所示，於第2F圖之移 除該核心板20之製程後，係保留該承載層.21及該金屬層 23以作為散熱件，亦能提高散熱以避免該半導體晶片24 過熱而損壞。接著，於該第二線路層271之外露表面上形 成焊球30，再將該些焊球30接置於一印刷電路板31上。 本發明復提供一種嵌埋半導體元件之封裝結構，係 包括：具有相對之第一表面25a及第二表面25b之第一介 電層25、凸出嵌設於該第一介電層25之第二表面25b之半 導體晶片24、設於該第一介電層25之第一表面25a上之第 一線路層26、設於該第一介電層25之第一表面25a及該第 一線路層26上之增層結構27、以及設於該增層結構27上 之絕緣保護層28。 所述之半導體晶片24具有相對之作用面24a及非作用 面24b，且於該作用面24a上具有位於該第一介電層25中 之電極墊240，而該非作用面24b及其相鄰之部分侧面係 凸出於該第一介電層25之第二表面25b。 所述之第一線路層26於該第一介電層25中形成電性 連通該電極墊240之複數第一導電盲孔260。 099139081 表單編號A0101 第13頁/共24頁 0992068179-0 [0053] 201220457 [0054] [0055] [0056] [0057] 所述之增層結構27係具有至少一第二介電層270、設 於該第二介電層270上之第二線路層271、及設於該第二 介電層270中且電性連通該第一與第二線路層26, 271之 第二導電盲孔272。 所述之絕緣保護層28於其中形成複數開孔280，以令 該增層結構27之部分第二線路層271表面外露於該開孔 280中，而使焊球30係設於該第二線路層271之外露表面 上，以接置於一印刷電路板31上。 所述之封裝結構復包括金屬層23，係設於該第一介 電層25之第二表面25b上，且該金屬層23具有開口 230， 以令該半導體晶片2 4位於該開口 2 3 0中，以令該金屬層2 3 作為散熱件。該封裝結構又包括承載層21，係設於該金 屬層23及該半導體晶片24之非作用面24b上，以令該承載 層21亦作為散熱件。其中，形成該承載層21之材質係為 銅。 所述之封裝結構復包括表面處理層29，係設於該開 孔280中之增層結構27之第二線路層271之外露表面上， 且形成該表面處理層29之材料係選自由電鍍鎳/金、化學 鍍鎳/金、化鎳浸金（ENIG)、化鎳鈀浸金（ENEPIG) 、化學鍵錫（Immersion Tin)及有機保焊劑（OSP)所 組成之群組中之其中一者。 综上所述，本發明嵌埋半導體元件之封裝結構及其 製法藉由阻層曝光顯影之方式，可使半導體晶片之成型 偏移量優於習知技術中之成型偏移量，有效提升對位之 099139081 表單編號A0101 第14頁/共24頁 0992068179-0 [0058] 201220457 準確性。 [0059] 再者，藉由移除該核心板，以成為無核心板（core-less)之封裝結構，且因僅需於該第一介電層之其中一 表面上進行線路增層之製程，故大幅降低整體結構之厚 度，而達到薄小化之目的。 [0060] 又，藉由僅於該第一介電層之其中一表面上進行線 路增層之製程，故無需進行貫穿整體結構兩側之導電通 孔製程，因而有效降低成本，且使製程簡易。 [0061] 另外，藉由該半導體晶片凸出於該介電層及覆蓋金 屬層，因而提高半導體晶片之散熱性，有效避免該半導 體晶片過熱而損壞。 [0062] 上述實施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士均 可在不違背本發明之精神及範疇下，對上述實施例進行 修改。因此本發明之權利保護範圍，應如後述之申請專 利範圍所列。 【圖式簡單說明】 [0063] 第1A至1E圖係為習知嵌埋半導體元件之封裝結構之 製法的剖視示意圖；以及 [0064] 第2A至2H圖係為本發明嵌埋半導體元件之封裝結構 之製法的剖視示意圖；其中，第2H’圖係為第2H圖之另 一實施態樣。 【主要元件符號說明】 [0065] 10, 20 核心板 099139081 表單編號A0101 第15頁/共24頁 0992068179-0 201220457 [0066] 100,230 開口 [0067] 101 内層線路 [0068] 102 導電通孔 [0069] 11, 24 半導體晶片 [0070] 11a 黏著層 [0071] 110,240 電極墊 [0072] 12 介電層 [0073] 120a,120b 介電材 [0074] 13 線路層 [0075] 130 導電盲孔 [0076] 130a 電性接觸墊 [0077] 130b 植球墊 [0078] 14 承載板 [0079] 15 防焊層 [0080] 150,280 開孔 [0081] 20a 表面 [0082] 200 離形層 [0083] 21 承載層 [0084] 22 阻層 099139081 表單編號A0101 第16頁/共24頁 0992068179-0 201220457 Ο ❹ [0085] 220 開口區 [0086] 23 金屬層 [0087] 24a 作用面 [0088] 24b 非作用面 [0089] 25 第一介電層 [0090] 25a 第一表面 [0091] 25b 第二表面 [0092] 26 第一線路層 [0093] 260 ':應 第一導電盲孔 [0094] 27 增層結構 [0095] 270 第二介電層 [0096] 271 第二線路層：^ [0097] 272 第二導電盲 [0098] 28 絶緣保護層 [0099] 29 表面處理層 [0100] 30 焊球 [0101] 31 印刷電路板 [0102] t, s 間距 099139081 表單編號Α0101 第17頁/共24頁 0992068179-0Further, since the present invention does not require a process of conducting via holes as in the prior art, it not only reduces the cost but also makes the process simple. In addition, the semiconductor wafer 24 protrudes from the second surface 25b of the first dielectric layer 25 to improve heat dissipation, and the semiconductor wafer 24 can be prevented from being overheated and damaged, thereby effectively overcoming the problem of heat dissipation of the semiconductor wafer of the prior art. . In another embodiment, as shown in FIG. 2H′, after the process of removing the core board 20 in FIG. 2F, the carrier layer .21 and the metal layer 23 are retained as heat sinks, which can also be improved. The heat is dissipated to prevent the semiconductor wafer 24 from being overheated and damaged. Next, solder balls 30 are formed on the exposed surface of the second circuit layer 271, and the solder balls 30 are placed on a printed circuit board 31. The present invention further provides a package structure for embedding a semiconductor device, comprising: a first dielectric layer 25 having a first surface 25a and a second surface 25b opposite thereto, and a protrusion embedded in the first dielectric layer 25 a semiconductor wafer 24 having two surfaces 25b, a first wiring layer 26 disposed on the first surface 25a of the first dielectric layer 25, a first surface 25a disposed on the first dielectric layer 25, and the first wiring layer A build-up structure 27 on the 26, and an insulating protective layer 28 disposed on the build-up structure 27. The semiconductor wafer 24 has an opposite active surface 24a and an inactive surface 24b, and has an electrode pad 240 in the first dielectric layer 25 on the active surface 24a, and the non-active surface 24b and its adjacent A portion of the side surface protrudes from the second surface 25b of the first dielectric layer 25. The first circuit layer 26 forms a plurality of first conductive vias 260 electrically connected to the electrode pads 240 in the first dielectric layer 25. 099139081 Form No. A0101 Page 13 / Total 24 Page 0992068179-0 [0053] [0057] [0057] [0057] The build-up structure 27 has at least one second dielectric layer 270, a second circuit layer 271 on the second dielectric layer 270, and a second conductive via 272 disposed in the second dielectric layer 270 and electrically connected to the first and second circuit layers 26, 271. The insulating protective layer 28 defines a plurality of openings 280 therein to expose a portion of the surface of the second wiring layer 271 of the build-up structure 27 in the opening 280, and the solder ball 30 is disposed on the second line. The layer 271 is exposed on the exposed surface to be attached to a printed circuit board 31. The package structure further includes a metal layer 23 disposed on the second surface 25b of the first dielectric layer 25, and the metal layer 23 has an opening 230 for the semiconductor wafer 24 to be located in the opening 2300. In order to make the metal layer 2 3 as a heat sink. The package structure further includes a carrier layer 21 disposed on the metal layer 23 and the non-active surface 24b of the semiconductor wafer 24 such that the carrier layer 21 also functions as a heat sink. The material forming the carrier layer 21 is copper. The package structure includes a surface treatment layer 29 disposed on the exposed surface of the second circuit layer 271 of the build-up structure 27 in the opening 280, and the material forming the surface treatment layer 29 is selected from the group consisting of electroplated nickel. One of a group consisting of gold, electroless nickel/gold, nickel immersion gold (ENIG), nickel-palladium immersion gold (ENEPIG), chemical bond tin (Immersion Tin), and organic solder resist (OSP). In summary, the package structure of the embedded semiconductor device of the present invention and the method for manufacturing the same can be formed by the resistive layer exposure and development, so that the molding offset of the semiconductor wafer can be made better than the molding offset in the prior art, thereby effectively improving the Bit 099139081 Form No. A0101 Page 14 / Total 24 Page 0992068179-0 [0058] 201220457 Accuracy. [0059] Furthermore, the core board is removed to form a core-less package structure, and the circuit is added only on one surface of the first dielectric layer. Therefore, the thickness of the overall structure is greatly reduced, and the purpose of thinning is achieved. [0060] Moreover, by performing the process of circuit build-up only on one surface of the first dielectric layer, it is not necessary to perform a conductive via process through both sides of the integrated structure, thereby effectively reducing the cost and making the process simple. . In addition, since the semiconductor wafer protrudes from the dielectric layer and covers the metal layer, heat dissipation of the semiconductor wafer is improved, and the semiconductor wafer is effectively prevented from being overheated and damaged. The above-described embodiments are intended to illustrate the principles of the invention and its advantages, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the application patents which will be described later. BRIEF DESCRIPTION OF THE DRAWINGS [0063] FIGS. 1A to 1E are schematic cross-sectional views showing a method of fabricating a package structure of a conventional embedded semiconductor device; and [0064] FIGS. 2A to 2H are the embedded semiconductor device of the present invention. A schematic cross-sectional view of a method of fabricating a package structure; wherein the 2H' diagram is another embodiment of the 2H diagram. [Main component symbol description] [0065] 10, 20 Core board 099139081 Form number A0101 Page 15 / Total 24 page 0992068179-0 201220457 [0066] 100,230 Opening [0067] 101 Inner layer line [0068] 102 Conductive through hole [0069] 11, 24 semiconductor wafer [0070] 11a adhesive layer [0071] 110, 240 electrode pad [0072] 12 dielectric layer [0073] 120a, 120b dielectric material [0074] 13 circuit layer [0075] 130 conductive blind hole [0076] 130a Electrical contact pad [0077] 130b ball pad [0078] 14 carrier plate [0079] 15 solder mask [0080] 150, 280 opening [0081] 20a surface [0082] 200 release layer [0083] 21 carrier layer [0084 ] 22 Resistive layer 099139081 Form number A0101 Page 16 / Total 24 page 0992068179-0 201220457 Ο ❹ [0085] 220 Open area [0086] 23 Metal layer [0087] 24a Action surface [0088] 24b Non-active surface [0089] 25 First dielectric layer [0090] 25a first surface [0091] 25b second surface [0092] 26 first wiring layer [0093] 260 ': first conductive blind via [0094] 27 buildup structure [0095] 270 Second dielectric layer [0096] 271 Second circuit layer: ^ [0097] 272 Second conductive blind [0098] 28 The protective layer [0099] 29 surface treatment layer [0100] 30 solder balls [0101] The printed circuit board 31 [0102] t, s pitch Α0101 Form Number 099139081 Page 17/24 p 0992068179-0