TWI843015B - Slot connectivity test device and test method thereof - Google Patents
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- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 3
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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- 229910000679 solder Inorganic materials 0.000 description 1
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Abstract
Description
本發明涉及資訊安全的技術領域，特別是涉及一種插槽連通性測試裝置及其測試方法。 The present invention relates to the technical field of information security, and in particular to a slot connectivity testing device and a testing method thereof.
主機板廠商的主機板上會有很多外部設備互連匯流排插槽(PCIe Slot)，對於新生產的主機板來說，外部設備互連匯流排插槽在焊接時候可能會有虛焊，需要進行物理連接的連通性測試，測試外部設備互連匯流排插槽網路的連通性，來保證主機板生產品質。 Motherboard manufacturers have many PCIe slots on their motherboards. For newly produced motherboards, the PCIe slots may have weak solder joints during soldering. Physical connection connectivity tests are required to test the connectivity of the PCIe slot network to ensure motherboard production quality.
目前，在進行主機板網路連通性測試時，需要為主機板添加一些複雜的專用測試設備，例如網卡，GPU卡等插在外部設備互連匯流排插槽中進行測試驗證，由於專用測試設備價格較高，導致測試成本高，而且使用專用測試設備整個測試過程較複雜，耗時較長，測試效率低。 At present, when testing the network connectivity of the motherboard, it is necessary to add some complex dedicated test equipment to the motherboard, such as network cards, GPU cards, etc., which are inserted into the external device interconnect bus slot for testing and verification. Due to the high price of dedicated test equipment, the test cost is high, and the entire test process using dedicated test equipment is complex, time-consuming, and the test efficiency is low.
鑒於以上所述現有技術的缺點，本發明的目的在於提供一種插槽連通性測試裝置及其測試方法，用於解決現有技術中測試主機板上用於外部設備互連的匯流排插槽的連通性時測試成本高、測試效率低的問題。 In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a slot connectivity test device and a test method thereof, which are used to solve the problems of high test cost and low test efficiency when testing the connectivity of bus slots on a motherboard for interconnecting external devices in the prior art.
為實現上述目的及其他相關目的，本發明提供一種插槽連通性測試裝置，所述插槽連通性測試裝置包括一電路板、一重定時器晶片(也稱Retimer晶片)、一連接端以及一回傳模組；所述連接端裝設於所述電路板一側，係用於插接待測主機板的插槽；所述重定時器晶片裝設於所述電路板上，所述重定時器晶片的信號發送端子與信號接收端子分別與所述連接端電連接，所述信號接收端子接收待測主機板發送的輸出信號，所述信號發送端子經由所述重定時器晶片和所述連接端向待測主機板發送測試信號；所述回傳模組用於將所述信號接收端子接收的所述輸出信號回傳到所述重定時器晶片的信號發送端子，以使得所述信號發送端子經由所述重定時器晶片和所述連接端向待測主機板發送測試信號。 To achieve the above-mentioned purpose and other related purposes, the present invention provides a slot connectivity test device, the slot connectivity test device comprising a circuit board, a retimer chip (also called a Retimer chip), a connection terminal and a return module; the connection terminal is installed on one side of the circuit board and is used to be plugged into the slot of the motherboard to be tested; the retimer chip is installed on the circuit board, and the signal sending terminal and the signal receiving terminal of the retimer chip are respectively The signal receiving terminal is electrically connected to the connection end, the signal sending terminal receives the output signal sent by the motherboard to be tested, and the signal sending terminal sends the test signal to the motherboard to be tested via the retimer chip and the connection end; the feedback module is used to feedback the output signal received by the signal receiving terminal to the signal sending terminal of the retimer chip, so that the signal sending terminal sends the test signal to the motherboard to be tested via the retimer chip and the connection end.
於本發明一實施例中，所述連接端為金手指組件。 In one embodiment of the present invention, the connection end is a gold finger assembly.
於本發明一實施例中，所述金手指組件包含的金手指個數與所述待測主機板的插槽的端子個數匹配。 In one embodiment of the present invention, the number of gold fingers included in the gold finger assembly matches the number of terminals of the slot of the motherboard to be tested.
於本發明一實施例中，所述回傳模組為裝設於所述電路板上，並分別與所述重定時器晶片的信號接收端子和所述信號發送端子相連的回傳電路。 In one embodiment of the present invention, the feedback module is a feedback circuit installed on the circuit board and connected to the signal receiving terminal and the signal sending terminal of the retimer chip respectively.
於本發明一實施例中，所述回傳模組包括與所述電路板相連的控制板和裝設於所述控制板上的分別與所述重定時器晶片的信號接收端子和所述信號發送端子相連的回傳電路。 In one embodiment of the present invention, the feedback module includes a control board connected to the circuit board and a feedback circuit installed on the control board and connected to the signal receiving terminal and the signal sending terminal of the retimer chip respectively.
於本發明一實施例中，所述回傳電路包括一端與所述重定時器晶片的信號接收端子相連，另一端與所述重定時器晶片的信號發送端子相連的回傳電阻模組。 In one embodiment of the present invention, the feedback circuit includes a feedback resistor module having one end connected to the signal receiving terminal of the retimer chip and the other end connected to the signal sending terminal of the retimer chip.
於本發明一實施例中，所述回傳模組位於所述重定時器晶片內並通過所述重定時器晶片內的串列器/解串器將所述信號接收端子接收的所述輸出信號回傳到所述重定時器晶片的信號發送端子。 In one embodiment of the present invention, the feedback module is located in the retimer chip and transmits the output signal received by the signal receiving terminal back to the signal sending terminal of the retimer chip through the serializer/deserializer in the retimer chip.
為實現上述目的及其他相關目的，本發明還提供一種插槽連通性測試方法，所述插槽連通性測試方法應用於插槽連通性測試裝置；所述插槽連通性測試裝置包括一電路板、一重定時器晶片、一連接端以及一回傳模組，所述重定時器晶片具有信號接收端子和信號發送端子；所述插槽連通性測試方法包括以下步驟：在所述連接端插接待測主機板的插槽時，通過重定時器晶片的信號接收端子從待測主機板接收輸出信號；基於所述回傳模組將所述信號接收端子接收的所述輸出信號回傳到所述重定時器晶片的信號發送端子；所述信號發送端子經由所述重定時器晶片和所述連接端向待測主機板發送測試信號。 To achieve the above-mentioned purpose and other related purposes, the present invention also provides a slot connectivity test method, which is applied to a slot connectivity test device; the slot connectivity test device includes a circuit board, a retimer chip, a connection end and a return module, and the retimer chip has a signal receiving terminal and a signal sending terminal; the slot connectivity test method includes the following steps: when the connection end is inserted into the slot of the motherboard to be tested, the output signal is received from the motherboard to be tested through the signal receiving terminal of the retimer chip; based on the return module, the output signal received by the signal receiving terminal is returned to the signal sending terminal of the retimer chip; the signal sending terminal sends a test signal to the motherboard to be tested via the retimer chip and the connection end.
於本發明一實施例中，所述連接端為金手指組件。 In one embodiment of the present invention, the connection end is a gold finger assembly.
於本發明一實施例中，所述金手指組件包含的金手指個數與所述待測主機板的插槽的端子個數匹配。 In one embodiment of the present invention, the number of gold fingers included in the gold finger assembly matches the number of terminals of the slot of the motherboard to be tested.
於本發明一實施例中，所述回傳模組為裝設於所述電路板上，並分別與所述重定時器晶片的信號接收端子和所述信號發送端子相連的回傳電路。 In one embodiment of the present invention, the feedback module is a feedback circuit installed on the circuit board and connected to the signal receiving terminal and the signal sending terminal of the retimer chip respectively.
於本發明一實施例中，所述回傳模組包括與所述電路板相連的控制板和裝設於所述控制板上的分別與所述重定時器晶片的信號接收端子和所述信號發送端子相連的回傳電路。 In one embodiment of the present invention, the feedback module includes a control board connected to the circuit board and a feedback circuit installed on the control board and connected to the signal receiving terminal and the signal sending terminal of the retimer chip respectively.
於本發明一實施例中，所述回傳電路包括一端與所述重定時器晶片的信號接收端子相連，另一端與所述重定時器晶片的信號發送端子相連的回傳電阻模組。 In one embodiment of the present invention, the feedback circuit includes a feedback resistor module having one end connected to the signal receiving terminal of the retimer chip and the other end connected to the signal sending terminal of the retimer chip.
於本發明一實施例中，所述回傳模組位於所述重定時器晶片內並通過所述重定時器晶片內的串列器/解串器將所述信號接收端子接收的所述輸出信號回傳到所述重定時器晶片的信號發送端子。 In one embodiment of the present invention, the feedback module is located in the retimer chip and transmits the output signal received by the signal receiving terminal back to the signal sending terminal of the retimer chip through the serializer/deserializer in the retimer chip.
如上所示，本發明的一種插槽連通性測試裝置及其測試方法通過將成本低廉的重定時器晶片的信號接收端子接收的信號通過外部鏈路或晶片內部，回傳到重定時器晶片的信號發送端子，不需要專用的測試設備就能實現對主機板上插槽的連通性測試，大大降低了主機板的生產測試成本。 As shown above, the slot connectivity test device and test method of the present invention transmits the signal received by the signal receiving terminal of the low-cost retimer chip back to the signal sending terminal of the retimer chip through an external link or inside the chip, and can realize the connectivity test of the slot on the motherboard without the need for dedicated test equipment, greatly reducing the production test cost of the motherboard.
100:插槽連通性測試裝置 100: Slot connectivity test device
110:電路板 110: Circuit board
120:連接端 120:Connection terminal
130:重定時器(Retimer)晶片 130: Retimer chip
140:回傳模組 140: Feedback module
141:控制板 141: Control panel
142:回傳電路 142: Feedback circuit
200:主機板 200: Motherboard
210:待測主機板的插槽 210: Slot of the motherboard to be tested
220:中央處理器 220: Central Processing Unit
S100~S300:步驟 S100~S300: Steps
圖1顯示為本發明的插槽連通性測試裝置通過外部鏈路進行回傳時的一種結構示意圖；圖2顯示為本發明的插槽連通性測試裝置通過外部鏈路進行回傳時的另一種結構示意圖；圖3顯示為本發明的插槽連通性測試裝置通過內部鏈路進行回傳時的一種結構示意圖；圖4顯示為本發明的插槽連通性測試裝置應用於主機板的插槽測試時的應用示意圖；圖5顯示為本發明的插槽連通性測試方法於一實施例中的流程圖。 FIG1 shows a structural schematic diagram of the slot connectivity test device of the present invention when it is transmitted back through an external link; FIG2 shows another structural schematic diagram of the slot connectivity test device of the present invention when it is transmitted back through an external link; FIG3 shows a structural schematic diagram of the slot connectivity test device of the present invention when it is transmitted back through an internal link; FIG4 shows an application schematic diagram of the slot connectivity test device of the present invention when it is applied to the slot test of a motherboard; FIG5 shows a flow chart of the slot connectivity test method of the present invention in an embodiment.
以下通過特定的具體實例說明本發明的實施方式，本領域技術人員可由本說明書所揭露的內容輕易地瞭解本發明的其他優點與功效。本發明還可以通過另外不同的具體實施方式加以實施或應用，本說明書中的各項細節也可以基於不同觀點與應用，在沒有背離本發明的精神下進行各種修飾或改變。需說明的是，在不衝突的情況下，以下實施例及實施例中的特徵可以相互組合。 The following is an explanation of the implementation of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations. The details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.
需要說明的是，以下實施例中所提供的圖示僅以示意方式說明本發明的基本構想，遂圖式中僅顯示與本發明中有關的組件而非按照實際實施時的元件數目、形狀及尺寸繪製，其實際實施時各元件的型態、數量及比例可為一種隨意的改變，且其元件佈局型態也可能更為複雜。 It should be noted that the diagrams provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and the diagrams only show the components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. The type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may also be more complicated.
本實施例的目的在於提供一種插槽連通性測試裝置100及其測試方法，用於解決現有技術中測試主機板上用於外部設備互連的匯流排插槽的連通性時測試成本高、測試效率低的問題。 The purpose of this embodiment is to provide a slot connectivity test device 100 and a test method thereof, which are used to solve the problems of high test cost and low test efficiency when testing the connectivity of bus slots on a motherboard for interconnecting external devices in the prior art.
以下將詳細闡述本實施例的插槽連通性測試裝置100及其測試方法的原理及實施方式，使本領域技術人員不需要創造性勞動即可理解本發明的插槽連通性測試裝置100及其測試方法。 The following will explain in detail the principle and implementation of the slot connectivity test device 100 and its testing method of this embodiment, so that technical personnel in this field can understand the slot connectivity test device 100 and its testing method of the present invention without creative labor.
實施例1 Implementation Example 1
如圖1所示，本實施例提供一種插槽連通性測試裝置100，所述插槽連通性測試裝置100包括電路板110，重定時器晶片130，連接端120以及回傳模組140。 As shown in FIG. 1 , the present embodiment provides a slot connectivity test device 100, wherein the slot connectivity test device 100 includes a circuit board 110, a retimer chip 130, a connection terminal 120, and a feedback module 140.
於本實施例中，所述連接端120裝設於所述電路板110一側，用於插接待測主機板的插槽210。 In this embodiment, the connection end 120 is installed on one side of the circuit board 110 and is used to be plugged into the slot 210 of the motherboard to be tested.
具體地，於本實施例中，所述連接端120為金手指組件。 Specifically, in this embodiment, the connection end 120 is a gold finger assembly.
其中，所述金手指組件包含的金手指個數與所述待測主機板的插槽210的端子個數匹配，即根據所述待測主機板的插槽210的導電端子的數量確定所述插槽連通性測試裝置100中連接端120的金手指個數。 The number of gold fingers included in the gold finger assembly matches the number of terminals of the slot 210 of the motherboard to be tested, that is, the number of gold fingers of the connection end 120 in the slot connectivity test device 100 is determined according to the number of conductive terminals of the slot 210 of the motherboard to be tested.
於本實施例中，所述待測主機板的插槽210優選但不限於PCIe插槽。 In this embodiment, the slot 210 of the motherboard to be tested is preferably but not limited to a PCIe slot.
根據待測主機板的插槽210的輸出信號定義所述金手指組件的各個金手指。例如，所述待測主機板通過插槽輸出的輸出信號包括PCIe信號和時鐘重定信號以及I2C信號，對應的金手指組件定義對應的金手指從所述待測主機板的插槽210接收PCIe信號和時鐘重定信號以及I2C信號。 The gold fingers of the gold finger assembly are defined according to the output signal of the slot 210 of the motherboard to be tested. For example, the output signal output by the motherboard to be tested through the slot includes a PCIe signal, a clock reset signal, and an I2C signal, and the corresponding gold finger assembly defines that the corresponding gold finger receives the PCIe signal, the clock reset signal, and the I2C signal from the slot 210 of the motherboard to be tested.
於本實施例中，所述重定時器晶片130裝設於所述電路板110上，所述重定時器晶片130的信號發送端子與信號接收端子分別與所述連接端120電連接，所述信號接收端子接收待測主機板發送的輸出信號，所述信號發送端子經由所述重定時器晶片和所述連接端向待測主機板發送測試信號。 In this embodiment, the retimer chip 130 is mounted on the circuit board 110, and the signal sending terminal and the signal receiving terminal of the retimer chip 130 are electrically connected to the connecting terminal 120 respectively. The signal receiving terminal receives the output signal sent by the motherboard to be tested, and the signal sending terminal sends the test signal to the motherboard to be tested via the retimer chip and the connecting terminal.
其中，重定時器晶片130採用信號調理技術來提升信號完整性，增加高速信號的有效傳輸距離。重定時器晶片130採用業界主流封裝，其功耗、傳輸時延等關鍵性能指標領先其它測試晶片，並且重定時器晶片130支援SRIS(具有獨立擴展頻譜時鐘架構的分離式參考時鐘)和重定時器級聯等應用。所述重定時器晶片130可與PCIe插槽通信，例如，所述重定時器晶片130符合PCIe 4.0規範、PCIe 5.0規範、或符合未來PCIe標準規範。相比現有技術中的專用測試設備網卡，GPU卡等，所述重定時器晶片130具有價格低廉的優勢。所以通過本 實施例的重定時器晶片130對待測主機板的插槽210進行連通性測試，可以大大降低主機板的生產測試成本。 Among them, the retimer chip 130 adopts signal conditioning technology to improve signal integrity and increase the effective transmission distance of high-speed signals. The retimer chip 130 adopts the mainstream packaging in the industry, and its key performance indicators such as power consumption and transmission delay are ahead of other test chips, and the retimer chip 130 supports SRIS (separate reference clock with independent extended spectrum clock architecture) and retimer cascading and other applications. The retimer chip 130 can communicate with the PCIe slot. For example, the retimer chip 130 complies with the PCIe 4.0 specification, the PCIe 5.0 specification, or complies with the future PCIe standard specification. Compared with the dedicated test equipment network card, GPU card, etc. in the prior art, the retimer chip 130 has the advantage of low price. Therefore, by using the retimer chip 130 of this embodiment to test the connectivity of the slot 210 of the motherboard to be tested, the production test cost of the motherboard can be greatly reduced.
在所述金手指組件插接到待測主機板的插槽210中時，從所述待測主機板的插槽210接收PCIe信號和時鐘重定信號以及I2C信號等輸出信號，然後傳入重定時器晶片130中。所述重定時器晶片130的信號接收端子接收待測主機板發送的輸出信號，並經所述回傳模組140之後，所述重定時器晶片130的信號發送端子向待測主機板發送測試信號。在所述待測主機板的中央處理器CPU)檢測到所述重定時器晶片130發送的測試信號時，即實現了測試主機板的插槽的連通性。 When the gold finger assembly is plugged into the slot 210 of the motherboard to be tested, the PCIe signal, clock reset signal, I2C signal and other output signals are received from the slot 210 of the motherboard to be tested, and then transmitted to the retimer chip 130. The signal receiving terminal of the retimer chip 130 receives the output signal sent by the motherboard to be tested, and after passing through the feedback module 140, the signal sending terminal of the retimer chip 130 sends a test signal to the motherboard to be tested. When the central processing unit (CPU) of the motherboard to be tested detects the test signal sent by the retimer chip 130, the connectivity of the slot of the test motherboard is realized.
於本實施例中，所述回傳模組140用於將所述信號接收端子接收的所述輸出信號回傳到所述重定時器晶片的信號發送端子，以使得所述信號發送端子經由重定時器晶片130和連接端120向待測主機板發送測試信號。 In this embodiment, the feedback module 140 is used to feedback the output signal received by the signal receiving terminal to the signal sending terminal of the retimer chip, so that the signal sending terminal sends a test signal to the motherboard under test via the retimer chip 130 and the connection terminal 120.
於本實施例中，優選地，所述回傳模組140通過外部鏈路環回所述重定時器晶片130的信號。 In this embodiment, preferably, the feedback module 140 loops back the signal of the retimer chip 130 through an external link.
圖1顯示為回傳模組140通過外部鏈路環回所述重定時器晶片130的信號的一種結構示意圖。具體地，於本實施例中，如圖1所示，所述回傳模組140設置在所述電路板110外部，包括與所述電路板110相連的控制板141和裝設於所述控制板141上的分別與所述重定時器晶片130的信號接收端子和所述信號發送端子相連的回傳電路142。所述控制板141用於承載所述回傳電路142，控制實現所述回傳電路142與所述電路板110的信號連接。 FIG1 shows a schematic diagram of a structure in which a feedback module 140 loops back the signal of the retimer chip 130 through an external link. Specifically, in this embodiment, as shown in FIG1 , the feedback module 140 is arranged outside the circuit board 110, and includes a control board 141 connected to the circuit board 110 and a feedback circuit 142 installed on the control board 141 and connected to the signal receiving terminal and the signal sending terminal of the retimer chip 130 respectively. The control board 141 is used to carry the feedback circuit 142 and control the signal connection between the feedback circuit 142 and the circuit board 110.
即所述回傳模組140通過位於所述重定時器晶片130的外部，獨立於所述重定時器晶片130的控制板141和回傳電路142將所述信號接收端子接收 的所述輸出信號回傳到所述重定時器晶片的信號發送端子，以使得所述信號發送端子經由所述重定時器晶片和所述連接端向待測主機板發送測試信號。在所述待測主機板的中央處理器220(CPU)檢測到所述重定時器晶片130發送的測試信號時，即實現了測試主機板的插槽的連通性。 That is, the feedback module 140 transmits the output signal received by the signal receiving terminal back to the signal sending terminal of the retimer chip through the control board 141 and feedback circuit 142 located outside the retimer chip 130 and independent of the retimer chip 130, so that the signal sending terminal sends a test signal to the motherboard under test through the retimer chip and the connection terminal. When the central processing unit 220 (CPU) of the motherboard under test detects the test signal sent by the retimer chip 130, the connectivity of the slot of the test motherboard is realized.
其中，於本實施例中，所述回傳電路例如包括回傳電阻模組，所述回傳電阻模組的一端與所述重定時器晶片130的信號接收端子相連，另一端與所述重定時器晶片130的信號發送端子相連。其中，所述回傳電阻模組包括一個或多個電阻。 In this embodiment, the feedback circuit includes, for example, a feedback resistor module, one end of which is connected to the signal receiving terminal of the retimer chip 130, and the other end of which is connected to the signal sending terminal of the retimer chip 130. The feedback resistor module includes one or more resistors.
圖2顯示為回傳模組140通過外部鏈路環回所述重定時器晶片130的信號的另一種結構示意圖。如圖2所示，於本實施例中，所述回傳模組140裝設於所述電路板110上，所述回傳模組140包括裝設於所述電路板110上的回傳電路，所述回傳電路分別與所述重定時器晶片130的信號接收端子和所述信號發送端子相連，所述回傳電路通過所述電路板110實現與所述重定時器晶片130的信號連接。 FIG2 shows another structural schematic diagram of the feedback module 140 looping back the signal of the retimer chip 130 through an external link. As shown in FIG2, in this embodiment, the feedback module 140 is installed on the circuit board 110, and the feedback module 140 includes a feedback circuit installed on the circuit board 110, and the feedback circuit is respectively connected to the signal receiving terminal and the signal sending terminal of the retimer chip 130, and the feedback circuit realizes the signal connection with the retimer chip 130 through the circuit board 110.
其中，於本實施例中，所述回傳電路例如包括回傳電阻模組，所述回傳電阻模組的一端與所述重定時器晶片130的信號接收端子相連，另一端與所述重定時器晶片130的信號發送端子相連。其中，所述回傳電阻模組包括一個或多個電阻。 In this embodiment, the feedback circuit includes, for example, a feedback resistor module, one end of which is connected to the signal receiving terminal of the retimer chip 130, and the other end of which is connected to the signal sending terminal of the retimer chip 130. The feedback resistor module includes one or more resistors.
即本實施例中，所述回傳模組140與所述重定時器晶片130集成於一個電路板110上，所述回傳模組140位於所述重定時器晶片130的外部，獨立於所述重定時器晶片130，所述回傳模組140將所述信號接收端子接收的所述輸出信號回傳到所述重定時器晶片的信號發送端子，以使得所述信號發送端子經由 重定時器晶片130和連接端120向待測主機板發送測試信號。在所述待測主機板的中央處理器(CPU)檢測到所述重定時器晶片130發送的測試信號時，即實現了測試主機板的插槽的連通性。 That is, in this embodiment, the feedback module 140 and the retimer chip 130 are integrated on a circuit board 110, the feedback module 140 is located outside the retimer chip 130 and is independent of the retimer chip 130, and the feedback module 140 feeds the output signal received by the signal receiving terminal back to the signal sending terminal of the retimer chip, so that the signal sending terminal sends a test signal to the motherboard under test via the retimer chip 130 and the connection terminal 120. When the central processing unit (CPU) of the motherboard under test detects the test signal sent by the retimer chip 130, the connectivity of the slot of the test motherboard is realized.
此外，所述回傳模組140也可以通過所述重定時器晶片130的內部鏈路環回所述重定時器晶片130的信號。 In addition, the feedback module 140 can also loop back the signal of the retimer chip 130 through the internal link of the retimer chip 130.
圖3顯示為回傳模組140通過所述重定時器晶片130內部鏈路環回所述重定時器晶片130的信號的一種結構示意圖。如圖3所示，所述回傳模組140位於所述重定時器晶片130內並通過所述重定時器晶片130內的串列器/解串器SERDES(SERializer/DESerializer)將所述信號接收端子接收的所述輸出信號回傳到所述重定時器晶片的信號發送端子。 FIG3 shows a schematic diagram of a structure in which the feedback module 140 loops back the signal of the retimer chip 130 through the internal link of the retimer chip 130. As shown in FIG3, the feedback module 140 is located in the retimer chip 130 and transmits the output signal received by the signal receiving terminal back to the signal sending terminal of the retimer chip through the serializer/deserializer SERDES (SERializer/DESerializer) in the retimer chip 130.
其中，SERDES在發送端多路低速並行信號被轉換成高速串列信號，經過傳輸媒體(光纜或銅線)，最後在接收端將高速串列信號重新轉換成低速並行信號。 Among them, SERDES converts multiple low-speed parallel signals into high-speed serial signals at the transmitting end, passes through the transmission medium (optical cable or copper wire), and finally converts the high-speed serial signals back into low-speed parallel signals at the receiving end.
所述重定時器晶片130內部具有串列器/解串器，本實施例的回傳模組140在重定時器晶片內部利用串列器/解串器可以將信號轉換的功能將所述重定時器晶片130信號接收端子接收的所述輸出信號經重定時器晶片內部的串列器/解串器處理後，回傳到所述重定時器晶片的信號發送端子，以使得所述信號發送端子經由連接端120向待測主機板發送測試信號。在所述待測主機板的中央處理器220(CPU)檢測到所述重定時器晶片130發送的測試信號時，即實現了測試主機板的插槽的連通性。 The retimer chip 130 has a serializer/deserializer inside. The return module 140 of this embodiment uses the signal conversion function of the serializer/deserializer inside the retimer chip to process the output signal received by the signal receiving terminal of the retimer chip 130 through the serializer/deserializer inside the retimer chip, and then returns it to the signal sending terminal of the retimer chip, so that the signal sending terminal sends a test signal to the motherboard under test through the connection terminal 120. When the central processing unit 220 (CPU) of the motherboard under test detects the test signal sent by the retimer chip 130, the connectivity of the slot of the test motherboard is realized.
為使本領域技術人員進一步理解本實施例的插槽連通性測試裝置100，以下對本實施例的插槽連通性測試裝置100的使用過程進行說明。 In order to enable technical personnel in this field to further understand the slot connectivity test device 100 of this embodiment, the following describes the use process of the slot connectivity test device 100 of this embodiment.
如圖4所示，主機板200具有多個插槽：插槽1……插槽N；本實施例的插槽連通性測試裝置100每次測試一個插槽的連通性，若多個插槽同時測試，可以在每一個插槽中插接一個本實施例的插槽連通性測試裝置100。 As shown in FIG. 4 , the motherboard 200 has multiple slots: slot 1 ... slot N; the slot connectivity test device 100 of this embodiment tests the connectivity of one slot at a time. If multiple slots are tested at the same time, a slot connectivity test device 100 of this embodiment can be inserted into each slot.
在插槽連通性測試裝置100的金手指組件插接到插槽中時，所述金手指組件從所述主機板200的插槽接收PCIe信號和時鐘重定信號以及I2C信號等輸出信號，然後傳入插槽連通性測試裝置100的重定時器晶片。所述重定時器晶片的信號接收端子接收主機板200發送的輸出信號，並經所述回傳模組之後，所述重定時器晶片的信號發送端子向主機板200發送測試信號。在所述主機板200的中央處理器220(CPU)檢測到所述重定時器晶片發送的測試信號時，即實現了測試主機板200的插槽的連通性。 When the gold finger assembly of the slot connectivity test device 100 is inserted into the slot, the gold finger assembly receives output signals such as PCIe signals, clock reset signals, and I2C signals from the slot of the motherboard 200, and then transmits them to the retimer chip of the slot connectivity test device 100. The signal receiving terminal of the retimer chip receives the output signal sent by the motherboard 200, and after passing through the feedback module, the signal sending terminal of the retimer chip sends a test signal to the motherboard 200. When the central processing unit 220 (CPU) of the motherboard 200 detects the test signal sent by the retimer chip, the connectivity of the slot of the motherboard 200 is tested.
所以本實施例的插槽連通性測試裝置100利用成本低廉的重定時器晶片，將重定時器晶片的信號接收端子接收的信號通過外部鏈路或晶片內部，回傳到重定時器晶片的信號發送端子，實現對主機板200上插槽的連通性測試，有效降低了主機板200的生產測試成本。 Therefore, the slot connectivity test device 100 of this embodiment uses a low-cost retimer chip to transmit the signal received by the signal receiving terminal of the retimer chip back to the signal sending terminal of the retimer chip through an external link or inside the chip, thereby realizing the connectivity test of the slot on the motherboard 200, effectively reducing the production test cost of the motherboard 200.
實施例2 Example 2
本實施例提供一種插槽連通性測試方法，所述插槽連通性測試方法應用於本申請的插槽連通性測試裝置；所述插槽連通性測試裝置包括電路板，重定時器晶片，連接端以及回傳模組，所述重定時器晶片具有信號接收端子和信號發送端子；如圖5所示，所述插槽連通性測試方法包括以下步驟：步驟S100，在所述連接端插接待測主機板的插槽時，通過重定時器晶片的信號接收端子從待測主機板接收輸出信號； 步驟S200，基於所述回傳模組將所述信號接收端子接收的所述輸出信號回傳到所述重定時器晶片的信號發送端子；步驟S300，所述信號發送端子經由所述重定時器晶片和所述連接端向待測主機板發送測試信號。 This embodiment provides a slot connectivity test method, which is applied to the slot connectivity test device of the present application; the slot connectivity test device includes a circuit board, a retimer chip, a connection end and a return module, and the retimer chip has a signal receiving terminal and a signal sending terminal; as shown in FIG5 , the slot connectivity test method includes the following steps: Step S100, when the connection end is inserted into the slot of the motherboard to be tested, the output signal is received from the motherboard to be tested through the signal receiving terminal of the retimer chip; Step S200, based on the return module, the output signal received by the signal receiving terminal is returned to the signal sending terminal of the retimer chip; Step S300, the signal sending terminal sends a test signal to the motherboard to be tested via the retimer chip and the connection end.
於本實施例中，所述連接端為金手指組件。 In this embodiment, the connection end is a gold finger assembly.
其中，所述金手指組件包含的金手指個數與所述待測主機板的插槽的端子個數匹配，即根據所述待測主機板的插槽的導電端子的數量確定所述插槽連通性測試裝置中連接端的金手指個數。 The number of gold fingers included in the gold finger assembly matches the number of terminals of the slot of the motherboard to be tested, that is, the number of gold fingers of the connection end in the slot connectivity test device is determined according to the number of conductive terminals of the slot of the motherboard to be tested.
根據待測主機板的插槽的輸出信號定義所述金手指組件的各個金手指。例如，所述待測主機板通過插槽輸出的輸出信號包括PCIe信號和時鐘重定信號以及I2C信號，對應的金手指組件定義對應的金手指從所述待測主機板的插槽接收PCIe信號和時鐘重定信號以及I2C信號。 The gold fingers of the gold finger assembly are defined according to the output signal of the slot of the motherboard to be tested. For example, the output signal output by the motherboard to be tested through the slot includes a PCIe signal, a clock reset signal, and an I2C signal, and the corresponding gold finger assembly defines that the corresponding gold finger receives the PCIe signal, the clock reset signal, and the I2C signal from the slot of the motherboard to be tested.
於本實施例中，所述回傳模組為裝設於所述電路板上，並分別與所述重定時器晶片的信號接收端子和所述信號發送端子相連的回傳電路。 In this embodiment, the feedback module is a feedback circuit installed on the circuit board and connected to the signal receiving terminal and the signal sending terminal of the retimer chip respectively.
於本實施例中，所述回傳模組包括與所述電路板相連的控制板和裝設於所述控制板上的分別與所述重定時器晶片的信號接收端子和所述信號發送端子相連的回傳電路。 In this embodiment, the feedback module includes a control board connected to the circuit board and a feedback circuit installed on the control board and connected to the signal receiving terminal and the signal sending terminal of the retimer chip respectively.
於本實施例中，所述回傳電路包括一端與所述重定時器晶片的信號接收端子相連，另一端與所述重定時器晶片的信號發送端子相連的回傳電阻模組。 In this embodiment, the feedback circuit includes a feedback resistor module having one end connected to the signal receiving terminal of the retimer chip and the other end connected to the signal sending terminal of the retimer chip.
於本實施例中，所述回傳模組位於所述重定時器晶片內並通過所述重定時器晶片內的串列器/解串器將所述信號接收端子接收的所述輸出信號回傳到所述重定時器晶片的信號發送端子。 In this embodiment, the feedback module is located in the retimer chip and transmits the output signal received by the signal receiving terminal back to the signal sending terminal of the retimer chip through the serializer/deserializer in the retimer chip.
其中，本實施例中回傳模組的結構和功能與實施例1中回傳模組140的結構和功能相同，所述重定時器晶片的結構和功能與實施例1中重定時器晶片130的結構和功能相同，實施例間相同的部分不再贅述。 Among them, the structure and function of the feedback module in this embodiment are the same as the structure and function of the feedback module 140 in embodiment 1, and the structure and function of the retimer chip are the same as the structure and function of the retimer chip 130 in embodiment 1. The same parts between the embodiments will not be repeated.
綜上所述，本發明的一種插槽連通性測試裝置及其測試方法通過將成本低廉的重定時器晶片的信號接收端子接收的信號通過外部鏈路或晶片內部，回傳到重定時器晶片的信號發送端子的方式，不需要專用的測試設備就能實現對主機板上插槽的連通性測試，大大降低了主機板的生產測試成本。所以，本發明有效克服了現有技術中的種種缺點而具高度產業利用價值。 In summary, the slot connectivity test device and test method of the present invention can realize the connectivity test of the slot on the motherboard without the need for dedicated test equipment by transmitting the signal received by the signal receiving terminal of the low-cost retimer chip through an external link or inside the chip to the signal sending terminal of the retimer chip, thereby greatly reducing the production test cost of the motherboard. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
上述實施例僅例示性說明本發明的原理及其功效，而非用於限制本發明。任何熟悉此技術的人士皆可在不違背本發明的精神及範疇下，對上述實施例進行修飾或改變。因此，舉凡所屬技術領域中具有通常知識者在未脫離本發明所揭示的精神與技術思想下所完成的一切等效修飾或改變，仍應由本發明的權利要求所涵蓋。 The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person with ordinary knowledge in the relevant technical field without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.
100:插槽連通性測試裝置 100: Slot connectivity test device
110:電路板 110: Circuit board
120:連接端 120:Connection terminal
130:重定時器(Retimer)晶片 130: Retimer chip
140:回傳模組 140: Feedback module
141:控制板 141: Control panel
142:回傳電路 142: Feedback circuit
210:待測主機板的插槽 210: Slot of the motherboard to be tested
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| CN116643208A (en) * | 2023-06-25 | 2023-08-25 | 深圳市芯瞳半导体技术有限公司 | High-speed transmission link detection device |
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