TWI552522B - Differential signal generating circuit - Google Patents
Differential signal generating circuit Download PDFInfo
- Publication number
- TWI552522B TWI552522B TW102110726A TW102110726A TWI552522B TW I552522 B TWI552522 B TW I552522B TW 102110726 A TW102110726 A TW 102110726A TW 102110726 A TW102110726 A TW 102110726A TW I552522 B TWI552522 B TW I552522B
- Authority
- TW
- Taiwan
- Prior art keywords
- transmission line
- signal transmission
- coupled
- receiving end
- differential
- Prior art date
Links
- 230000008054 signal transmission Effects 0.000 claims description 67
- 238000013016 damping Methods 0.000 claims description 34
- 230000008878 coupling Effects 0.000 claims 1
- 238000010168 coupling process Methods 0.000 claims 1
- 238000005859 coupling reaction Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 11
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 4
- 230000005611 electricity Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
Description
本發明係相關於一種差動訊號產生電路，尤指一種可改善訊號完整度之差動訊號產生電路。 The present invention relates to a differential signal generating circuit, and more particularly to a differential signal generating circuit that can improve signal integrity.
請同時參考第1圖及第2圖。第1圖及第2圖為習知分支(multi-drop)差動訊號產生電路100輸出差動訊號的示意圖。如圖所示，習知分支差動訊號產生電路100包含一差動驅動電路110，複數條訊號傳輸線L1、L2、L3、L4，及一終端電阻TR。差動驅動電路110具有一第一輸出端TX1及一第二輸出端TX2，用以交錯地輸出一正向電流If及一反向電流Ir。正向電流If及反向電流Ir之電流值相同。第一訊號傳輸線L1係耦接於第一接收端RX1及第一輸出端TX1之間。第二訊號傳輸線L2係耦接於第二接收端RX2及第二輸出端TX2之間。終端電阻TR之第一端係耦接於第一訊號傳輸線L1，終端電阻TR之第二端係耦接於第二訊號傳輸線L2。第三訊號傳輸線L3係耦接於第三接收端RX3及第一輸出端TX1之間。第四訊號傳輸線L4係耦接於第四接收端RX4及第二輸出端TX2之間。 Please refer to both Figure 1 and Figure 2. 1 and 2 are schematic diagrams showing the output of the differential signal by the multi-drop differential signal generating circuit 100. As shown, the conventional branch differential signal generating circuit 100 includes a differential driving circuit 110, a plurality of signal transmission lines L1, L2, L3, and L4, and a terminating resistor TR. The differential driving circuit 110 has a first output terminal TX1 and a second output terminal TX2 for alternately outputting a forward current If and a reverse current Ir. The current values of the forward current If and the reverse current Ir are the same. The first signal transmission line L1 is coupled between the first receiving end RX1 and the first output end TX1. The second signal transmission line L2 is coupled between the second receiving end RX2 and the second output end TX2. The first end of the terminating resistor TR is coupled to the first signal transmission line L1, and the second end of the terminating resistor TR is coupled to the second signal transmission line L2. The third signal transmission line L3 is coupled between the third receiving end RX3 and the first output end TX1. The fourth signal transmission line L4 is coupled between the fourth receiving end RX4 and the second output end TX2.
依據上述配置，當差動驅動電路110輸出正向電流If時，正向電流If會依序流經第一訊號傳輸線L1、終端電阻TR及第二訊號傳輸線L2，進而於第一接收端RX1及第三接收端RX3產生正電壓訊號+V，及於第二接收端RX2及第四接收端RX4產生負電壓訊號-V；當差動驅動電路110輸出反向電流Ir時，反向電流Ir會依序流經第二訊號傳輸線L2、終端電阻TR及第 一訊號傳輸線L1，進而於第一接收端RX1及第三接收端RX3產生負電壓訊號-V，及於第二接收端RX2及第四接收端RX4產生正電壓訊號+V。第一接收端RX1及第二接收端RX2接收的電壓訊號即為一對差動訊號，相似地，第三接收端RX3及第四接收端RX4接收的電壓訊號亦為一對差動訊號，且第一及第二接收端RX1、RX2接收的一對差動訊號係相同於第三及第四接收端RX3、RX4接收的一對差動訊號。 According to the above configuration, when the differential driving circuit 110 outputs the forward current If, the forward current If flows through the first signal transmission line L1, the terminating resistor TR and the second signal transmission line L2, and then to the first receiving end RX1 and The third receiving end RX3 generates a positive voltage signal +V, and generates a negative voltage signal -V at the second receiving end RX2 and the fourth receiving end RX4; when the differential driving circuit 110 outputs the reverse current Ir, the reverse current Ir Passing through the second signal transmission line L2, the terminating resistor TR and the A signal transmission line L1 generates a negative voltage signal -V at the first receiving end RX1 and the third receiving end RX3, and generates a positive voltage signal +V at the second receiving end RX2 and the fourth receiving end RX4. The voltage signals received by the first receiving end RX1 and the second receiving end RX2 are a pair of differential signals. Similarly, the voltage signals received by the third receiving end RX3 and the fourth receiving end RX4 are also a pair of differential signals, and The pair of differential signals received by the first and second receiving ends RX1 and RX2 are the same as the pair of differential signals received by the third and fourth receiving ends RX3 and RX4.
然而，在習知分支差動訊號產生電路100中，由於第一及第二接收端RX1、RX2之間設置有終端電阻TR，而第三及第四接收端RX3、RX4係開路殘端，亦即第三及第四接收端RX3、RX4和第三及第四訊號傳輸線L3、L4之間並沒有電阻，因此第一及第二接收端RX1、RX2的阻抗無法和第三及第四接收端RX3、RX4的阻抗匹配，進而造成訊號反射(reflection)，使得差動訊號的訊號完整度(signal integrity,SI)變差。請參考第3圖，第3圖為習知分支差動訊號產生電路輸出的差動訊號的眼圖。如第3圖所示，訊號反射會使得差動訊號產生過沖(overshoot)與下沖(undershoot)現象，進而使得一對差動訊號之間的辨識度變差，亦即訊號完整度變差。 However, in the conventional branch differential signal generating circuit 100, since the terminating resistor TR is disposed between the first and second receiving terminals RX1 and RX2, and the third and fourth receiving terminals RX3 and RX4 are open stubs, That is, there is no resistance between the third and fourth receiving ends RX3, RX4 and the third and fourth signal transmission lines L3, L4, so the impedances of the first and second receiving ends RX1, RX2 cannot be combined with the third and fourth receiving ends. The impedance matching of RX3 and RX4 causes signal reflection, which makes the signal integrity (SI) of the differential signal deteriorate. Please refer to FIG. 3, which is an eye diagram of the differential signal outputted by the conventional branch differential signal generating circuit. As shown in Figure 3, the signal reflection causes the overshoot and undershoot of the differential signal, which worsens the discrimination between a pair of differential signals, that is, the signal integrity is deteriorated. .
本發明之目的在於提供一種可改善訊號完整度之差動訊號產生電路，以解決先前技術的問題。 It is an object of the present invention to provide a differential signal generating circuit that improves signal integrity to solve the problems of the prior art.
本發明差動訊號產生電路包含一差動驅動電路，具有一第一輸出端及一第二輸出端，用以交錯地輸出一正向電流及一反向電流；一第一訊號傳輸線，耦接於一第一接收端及該第一輸出端之間；一第二訊號傳輸線，耦接於一第二接收端及該第二輸出端之間；一終端電阻，其第一端耦接於該第一訊號傳輸線，第二端耦接於該第二訊號傳輸線；一第三訊號傳輸線，耦接於該第一輸出端；一第四訊號傳輸線，耦接於該第二輸出端；一第一阻尼電 阻，耦接於該第三訊號傳輸線及一第三接收端之間；及一第二阻尼電阻，耦接於該第四訊號傳輸線及一第四接收端之間。其中該第一接收端及該第二接收端係用以接收一對差動訊號，且該第三接收端及該第四接收端係用以接收該對差動訊號。 The differential signal generating circuit of the present invention comprises a differential driving circuit having a first output end and a second output end for alternately outputting a forward current and a reverse current; a first signal transmission line coupled Between a first receiving end and the first output end; a second signal transmission line coupled between a second receiving end and the second output end; a terminal resistor, the first end of which is coupled to the a first signal transmission line, the second end is coupled to the second signal transmission line; a third signal transmission line is coupled to the first output end; a fourth signal transmission line is coupled to the second output end; Damping electricity The resistor is coupled between the third signal transmission line and a third receiving end; and a second damping resistor coupled between the fourth signal transmission line and a fourth receiving end. The first receiving end and the second receiving end are configured to receive a pair of differential signals, and the third receiving end and the fourth receiving end are configured to receive the pair of differential signals.
本發明另提供一種顯示驅動系統，包含一差動訊號產生電路，一第一顯示驅動晶片，及一第二顯示驅動晶片。該差動訊號產生電路係用以產生一對差動訊號，該差動訊號產生電路包含一差動驅動電路，具有一第一輸出端及一第二輸出端，用以交錯地輸出一正向電流及一反向電流；一第一訊號傳輸線，耦接於一第一接收端及該第一輸出端之間；一第二訊號傳輸線，耦接於一第二接收端及該第二輸出端之間；一終端電阻，其第一端耦接於該第一訊號傳輸線，第二端耦接於該第二訊號傳輸線；一第三訊號傳輸線，耦接於該第一輸出端；一第四訊號傳輸線，耦接於該第二輸出端；一第一阻尼電阻，耦接於該第三訊號傳輸線及一第三接收端之間；及一第二阻尼電阻，耦接於該第四訊號傳輸線及一第四接收端之間。該第一顯示驅動晶片係耦接於該第一接收端及該第二接收端，用以根據該對差動訊號產生一第一組顯示訊號。該第二顯示驅動晶片係耦接於該第三接收端及該第四接收端，用以根據該對差動訊號產生一第二組顯示訊號。 The invention further provides a display driving system comprising a differential signal generating circuit, a first display driving chip, and a second display driving chip. The differential signal generating circuit is configured to generate a pair of differential signals, the differential signal generating circuit includes a differential driving circuit having a first output end and a second output end for alternately outputting a forward direction a current signal and a reverse current; a first signal transmission line coupled between a first receiving end and the first output end; a second signal transmission line coupled to a second receiving end and the second output end a first terminal is coupled to the first signal transmission line, the second end is coupled to the second signal transmission line, and a third signal transmission line is coupled to the first output end; The signal transmission line is coupled to the second output end; a first damping resistor coupled between the third signal transmission line and a third receiving end; and a second damping resistor coupled to the fourth signal transmission line And a fourth receiving end. The first display driving chip is coupled to the first receiving end and the second receiving end for generating a first set of display signals according to the pair of differential signals. The second display driving chip is coupled to the third receiving end and the fourth receiving end for generating a second group of display signals according to the pair of differential signals.
相較於先前技術，本發明差動訊號產生電路係將阻尼電阻設置於開路殘端的接收端，以抑制差動訊號的訊號反射，進而改善差動訊號的訊號完整度。 Compared with the prior art, the differential signal generating circuit of the present invention sets the damping resistor to the receiving end of the open circuit stump to suppress the signal reflection of the differential signal, thereby improving the signal integrity of the differential signal.
100,200‧‧‧分支差動訊號產生電路 100,200‧‧‧ branch differential signal generation circuit
110,210‧‧‧差動驅動電路 110,210‧‧‧Differential drive circuit
300‧‧‧顯示驅動系統 300‧‧‧Display drive system
310‧‧‧第一顯示驅動晶片 310‧‧‧First display driver chip
320‧‧‧第二顯示驅動晶片 320‧‧‧Second display driver chip
L1‧‧‧第一訊號傳輸線 L1‧‧‧ first signal transmission line
L2‧‧‧第二訊號傳輸線 L2‧‧‧second signal transmission line
L3‧‧‧第三訊號傳輸線 L3‧‧‧ third signal transmission line
L4‧‧‧第四訊號傳輸線 L4‧‧‧fourth signal transmission line
TX1‧‧‧第一輸出端 TX1‧‧‧ first output
TX2‧‧‧第二輸出端 TX2‧‧‧ second output
RX1‧‧‧第一接收端 RX1‧‧‧ first receiving end
RX2‧‧‧第二接收端 RX2‧‧‧second receiving end
RX3‧‧‧第三接收端 RX3‧‧‧ third receiver
RX4‧‧‧第四接收端 RX4‧‧‧fourth receiving end
If‧‧‧正向電流 If‧‧‧ forward current
Ir‧‧‧反向電流 Ir‧‧‧ reverse current
TR‧‧‧終端電阻 TR‧‧‧ terminating resistor
DR1‧‧‧第一阻尼電阻 DR1‧‧‧First damping resistor
DR2‧‧‧第二阻尼電阻 DR2‧‧‧second damping resistor
+V,-V‧‧‧電壓訊號 +V,-V‧‧‧Voltage signal
第1圖為習知分支差動訊號產生電路輸出差動訊號的示意圖。 FIG. 1 is a schematic diagram of a differential signal generated by a conventional branch differential signal generating circuit.
第2圖為習知分支差動訊號產生電路輸出差動訊號的示意圖。 Figure 2 is a schematic diagram showing the output of the differential signal by the conventional branch differential signal generating circuit.
第3圖為習知分支差動訊號產生電路輸出的差動訊號的眼圖。 Figure 3 is an eye diagram of the differential signal output by the conventional branch differential signal generating circuit.
第4圖為本發明分支差動訊號產生電路輸出差動訊號的示意圖。 FIG. 4 is a schematic diagram of the differential signal generation circuit of the present invention outputting a differential signal.
第5圖為本發明分支差動訊號產生電路輸出差動訊號的示意圖。 FIG. 5 is a schematic diagram of the differential signal generation circuit of the present invention outputting a differential signal.
第6圖為本發明分支差動訊號產生電路輸出的差動訊號的眼圖。 Figure 6 is an eye diagram of the differential signal outputted by the branch differential signal generating circuit of the present invention.
第7圖為本發明顯示驅動系統的示意圖。 Figure 7 is a schematic view of the display drive system of the present invention.
請同時參考第4圖及第5圖。第4圖及第5圖為本發明分支(multi-drop)差動訊號產生電路200輸出差動訊號的示意圖。如圖所示，本發明差動訊號產生電路200包含一差動驅動電路210，複數條訊號傳輸線L1、L2、L3、L4，一終端電阻TR，一第一阻尼電阻DR1，及一第二阻尼電阻DR2。差動驅動電路210，具有一第一輸出端TX1及一第二輸出端TX2，用以交錯地輸出一正向電流If及一反向電流Ir。正向電流If及反向電流Ir之電流值相同。第一訊號傳輸線L1係耦接於第一接收端TX1及第一輸出端RX1之間。第二訊號傳輸線L2係耦接於第二接收端RX2及第二輸出端TX2之間。終端電阻TR之第一端係耦接於第一訊號傳輸線L1，終端電阻TR之第二端係耦接於第二訊號傳輸線L2。第三訊號傳輸線L3係耦接於第一輸出端TX1。第四訊號傳輸線L4係耦接於第二輸出端TX2。第一阻尼電阻DR1係耦接於第三訊號傳輸線L3及第三接收端RX3之間。第二阻尼電阻DR2係耦接於第四訊號傳輸線L4及第四接收端RX4之間。第一阻尼電阻DR1及第二阻尼電阻DR2之電阻值相同。 Please also refer to Figures 4 and 5. 4 and 5 are schematic diagrams showing the output of the differential signal by the multi-drop differential signal generating circuit 200 of the present invention. As shown in the figure, the differential signal generating circuit 200 of the present invention comprises a differential driving circuit 210, a plurality of signal transmission lines L1, L2, L3, L4, a terminating resistor TR, a first damping resistor DR1, and a second damping. Resistance DR2. The differential driving circuit 210 has a first output terminal TX1 and a second output terminal TX2 for alternately outputting a forward current If and a reverse current Ir. The current values of the forward current If and the reverse current Ir are the same. The first signal transmission line L1 is coupled between the first receiving end TX1 and the first output end RX1. The second signal transmission line L2 is coupled between the second receiving end RX2 and the second output end TX2. The first end of the terminating resistor TR is coupled to the first signal transmission line L1, and the second end of the terminating resistor TR is coupled to the second signal transmission line L2. The third signal transmission line L3 is coupled to the first output terminal TX1. The fourth signal transmission line L4 is coupled to the second output terminal TX2. The first damping resistor DR1 is coupled between the third signal transmission line L3 and the third receiving end RX3. The second damping resistor DR2 is coupled between the fourth signal transmission line L4 and the fourth receiving end RX4. The resistance values of the first damping resistor DR1 and the second damping resistor DR2 are the same.
依據上述配置，當差動驅動電路210輸出正向電流If時，正向電流If會依序流經第一訊號傳輸線L1、終端電阻TR及第二訊號傳輸線L2，進而於第一接收端RX1及第三接收端RX3產生正電壓訊號+V，及於第二接收端RX2及第四接收端RX4產生負電壓訊號-V；當差動驅動電路210輸出反 向電流Ir時，反向電流Ir會依序流經第二訊號傳輸線L2、終端電阻TR及第一訊號傳輸線L1，進而於第一接收端RX1及第三接收端RX3產生負電壓訊號-V，及於第二接收端RX2及第四接收端RX4產生正電壓訊號+V。第一接收端RX1及第二接收端RX2接收的電壓訊號即為一對差動訊號，相似地，第三接收端RX3及第四接收端RX4接收的電壓訊號亦為一對差動訊號。由於第一阻尼電阻DR1及第二阻尼電阻DR2幾乎沒有電流流過，亦即不會造成電壓降，因此第三及第四接收端RX3、RX4接收的一對差動訊號係幾乎相同於第一及第二接收端RX1、RX2接收的一對差動訊號。 According to the above configuration, when the differential driving circuit 210 outputs the forward current If, the forward current If flows through the first signal transmission line L1, the terminating resistor TR and the second signal transmission line L2, and then to the first receiving end RX1 and The third receiving end RX3 generates a positive voltage signal +V, and generates a negative voltage signal -V at the second receiving end RX2 and the fourth receiving end RX4; when the differential driving circuit 210 outputs the opposite When the current is Ir, the reverse current Ir flows through the second signal transmission line L2, the terminating resistor TR and the first signal transmission line L1, and generates a negative voltage signal -V at the first receiving end RX1 and the third receiving end RX3, And generating a positive voltage signal +V at the second receiving end RX2 and the fourth receiving end RX4. The voltage signals received by the first receiving end RX1 and the second receiving end RX2 are a pair of differential signals. Similarly, the voltage signals received by the third receiving end RX3 and the fourth receiving end RX4 are also a pair of differential signals. Since the first damping resistor DR1 and the second damping resistor DR2 have almost no current flowing, that is, no voltage drop is generated, the pair of differential signals received by the third and fourth receiving terminals RX3 and RX4 are almost the same as the first. And a pair of differential signals received by the second receiving ends RX1 and RX2.
另一方面，由於第三訊號傳輸線L3及第三接收端RX3之間設置有第一阻尼電阻DR1，且第四訊號傳輸線L4及第四接收端RX4之間設置有第二阻尼電阻DR2，因此第一及第二接收端RX1、RX2的阻抗可以和第三及第四接收端RX3、RX4的阻抗互相匹配，進而抑制訊號反射(reflection)，使得差動訊號的訊號完整度(signal integrity,SI)變好。請參考第6圖，第6圖為本發明分支差動訊號產生電路輸出的差動訊號的眼圖。如第6圖所示，由於訊號反射被抑制，進而減少差動訊號的過沖(overshoot)與下沖(undershoot)現象，因此一對差動訊號之間的辨識度變好，亦即改善差動訊號的訊號完整度。 On the other hand, since the first damping resistor DR1 is disposed between the third signal transmission line L3 and the third receiving terminal RX3, and the second damping resistor DR2 is disposed between the fourth signal transmission line L4 and the fourth receiving terminal RX4, The impedances of the first and second receiving ends RX1 and RX2 can be matched with the impedances of the third and fourth receiving terminals RX3 and RX4, thereby suppressing signal reflection and making signal integrity (SI) of the differential signal. Getting better. Please refer to FIG. 6. FIG. 6 is an eye diagram of the differential signal outputted by the branch differential signal generating circuit of the present invention. As shown in Fig. 6, since the signal reflection is suppressed, thereby reducing the overshoot and undershoot of the differential signal, the discrimination between the pair of differential signals becomes better, that is, the difference is improved. The signal integrity of the signal.
請參考第7圖，第7圖為本發明顯示驅動系統300的示意圖。如第7圖所示，本發明差動訊號產生電路200可應用於一顯示驅動系統。顯示驅動系統300的第一顯示驅動晶片310係耦接於第一接收端RX1及第二接收端RX2，用以根據差動訊號產生電路200輸出的一對差動訊號產生第一組顯示訊號；而顯示驅動系統300的第二顯示驅動晶片320係耦接於第三接收端RX3及第四接收端RX4，用以根據差動訊號產生電路200輸出的一對差動訊號產生第二組顯示訊號。第一顯示驅動晶片310及第二顯示驅動晶片320皆包含一源極驅動電路及一時序控制電路。第一組顯示訊號及第二組顯示訊號 可用以分別驅動顯示面板的不同顯示區塊。 Please refer to FIG. 7. FIG. 7 is a schematic diagram of the display driving system 300 of the present invention. As shown in Fig. 7, the differential signal generating circuit 200 of the present invention can be applied to a display driving system. The first display driving chip 310 of the display driving system 300 is coupled to the first receiving end RX1 and the second receiving end RX2 for generating a first set of display signals according to a pair of differential signals output by the differential signal generating circuit 200; The second display driving chip 320 of the display driving system 300 is coupled to the third receiving end RX3 and the fourth receiving end RX4 for generating a second set of display signals according to a pair of differential signals output by the differential signal generating circuit 200. . Each of the first display driving chip 310 and the second display driving chip 320 includes a source driving circuit and a timing control circuit. The first group of display signals and the second group of display signals It can be used to drive different display blocks of the display panel separately.
另外，在本發明實施例中，第一阻尼電阻DR1及第二阻尼電阻DR2之電阻值是介於10歐姆到100歐姆之間，且差動訊號產生電路200是一低電壓差動訊號(low voltage differential signal,LVDS)產生電路。 In addition, in the embodiment of the present invention, the resistance values of the first damping resistor DR1 and the second damping resistor DR2 are between 10 ohms and 100 ohms, and the differential signal generating circuit 200 is a low voltage differential signal (low) Voltage differential signal (LVDS) generates a circuit.
相較於先前技術，本發明差動訊號產生電路係將阻尼電阻設置於開路殘端的接收端，以抑制差動訊號的訊號反射，進而改善差動訊號的訊號完整度。 Compared with the prior art, the differential signal generating circuit of the present invention sets the damping resistor to the receiving end of the open circuit stump to suppress the signal reflection of the differential signal, thereby improving the signal integrity of the differential signal.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
200‧‧‧分支差動訊號產生電路 200‧‧‧ branch differential signal generation circuit
210‧‧‧差動驅動電路 210‧‧‧Differential drive circuit
L1‧‧‧第一訊號傳輸線 L1‧‧‧ first signal transmission line
L2‧‧‧第二訊號傳輸線 L2‧‧‧second signal transmission line
L3‧‧‧第三訊號傳輸線 L3‧‧‧ third signal transmission line
L4‧‧‧第四訊號傳輸線 L4‧‧‧fourth signal transmission line
TX1‧‧‧第一輸出端 TX1‧‧‧ first output
TX2‧‧‧第二輸出端 TX2‧‧‧ second output
RX1‧‧‧第一接收端 RX1‧‧‧ first receiving end
RX2‧‧‧第二接收端 RX2‧‧‧second receiving end
RX3‧‧‧第三接收端 RX3‧‧‧ third receiver
RX4‧‧‧第四接收端 RX4‧‧‧fourth receiving end
If‧‧‧正向電流 If‧‧‧ forward current
Ir‧‧‧反向電流 Ir‧‧‧ reverse current
TR‧‧‧終端電阻 TR‧‧‧ terminating resistor
DR1‧‧‧第一阻尼電阻 DR1‧‧‧First damping resistor
DR2‧‧‧第二阻尼電阻 DR2‧‧‧second damping resistor
+V,-V‧‧‧電壓訊號 +V,-V‧‧‧Voltage signal
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102110726A TWI552522B (en) | 2013-03-26 | 2013-03-26 | Differential signal generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102110726A TWI552522B (en) | 2013-03-26 | 2013-03-26 | Differential signal generating circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201438399A TW201438399A (en) | 2014-10-01 |
| TWI552522B true TWI552522B (en) | 2016-10-01 |
Family
ID=52113524
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102110726A TWI552522B (en) | 2013-03-26 | 2013-03-26 | Differential signal generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI552522B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6812741B2 (en) * | 1999-04-22 | 2004-11-02 | Matsushita Electric Industrial Co., Ltd. | Bidirectional signal transmission circuit and bus system |
| TW200709748A (en) * | 2005-08-19 | 2007-03-01 | Hon Hai Prec Ind Co Ltd | Arrangement of transmission lines on printed circuit board |
| US7274583B2 (en) * | 2004-12-31 | 2007-09-25 | Postech | Memory system having multi-terminated multi-drop bus |
| US7768310B2 (en) * | 2007-04-03 | 2010-08-03 | Panasonic Corporation | Semiconductor device, method of switching drive capability of the semiconductor device, and system including semiconductor devices |
| WO2012017691A1 (en) * | 2010-08-05 | 2012-02-09 | Gvbb Holdings S.A.R.L. | Ac coupled single-ended lvds receiving circuit comprising low-pass filter and voltage regulator |
| US20120250436A1 (en) * | 2011-04-04 | 2012-10-04 | Byungcheol Cho | Impedance matching between fpga and memory modules |
-
2013
- 2013-03-26 TW TW102110726A patent/TWI552522B/en active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6812741B2 (en) * | 1999-04-22 | 2004-11-02 | Matsushita Electric Industrial Co., Ltd. | Bidirectional signal transmission circuit and bus system |
| US7274583B2 (en) * | 2004-12-31 | 2007-09-25 | Postech | Memory system having multi-terminated multi-drop bus |
| TW200709748A (en) * | 2005-08-19 | 2007-03-01 | Hon Hai Prec Ind Co Ltd | Arrangement of transmission lines on printed circuit board |
| US7768310B2 (en) * | 2007-04-03 | 2010-08-03 | Panasonic Corporation | Semiconductor device, method of switching drive capability of the semiconductor device, and system including semiconductor devices |
| WO2012017691A1 (en) * | 2010-08-05 | 2012-02-09 | Gvbb Holdings S.A.R.L. | Ac coupled single-ended lvds receiving circuit comprising low-pass filter and voltage regulator |
| US20120250436A1 (en) * | 2011-04-04 | 2012-10-04 | Byungcheol Cho | Impedance matching between fpga and memory modules |
Non-Patent Citations (1)
| Title |
|---|
| Zemo Yang; Rahman, M.; Mourad, S., "Signal integrity and design consideration of an MCM for video graphic acceleration," Advanced Packaging, IEEE Transactions on , vol.24, no.3, pp.309,316, Aug 2001. * |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201438399A (en) | 2014-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5451772B2 (en) | Data transmission system | |
| JP5543402B2 (en) | Ringing suppression circuit | |
| CN102324922B (en) | Low Voltage Differential Signal Driving Circuit and Digital Signal Transmitter | |
| CN109714041B (en) | High-speed signal driving circuit | |
| EP3154201B1 (en) | Differential driver circuit and method for controlling a differential driver circuit | |
| TWI587648B (en) | Full-duplex transceiver circuit and method of operating a full-duplex transceiver circuit | |
| KR101156914B1 (en) | System and method for providing a full fail-safe capability in signal transmission networks | |
| US20140210520A1 (en) | Low power low voltage differential driver | |
| US9716306B2 (en) | Directional coupler and communication device including same | |
| CN108334467A (en) | Transmitters and Receivers for Low Voltage Differential Signaling | |
| CN103378846B (en) | A kind of device that logical signal is converted to Low Voltage Differential Signal | |
| CN107872218B (en) | Current mode logic circuit | |
| TWI552522B (en) | Differential signal generating circuit | |
| CN204256735U (en) | The nonpolarity RS-485 interface chip of the inner upper pull down resistor of band | |
| TWI554027B (en) | Transmission line driver circuit for adaptively calibrating impedance matching | |
| TWI590752B (en) | Circuit board capable of decreasing cross talk | |
| US11005477B2 (en) | Driver circuit and control method therefor, and transmission/reception system | |
| CN205105240U (en) | Communication circuit | |
| CN107659476B (en) | Communication device | |
| CN104462000A (en) | Nonpolar RS-485 interface chip with internal pull-up and pull-down resistors | |
| CN108804361A (en) | A kind of PCIE switches based on VPX bus architectures | |
| CN107766278B (en) | A high-speed serial interface receiver front-end circuit compatible with DC/AC coupling | |
| CN106548742A (en) | Panel driving circuit | |
| TWI648636B (en) | Universal serial bus type c transmission line and transmission device | |
| CN204719747U (en) | The compatible equipment of Serial Peripheral Interface (SPI), Serial Peripheral Interface (SPI) and main process equipment |