201016094 --------iy!53twf.doc/n 九'發明說明： 【發明所屬之技術領域】 本發明是有關於-種線路板的製作方法 P職ss) ’且制是有關於—翻埋式線路結構的 製作方法。 【先前技術】 ❻ 近年來’隨著電子技術的日新月異，以及高科技電子 產業的相繼問世，具有佈線細密、平整表面的内埋式線路 結構已成為下一代線路基板的研發重點，以避免習知印刷 線路板的線路表面凹凸過大而造成蝕刻不均勻或漏 陷。並且，内埋式線路板的線路内埋於介電層的表面中， 因此線路層與介電層之間有較佳之接合性質，不易剝離， 且線路層不易文到製程所應用之敍刻液作用而影響到線路 層之線路寬度，因而具有佈線細密及縮小線距的優點。 於習知技術中，在製作線路板時，通常會在其外部之 糁 線路層及圖案化防焊層（solder mask layer)製作完^之^， 再於線路層所形成之接墊(bonding pad)表面上電鍍—抗氧 化層，例如一鎳金層(Ni/Au layer)，以防止接墊的表面氧化。 此外，在内埋式線路的領域中，藉由製作導電盲孔結 構（conductive blind via)，可使多層電路板（m爾妨订 circuit board)中的各層線路得以在相鄰層間電性連接。爲 了滿足目前電路板朝向縮小線路寬度與線路間距以及提高 線路密度的發展趨勢，這些導電盲孔結構一般是先採用雷 iyl53twf.doc/n 201016094 射鑽孔製程（laser drilling)來形成盲孔，再將導電材料填 入於盲孔中觸成。但是，由於微細線路的表面上可供雷 射鑽孔的空間有限，若從微細線路的表面以雷射鑽孔容^ 造成雷射偏移或對位上的誤差，且導電材料沈積在微細的 線路上的厚度不均勻’也會對後續餘刻製程的線路平坦戶 造成不良影響’因此有待業界進一步改良製程^ 程的良率。 【發明内容】 本發明提供一種内埋式線路結構的製作方法，以減少 雷射偏移或對位上的誤差。 參 本發明提出-種内埋式線路結構的製作方法 供-具有-第一導電層、一核心層以及一第二導電二^ ^其中一第-導電賴第二導電層分取—域法預先形I 而的弟-喃魏料二m鱗路之後，碰合至核 對二表面上;以雷射加工法形成至少―貫穿第^二仿目 =的盲孔’其中盲孔的孔徑由線路佈局密度相對小於 路2 一:埋線路朝第二内埋線路縮小;於第二導電層上形 成第阻障層’並形成一導電材料於盲孔中， -内埋線路與第二内埋線路;全面性 = 出所需的第—内埋線路.以料占② 》電曰以顯路 摊姐廿㈣山 成一第一防焊層以覆蓋第—内 x月之一霄施例中，全面性薄化第-導電層之後 更包括下列步驟:首先，移除第-轉層，並於第;二 6 29153twfdoc/n 201016094 料；全面㈣化第二導騎，賴露出所需 及开彡点一绝二L移除第二阻障層，以顯露第一内埋線路，·以 内埋線路上Μ防^層以覆蓋第二内埋線路，並麟出位於第二 内埋線路上的一第二抗氧化層。 提供ίΓΓί提出—翻埋輕路結構的㈣綠。首先， 線路弟—導電層、一核心層以及一第二導電層的 成所·的第内it電層與第二導電層分別以一加成法預先形 與第二_線路之後，秘合至核心層 ' ^ ，以雷射加工法形成至少一貫穿第一導電戶盥 核心層的盲孔，其中盲孔的孔獲由線路佈局;： =Γ 一，朝第二内埋線路縮：於第二導雜 接=線：J ’:形成-導電材料於盲孔中，以電性連 埋線路;於第—導電層上形成-第- ϋ層暴/_^2電層的-表面;於第一導電 鬌 未被該第—抗氧化層覆蓋的第電n顯^層=及薄化 路；以及形成-第-防焊層以覆蓋該二埋^第 P方焊層暴露出該第-抗氧化層。 Μ霄路且遠弟一 ^本發明之—實施例中，_式線路 更f:列步驟:首先’移除第-阻障層，並於上 n—覆盍層’第二覆蓋層暴露出第導曰 於第二導電層的此表面上形成—第騎的—表面， 層以及薄化未被第二抗氧移除第二覆蓋 二内埋線——mm 7 z9153twf.d〇c/n 201016094 第二防焊層暴露出第二抗氧化層。 蜜-ίΙΓ，—f内埋式線路結構，其包括—核心層、— 乂及-第-"—第二内埋線路、—導電材料、—第一防悍層 二層。第一内埋線路以及第二内埋線路分別埋入 盲二曰並At r表面。導電材料填入於貫穿核心層的至少一 1_丨接第一内埋線路以及第二内埋線路，其中盲 並顯露出位於第-路， 一i:以埋線路，並顯露出位於第二内埋線路上的 时祕轉及錢作方法，其經由第一 導電】來執仃雷射鑽孔，以形成至少一貫穿第—導電層愈 核二層的盲孔。如此’盲孔的孔徑由線路佈局密 ^ 於第-内埋線路的第一内埋線路朝 ς 、 此=對於經由第二導電層來執行雷射鑽孔=雷： 偏移或對位上的誤差。 ^雷射 ，讓本發明之上述特徵和優點能更明顯易懂，下 舉杈佳貫施例’並配合所附圖式，作詳細說明如下。、 【實施方式】 第一實施例 圖1Α〜圖1G為本發明第_實施例的 的製作方法的示意圖。 式線路〜構 201016094—d / ….....zyl53twf.doc/n 首先’請參照圖ΙΑ ’提供一線路板H〇。線路板u〇 例如是預定形成内埋線路的銅箔基板，且銅箔基板可以具 有單層或雙層内埋線路，本實施例是以雙層内埋線路的銅 箔基板為例作說明’但並非用以限定本發明。 線路板110具有一第一導電層112以及一第二導電層 116,其材質例如為銅，且在圖案化線路之前，第一導電層 112與第二導電層116分別以一加成法預先形成所需的第 ❹一内埋線路112a與第二内埋線路n6a。詳細而言，第一 内埋線路112a與第二内埋線路116a是以半加成法局部電 鍍而形成在銅箔（導電層）上，或以全加成法電鍍再局部 蝕刻而形成在銅箔（導電層）上，之後再堆疊壓合至半固 化態的核心層114的相對二表面上’也就是核心層114的 上表面114a與下表面U4b。此時，第一内埋線路112&與 第二内埋線路116a分別内埋於核心層114的上表面U4a 與下表面114b中。接著’再加熱烘烤半固化態的核心層 114,使其固化成形。 ® 第一内埋線路112a與第二内埋線路n6a分別具有多 =第接塾P1及第二接塾p2，但第一接塾Μ的面積大於 弟二接塾P2的面積1相_第„接墊pi2_間距也 目鄰的第二接墊P2之間的間距，因此第一内埋線路 a與第二内埋線路U6a的線路佈局密度也隨著接塾面 =冋、線距的不同而有所不同。在本實施例中，第一内 =ma的線路佈局密度相對小於第二内埋線路肠 佈局⑨度’舉例來說’第—内埋線路112&可為銲球 iy!53twf.doc/n 201016094 接合面（solder side)的線路或接墊’而接 差。此外，第二内埋線路116a可為元件接人面/位上的误 side)的線路或接墊，而接塾面積 ^面（component 的誤差較大，不利於後續雷射鑽孔的作i:’因而對位上 ❹ 法形=少請射鑽孔步驟’當以雷射加工 貝穿第—導電層U2與核心層山 時，目孔BV的倾由線路佈局 、目 路U6a的第-内埋線路ii 1對、於第二内埋線 如先前步驟所述，由於第—内埋線：n【、、’，U6a縮小。 面的線路)的接塾面積相對較大 a::=接合 小於第-內拽始π /人且其線路佈局密度相對 (例如元件接合面的線路)，因此 來執行雷射鑽孔，相對於經由第二導 II 仃田射鑽孔，可減少雷射偏移或對位上的誤 二導=1Β及圖lc的填孔步驟。首先，於第 或印刷Γ第—阻障層140，例如是貼附膠膜 上之後，將線路板110放置於化學 及盲孔的中的電鍍種子層120來進 真孔步驟’以形成—導電材料122於盲孔 如圖1C所示。 在本實施例中，形成導電材料m於盲孔中以電性連 dy!53twf.doc/n 201016094 接第一内埋線路U2a與第二内埋線路U6a，不限 述的方式實施’故形成導電材料122的方法可為電 法、化學沈積法、氣相沈積法或濺鍍法等，而導電 乃 除了是實心的導電體之外，亦可以是填入油墨或 空心導電體’其材質例如是銅或各類導電缪等。此外何， 圖1C中，經過單面填孔步驟之後，接著進行圖 ^ 性薄化第-導電層m的步驟，例如是_第_導電層j 二覆蓋。第-導電層112上的電鍍種子層i2。與二材 ;斗2。缚化之後而顯露出具有平整表面的第—内埋線 由於第-内埋線路必的平整度高且内埋於核心芦201016094 --------iy!53twf.doc/n 九' invention description: [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a circuit board P ss) 'and the system is related - The method of making a buried circuit structure. [Prior Art] 近年来 In recent years, with the rapid development of electronic technology and the advent of the high-tech electronics industry, buried wiring structures with fine wiring and flat surfaces have become the focus of research and development of next-generation circuit boards. The surface roughness of the printed wiring board is too large to cause uneven etching or leakage. Moreover, the wiring of the buried circuit board is buried in the surface of the dielectric layer, so that the wiring layer and the dielectric layer have better bonding properties, are not easy to be peeled off, and the circuit layer is not easy to be applied to the process. The effect affects the line width of the circuit layer, and thus has the advantages of fine wiring and reduced line spacing. In the prior art, when a circuit board is fabricated, a solder pad layer is formed on the outer layer and a solder mask layer, and a bonding pad is formed on the circuit layer. The surface is plated - an oxidation resistant layer, such as a Ni/Au layer, to prevent surface oxidation of the pads. In addition, in the field of buried wiring, by making a conductive blind via, the layers of the multilayer circuit board can be electrically connected between adjacent layers. In order to meet the current trend of reducing the line width and line spacing and increasing the line density of the circuit board, these conductive blind hole structures are generally formed by using laser drilling to form a blind hole, and then using a laser drilling method to form a blind hole. The conductive material is filled in a blind hole and touched. However, since the space available for laser drilling on the surface of the fine line is limited, if the laser drilling capacity is caused from the surface of the fine line, the laser offset or alignment error is caused, and the conductive material is deposited on the fine The uneven thickness on the line will also have a negative impact on the flat-line households of the subsequent remnant process's. Therefore, the industry is expected to further improve the yield of the process. SUMMARY OF THE INVENTION The present invention provides a method of fabricating a buried wiring structure to reduce laser offset or alignment error. The invention provides a method for fabricating an internal buried circuit structure, having a first conductive layer, a core layer and a second conductive layer, wherein the first conductive layer and the second conductive layer are separated by a domain method. After the shape I and the wei-wei material two m scale road, it is brought into contact with the surface of the check two; the laser processing method forms at least the "blind hole through the second ^ simulation = the aperture of the blind hole by the line layout The density is relatively smaller than the road 2: the buried line is reduced toward the second buried line; the first barrier layer is formed on the second conductive layer and a conductive material is formed in the blind hole, the buried line and the second buried line; Comprehensiveness = the required first-buried line. The material is occupied by 2 》Electric 曰 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显 显After thinning the first conductive layer, the method further comprises the steps of: firstly, removing the first-transfer layer, and at the second; 2, 2, 259, 153 ftfdoc/n 201016094; comprehensively (four) arranging the second lead riding, revealing the required and opening point The second barrier layer L removes the second barrier layer to expose the first buried circuit, and the buried layer is covered with a protective layer to cover the second buried layer. The line is lined with a second anti-oxidation layer on the second buried line. Providing ίΓΓί proposed—the (four) green of the buried light path structure. First, the first inner electric layer and the second conductive layer of the conductive layer, the first core layer and the second conductive layer are respectively pre-shaped with the second line by an additive method, and then The core layer ' ^ , forming at least one blind hole penetrating through the core layer of the first conductive household by laser processing, wherein the hole of the blind hole is obtained by the line layout;: = Γ one, shrinking toward the second buried line: Two-conductor hybrid = line: J ': formed - conductive material in the blind hole, electrically connected to the line; formed on the first conductive layer - the first - ϋ layer storm / _ ^ 2 electric layer - surface; a first conductive germanium is not covered by the first anti-oxidation layer and a thinning path; and a first-pre-solder layer is formed to cover the second buried P-side solder layer to expose the first- Antioxidant layer. In the embodiment of the invention, the _-type circuit is more f: column step: first 'removing the first barrier layer, and exposing the second cladding layer on the upper n-cladding layer' The first lead is formed on the surface of the second conductive layer - the first riding surface, the layer and the thinning are not removed by the second anti-oxidation second covering two buried wires - mm 7 z9153twf.d〇c/n 201016094 The second solder mask exposes a second oxidation resistant layer. Honey- ΙΓ, -f buried circuit structure, including - core layer, - 乂 and - - - " - second buried line, - conductive material, - first layer of anti-mite layer. The first buried line and the second buried line are buried in the blind dike and Atr surface, respectively. The conductive material is filled in at least one of the first buried circuit and the second buried circuit penetrating through the core layer, wherein the blind and exposed are located at the first path, and the i: is buried, and is exposed at the second The time-sharing and money-making method on the buried circuit, the laser drilling is performed via the first conductive to form at least one blind hole penetrating the second layer of the first conductive layer. Thus the aperture of the 'blind hole is densely arranged by the line layout on the first buried line of the first buried circuit, 此, for the laser drilling via the second conductive layer = Ray: offset or alignment error. The above features and advantages of the present invention will become more apparent and obvious, and the following description will be taken in conjunction with the accompanying drawings. [Embodiment] First Embodiment FIG. 1A to FIG. 1G are schematic views showing a manufacturing method of a first embodiment of the present invention. Type line ~ structure 201016094-d / ........zyl53twf.doc/n First 'please refer to Figure ’' to provide a circuit board H〇. The circuit board u is, for example, a copper foil substrate on which a buried circuit is to be formed, and the copper foil substrate may have a single layer or a double layer buried circuit. In this embodiment, a copper foil substrate with a double buried circuit is taken as an example for description. However, it is not intended to limit the invention. The circuit board 110 has a first conductive layer 112 and a second conductive layer 116, the material of which is, for example, copper. Before the patterned circuit, the first conductive layer 112 and the second conductive layer 116 are respectively formed by an additive method. The first buried circuit 112a and the second buried line n6a are required. In detail, the first buried wiring 112a and the second buried wiring 116a are partially plated by a semi-additive method to form a copper foil (conductive layer), or are plated by a full-addition method and then partially etched to form a copper layer. On the foil (conductive layer), it is then stacked and pressed onto the opposite surfaces of the core layer 114 of the semi-cured state, that is, the upper surface 114a and the lower surface U4b of the core layer 114. At this time, the first buried wiring 112& and the second buried wiring 116a are buried in the upper surface U4a and the lower surface 114b of the core layer 114, respectively. Next, the semi-cured core layer 114 is baked again and cured to form a solidified layer. The first buried line 112a and the second buried line n6a have more than the first connection P1 and the second connection p2, respectively, but the area of the first connection is larger than the area of the second connection P2. The pitch between the pads pi2_ is also adjacent to the second pads P2, so the line layout density of the first buried line a and the second buried line U6a is also different according to the joint surface = 冋, line spacing In this embodiment, the line layout density of the first inner =ma is relatively smaller than the layout of the second buried line intestines. For example, the first buried circuit 112& can be a solder ball iy! 53twf .doc/n 201016094 The line or pad of the solder side is connected. In addition, the second buried line 116a may be the line or the pad of the component's access surface/bit.塾 area ^ surface (component error is large, it is not conducive to the subsequent laser drilling i: 'so the upper position of the ❹ = = = less drilling step] when the laser processing of the shell - the conductive layer U2 In the case of the core layer, the tilt of the eyelet BV is determined by the line layout, the first-embedded line ii 1 of the head U6a, and the second buried line as in the previous step. As described, the first-embedded line: n [,, ', U6a is reduced. The surface of the line) has a relatively large joint area a::= joint is smaller than the first-inner start π / person and its line layout density is relative ( For example, the line of the component joint surface, so as to perform the laser drilling, the laser offset can be reduced by the second guide II, and the error of the laser offset or the misalignment of the alignment can be reduced. Hole step. First, after the first or printed Γ first barrier layer 140, for example, after attaching the adhesive film, the circuit board 110 is placed in the chemical and blind hole in the plating seed layer 120 to enter the true hole step ' The conductive material 122 is formed in the blind via hole as shown in FIG. 1C. In this embodiment, the conductive material m is formed in the blind via to electrically connect the dy! 53twf.doc/n 201016094 to the first buried circuit U2a and the second The buried line U6a is implemented in a manner not described so that the method of forming the conductive material 122 may be an electric method, a chemical deposition method, a vapor deposition method, or a sputtering method, and the conduction is in addition to a solid electric conductor. It can also be filled with ink or hollow conductors, such as copper or various types of conductive crucibles. In FIG. 1C, after the single-sided filling step, the step of thinning the first conductive layer m is performed, for example, the _the first conductive layer j is covered. The plating seed layer i2 on the first conductive layer 112 With the two materials; bucket 2. After the binding, the first buried line with a flat surface is revealed, because the first buried line must have a high flatness and is buried in the core
液丄沒!=表面’因而在薄化過程中不易受到“ 液的知蝕，以保持内埋線路的完整性。 J ,完簡化第-導電層112的步驟之後 =圖1F的步驟之外，亦可直接進行圖心？ 3層二30的製作，以覆蓋第-内埋線路ma，再於顯露 =:=12a(即接録面)上電鑛或無電』 以f’例如是錄金層’以防止缝表面氧化。 的步驟。首ΠΑΓ1E·1F的薄化第上導電層 埋二ΐΐ 的第一阻障層140，並於第-内 、、Ua上形成一第二阻障層150,例如 印刷液態光阻層，以防如疋貼齡膜或 n2a^s „ ^ 以顯露出具有平整表面_ —靴導電層116， 庄的第-阻第二内埋線路U6a，最後移除圖 第—阻p早層15G’以顯露第—内埋線路112a。 ^yl53twf.doc/n 201016094 值得注意的是，在圖1E中 22〜4微米，相對於圖lc的第-導電層丨：二· =路佈局密度較低的線路）以及其上的電4 2電材料122的總厚度而言，厚度明顯減少許多丄均勾 性較佳，因此經過圖1F的蝕刻薄化之後 夾= ❺Liquid helium! = surface' is therefore less susceptible to "liquid etch in the thinning process to maintain the integrity of the buried line. J, after the step of simplifying the first conductive layer 112 = step of Figure 1F, Can also directly carry out the picture heart? 3 layer 2 30 production, to cover the first-embedded line ma, and then reveal the =: = 12a (ie the recording surface) on the electricity or no electricity" f' for example is the gold layer The step of preventing the surface of the seam from being oxidized. The first barrier layer 140 of the first conductive layer is buried in the first conductive layer of the first layer 1E·1F, and a second barrier layer 150 is formed on the first inner and the Ua. For example, a liquid photoresist layer is printed to prevent a film or a n2a^s „ ^ to expose a flat surface _ the shoe conductive layer 116, and a second burying circuit U6a, and finally remove the figure. - Blocking the early layer 15G' to reveal the first buried line 112a. ^yl53twf.doc/n 201016094 It is worth noting that in Figure 1E 22~4 microns, relative to the first conductive layer of Figure lc: the circuit with a lower density of the layout of the circuit and the electricity 4 2 In terms of the total thickness of the electrical material 122, the thickness is significantly reduced, and many of the ruthenium properties are better, so after the thinning of the etching of FIG. 1F, the clip = ❺
=二内埋線路116a的平整度明顯改善，自然不會有線路凹 或凹凸不平的缺陷。對於第二導電層116 (用以製作線 局密度較高的線路)而言，線路平整度的要求g乍同 時符合客製化的需求且提高製程的良率。 心/=卜φ第埋線路116a的平整度較高且内埋於核 日 中又有凹凸表面，因而在薄化過程中不易受到 蝕刻液的侵蝕，以保持内埋線路的完整性。= The flatness of the two buried lines 116a is significantly improved, and naturally there are no defects such as concave or uneven lines. For the second conductive layer 116 (used to make a line with a higher line density), the line flatness requirement g符合 meets the requirements of customization and improves the yield of the process. The core/= Bu φ buried line 116a has a high flatness and is embedded in the core day and has a concave-convex surface, so that it is less susceptible to etching by the etching liquid during the thinning process to maintain the integrity of the buried line.
當完成薄化第二導電層u㈣步驟之後，則進行圖1G ^弟—防焊層134的製作，以覆蓋第二内埋線路116a，再 ;顯露的第二内埋線路116a (即接墊表面）上電鍍 電鍍一第二抗氧化層136，例如是鎳金層’以防止接；表 面虱化。如此，大致上完成具有微細線路及平整表面的内 埋式線路結構100。 以了介紹本發明第二實施例，雖然第二實施例的製作 法與弟只施例的製作方法略有不同，但均是經由第一 導電層112來執行雷射鑽孔，以形成至少一貫穿第—導電 ^ 112與核心層114的盲孔BV，且盲孔BV的孔徑係由線 ^佈局密度相對小於第二内埋線路116a的第-内埋線路 朝第一内埋線路116a縮小。因此，相對於經由第二 12 201016094一祕 導電層116來執行雷射鑽孔，可減少雷射偏移或對位上的 誤差。有關第一實施例的製作方法，僅簡要地介紹各個步 驟的流程，並未如第一實施例一般詳細描述各個步驟的^ 容，以避免贅述。 第二實施例 圖2A〜圖2F為本發明第二實施例的内埋式線路結構 的製作方法的示意圖。首先，請參照圖2A，提供—線路板 〇 110，而線路板110具有一第一導電層112、一核心層114 以及一第二導電層116。第—導電層112與第二導電層116 分別以一加成法預先形成所需的第一内埋線路丨12a與第 二内埋線路116a之後，再壓合至半固化態的核心層114 的相對二表面上。 接著’請參考圖2B的雷射鑽孔步驟，以形成至少一 貫穿第一導電層112與核心層114的盲孔bv，且盲孔Bv 的孔授係由線路佈局密度相對小於第二内埋線路116a的 第一内埋線路112a朝第二内埋線路U6a縮小。有關雷射 β 鑽孔的說明及減少雷射偏移或對位上的誤差，請參考第一 實施例的說明。 接著，請參考圖2Β及圖2C的填孔步驟。首先，於第 二導電層116上形成一第一阻障層μο,並形成一導電材 料122於盲孔BV中，以電性連接第一内埋線路U2a與第After the step of thinning the second conductive layer u (4) is completed, the fabrication of the solder resist layer 134 of FIG. 1G is performed to cover the second buried wiring 116a, and the exposed second buried wiring 116a (ie, the surface of the pad) A second anti-oxidation layer 136 is electroplated, for example, a nickel-gold layer to prevent bonding; the surface is deuterated. Thus, the buried wiring structure 100 having the fine wiring and the flat surface is substantially completed. In order to introduce the second embodiment of the present invention, although the manufacturing method of the second embodiment is slightly different from the manufacturing method of the other embodiments, the laser drilling is performed through the first conductive layer 112 to form at least one. The blind hole BV of the first conductive layer 112 and the core layer 114 is penetrated, and the aperture of the blind hole BV is narrowed toward the first buried circuit 116a by the first buried line 116 having a line layout density smaller than that of the second buried line 116a. Therefore, the laser offset or alignment error can be reduced with respect to performing laser drilling via the second 12 201016094 first conductive layer 116. Regarding the manufacturing method of the first embodiment, only the flow of each step is briefly introduced, and the details of the respective steps are not described in detail as in the first embodiment to avoid redundancy. Second Embodiment Figs. 2A to 2F are schematic views showing a method of fabricating a buried wiring structure according to a second embodiment of the present invention. First, referring to FIG. 2A, a circuit board 110 is provided, and the circuit board 110 has a first conductive layer 112, a core layer 114, and a second conductive layer 116. The first conductive layer 112 and the second conductive layer 116 are respectively formed into a desired first buried circuit 12a and a second buried line 116a by an additive method, and then pressed into the semi-cured core layer 114. On the opposite surface. Then, please refer to the laser drilling step of FIG. 2B to form at least one blind hole bv penetrating through the first conductive layer 112 and the core layer 114, and the hole of the blind hole Bv is given a line layout density which is relatively smaller than the second buried layer. The first buried line 112a of the line 116a is shrunk toward the second buried line U6a. For a description of laser beta drilling and to reduce laser offset or misalignment, please refer to the description of the first embodiment. Next, please refer to the filling step of FIG. 2A and FIG. 2C. First, a first barrier layer μ is formed on the second conductive layer 116, and a conductive material 122 is formed in the blind via BV to electrically connect the first buried wiring U2a and the first
二内埋線路U6a。有關導電材料122的製程請參考第一奋 施例的說明。 H 接著，移除圖2C的第一阻障層14〇之後，請參考圖 13 201016094 iy\53twf.doc/n 2D，於導電材料122上形成-第一覆蓋層142，且第 蓋層⑷,顯露出導電材料m的一表面（即預定形成接塾 的表面），之後於顯露的導電材料122上電鑛或無電電鑛 而形成-弟-抗氧化層132，例如是錄金層，以防止接塾 表面氧化。在本實施例中，圖2D的步驟更可進行 帛二覆蓋層144於第二導電層116上，且第二覆蓋層⑷ =出弟：導電層116的一表面（即預定形成接墊的表 β Si』於顯露的第二導電層116上電鑛或無電電鍍而 开巧-弟二抗氧化層136，例如是錄金層，以防止接塾表 nr\i J Li 當完成第-抗氧化層132之後，進行圖2E的薄化 2的步驟。首先，移除圖2D的第-覆蓋層142,接著薄 1種子層120及未被第一抗氧化層132覆蓋的第一導 2 ㈣枝触’以顯露出具有平整表面 =-内埋線路112a。在本實施例中，圖2£的步驟更可 進仃移除第二覆蓋層144,接著薄 — ❿覆蓋的第1靜w彳此 第—抗氧化層136 且右：例如以蝕刻方式薄化，以顯露出 ，、有千整表面的第二内埋線路116a。 以覆it請參考圖2F的步驟，形成一第一防焊層Two buried lines U6a. For the manufacturing process of the conductive material 122, please refer to the description of the first embodiment. H, after removing the first barrier layer 14A of FIG. 2C, referring to FIG. 13 201016094 iy\53twf.doc/n 2D, a first cover layer 142 is formed on the conductive material 122, and the first cover layer (4), A surface of the conductive material m (ie, a surface on which the interface is intended to be formed) is exposed, and then a conductive or electroless ore is formed on the exposed conductive material 122 to form an anti-oxidation layer 132, such as a gold layer, to prevent The surface of the joint is oxidized. In this embodiment, the step of FIG. 2D can further perform the second cover layer 144 on the second conductive layer 116, and the second cover layer (4) = a surface of the conductive layer 116 (ie, a table that is intended to form a pad). SiSi" is electroplated or electrolessly plated on the exposed second conductive layer 116 to open the anti-oxidation layer 136, such as a gold layer, to prevent the nr\i J Li from being connected to the first anti-oxidation. After layer 132, the step of thinning 2 of Figure 2E is performed. First, the first cap layer 142 of Figure 2D is removed, followed by the thin 1 seed layer 120 and the first lead 2 (four) branches not covered by the first anti-oxidation layer 132. Touch 'to reveal a flat surface =- buried line 112a. In this embodiment, the step of FIG. 2 can further remove the second cover layer 144, and then the thin-❿ covered first static w The first anti-oxidation layer 136 and the right side: for example, thinned by etching to expose the second buried line 116a having a thousand surfaces. To cover it, please refer to the step of FIG. 2F to form a first solder resist layer.
才m内埋線路112a，且第—防焊層130暴露出第一 ^化層132。本實施射，圖2F :二二焊^ 線路及tit—抗乳化層136°如此’大致上完成具有微細 、、及平整表面的内埋式線路結構100a。 iy!53twf.doc/n 201016094 ”發明之内埋式線路結構的製作方法可適 =夕層的線路板上，無論是具有導電線的線路板 t線的祕板’均可製料平整度高且㈣於核心層G 線路層’㈣符合客製化的需求且提高製程的 =由第-導電層（用以製作線路饰局密度較低的線路）卜來 鑽孔i以形成至少—貫穿第™導電層與核心層的 埋線路的第-内埋線路朝第二内埋線路縮小。因此第 ^由第二導電層（用以製作線路佈局密度較高的線路)十 來執灯雷射鑽孔，可減少雷射偏移或對位上的誤差、 =本發明已啸佳實施·露如上，然其° 限疋本發明’任何關技術領域巾具有通常知 = 脫離本發日狀精神和範_，當可作些許之絲與 因此本發明之保護範圍當視後附之申 二二， 為準。 τ π判關所界定者 _ 【圖式簡單說明】 的製本發明第—實施㈣峡式線路結構 的製作圖:T的發明第二實__埋式線路結構 【主要元件符號說明】 100、100a :内埋式線路結構 15 201016094』3twfdoc/n 110 :線路板 112 :第一導電層 112a :第一内埋線路 114 :核心層 114a :上表面 114b :下表面 116 :第二導電層 116a :第二内埋線路 P1 :第一接墊 P2 :第二接墊 BV :盲孔 120 :電鍍種子層 122 :導電材料 130 :第一防焊層 132 :第一抗氧化層 134 :第二防焊層 136 :第二抗氧化層 140 :第一阻障層 142 :第一覆蓋層 144 :第二覆蓋層 150 :第二阻障層 16The line 112a is buried, and the first solder resist layer 130 exposes the first layer 132. In the present embodiment, Fig. 2F: the second and second soldering lines and the tit-anti-emulsification layer 136° thus substantially complete the buried wiring structure 100a having a fine, flat surface. Iy!53twf.doc/n 201016094 ”The invention can be used to make the embedded circuit structure. The circuit board of the circuit board with the conductive line can be made with high flatness. And (4) in the core layer G circuit layer '(4) meets the requirements of customization and improve the process = by the first conductive layer (used to make the line with lower density of the line decoration) to drill hole i to form at least - through the The first buried circuit of the buried layer of the TM conductive layer and the core layer is shrunk toward the second buried line. Therefore, the second conductive layer (for making a line with a higher line layout density) is used to light the laser drill. Hole, can reduce the laser offset or the error in the alignment, = the invention has been implemented, the above is the same as the above, but the limit of the invention is "any technical field of the towel has the usual knowledge = off the spirit of the day and the spirit _, when a certain amount of silk can be made and therefore the scope of protection of the present invention is subject to the application of the second paragraph, τ π is defined by the _ _ simplification of the description of the invention - the implementation of the (four) gorge Production diagram of the line structure: T's invention second actual __ buried line structure Element Symbol Description 100, 100a: Buried Line Structure 15 201016094』3twfdoc/n 110: Circuit Board 112: First Conductive Layer 112a: First Buried Line 114: Core Layer 114a: Upper Surface 114b: Lower Surface 116 : second conductive layer 116a : second buried line P1 : first pad P2 : second pad BV : blind hole 120 : electroplating seed layer 122 : conductive material 130 : first solder resist layer 132 : first anti-oxidation Layer 134: second solder resist layer 136: second anti-oxidation layer 140: first barrier layer 142: first cover layer 144: second cover layer 150: second barrier layer 16