1355725 • 九、發明說明： • 【發明所屬之技術領域】 本發明係關於一種疊層氧化鋁基板及其製法，尤指一 種不易彎曲且具高線路密度之疊層氧化鋁基板及其製法。 5 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 (Integration )以及微型化（Miniaturization )的封裝要求， .10 提供多數主被動元件及線路連接之封裝基板，亦逐漸由單 • 層板演變成多層板，以使在有限的空間下，藉由層間連接 技術（Interlayer connection)擴大封裝基板上可利用的佈 線面積而配合尚電子密度之積體電路（Integrated eircuh ) 需求。 15 一般半導體裝置之製程，首先係由晶片載板製造業者 生產適用於該半導體裝置之晶片載板，如基板或導線架。 _ 之後再將該些晶片載板交由半導體封裝業者進行置晶、打 線、封膠以及植球等封裝製程《又一般半導體封裝是將半 導體晶片背面黏貼於封裝基板頂面進行打線接合（wire 20 bonding )，或者將半導體晶片之作用面以覆晶接合（fiip chip)方式與封裝基板接合，再於基板之背面植以焊料球以 供與其他電子裝置如印刷電路板進行電性連接。 上述之封裝基板可參考圖1所示之結構。目前業界常用 BT樹脂（BismaleimideTriazineResin)作為核心板 η 的材 5 1355725 料，而後進行線路製程，以於核心板π表面形成線路12及 導通核心板11兩側表面線路12之電锻導通孔121，再利用增 層技術形成增層結構13，其中，該增層結構13係包括導電 . 盲孔131及增層線路層132及介電層134 ’最後於增層結構13 * 5 表面形成一防焊層14 ’形成一封裝基板1〇。 然而’因上述核心板採用ΒΤ樹脂（Bismaleimide TriazineResin)作為材料，而增層結構13之介電層ι34之材 料大多為ABF樹脂（Ajinomoto build-up film)，通常不同 鲁材料所具有之熱膨脹係數（Coefficient of .thermal 1〇 exPanslon ’ CTE )不同。封裝基板10常因核心板11 ( Βτ樹 脂）與介電層134(ABF樹脂）兩者熱膨脹係數之差異（CTE _ difference )’或者因核心板11兩表面之增層結構13不對稱， 致使以BT樹脂為材質之硬度低封裝基板1〇因不對稱應力產 生彎翹情況’導致生產成品良率偏低且可靠度不佳。 15 另外’上述之封裝基板1〇需要核心板11，而其線路佈 局（例如線路12及増層線路層132)僅配置於核心板^及介 _ 電層134表面，但核心板11及介電層134中間沒有配置線 路’故封裝基板1 〇上可配置線路之空間較少。因此，若能 降低封裝基板產生板彎翹情況，並且提高封裝基板之生產 20良率’同時提高線路佈局之密度，將使封裝基板之應用性 提高。 【發明内容】 6 1355725 急“广缺點，本發明之主要目的係在提供-種疊層 =紹基板及其製法。本發明所提供之㈣氧㈣基板， =、有不易因應力彎曲之特性，且其厚度較薄並充分利 用氧化鋁基板線路佈局空間以提高線路密度。 51355725 • IX. DESCRIPTION OF THE INVENTION: 1. Field of the Invention The present invention relates to a laminated alumina substrate and a method of producing the same, and more particularly to a laminated alumina substrate which is less flexible and has a high line density and a method for producing the same. 5 [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the high integration and miniaturization requirements of semiconductor packages, .10 provides a majority of active and passive components and circuit-connected package substrates, and gradually evolved from single-layer boards to multi-layer boards. In a limited space, the interlayer area available on the package substrate is expanded by the interlayer connection technology to meet the requirements of the integrated electron density integrated circuit (Integrated eircuh). 15 The general semiconductor device process begins with a wafer carrier manufacturer producing a wafer carrier, such as a substrate or leadframe, suitable for the semiconductor device. _ After the wafer carrier is transferred to the semiconductor package manufacturer for the process of crystallization, wire bonding, sealing and ball-balling, etc. "Generally, the semiconductor package is to adhere the back surface of the semiconductor wafer to the top surface of the package substrate for wire bonding (wire 20 Bonding, or bonding the active surface of the semiconductor wafer to the package substrate in a flip-chip manner, and then soldering the solder balls on the back surface of the substrate for electrical connection with other electronic devices such as printed circuit boards. The above package substrate can be referred to the structure shown in FIG. At present, the BT resin (Bismaleimide Triazine Resin) is commonly used in the industry as the material of the core plate η 5 1355725, and then the line process is performed to form the line 12 on the surface of the core plate π and the electric forged via hole 121 of the surface 12 on both sides of the core board 11 , and then The build-up structure 13 is formed by a build-up technique, wherein the build-up structure 13 comprises a conductive layer. The blind via 131 and the build-up wiring layer 132 and the dielectric layer 134 ′ finally form a solder resist layer on the surface of the build-up structure 13 * 5 . 14 'Form a package substrate 1 〇. However, because the core plate is made of Bismaleimide Triazine Resin, the material of the dielectric layer ι34 of the build-up structure 13 is mostly ABF resin (Ajinomoto build-up film), which usually has different thermal expansion coefficients ( Coefficient of .thermal 1〇exPanslon ' CTE ) is different. The package substrate 10 is often asymmetrical due to the difference in thermal expansion coefficient between the core plate 11 (the Βτ resin) and the dielectric layer 134 (ABF resin) (CTE _ difference ) or due to the augmentation structure 13 of the two surfaces of the core plate 11 The low hardness of the BT resin is that the package substrate 1 has a bending condition due to the asymmetric stress, resulting in a low yield of the finished product and poor reliability. 15 In addition, the above-mentioned package substrate 1 requires the core board 11, and its circuit layout (for example, the line 12 and the layer line layer 132) is disposed only on the surface of the core board and the dielectric layer 134, but the core board 11 and the dielectric There is no line disposed in the middle of layer 134. Therefore, there is less space on the package substrate 1 for configurable lines. Therefore, if the bending of the package substrate is reduced, and the yield of the package substrate is increased, and the density of the layout is increased, the applicability of the package substrate is improved. SUMMARY OF THE INVENTION 6 1355725 Anxious "wide disadvantages, the main purpose of the present invention is to provide a laminate = Shao substrate and its preparation method. The (four) oxygen (four) substrate provided by the present invention, =, is not easy to bend due to stress characteristics, And its thickness is thin and make full use of the aluminum substrate line layout space to increase the line density.
10 為達成上述目的，本發明提供一種疊層氧化紹基板， 包括.複數氧化⑭基板，其分別具有__氧化銘層以及一 第-線路層’ Λ中，該氧健層具有複數貫穿之開口區， 而該第一線路層係配置並嵌埋於該複數開口區令，且該第 一線路層係齊平於該氧化鋁層相對兩表面；以及複數介電 層，其中各該介電層係設置於各該氧化鋁基板之間，使該 些氧化鋁基板上下疊層。 上述之疊層氧化紹基板係可包括一電鐘導通孔貫穿該 疊層氧化鋁基板，其中，該導電通孔電性連接該疊層氧化 鋁基板之該第一線路層。或者，上述之疊層氧化鋁基板也 15 可再包括一第二線路層係配置於該疊層氧化鋁基板之兩側 表面’並直接電性連接至該第一線路層。而該疊層氧化鋁 基板表面也可再覆蓋有一防焊層，且該防焊層具有複數開 孔顯露部分該第二線路層以作為電性連接墊。 上述之疊層氧化鋁基板中，該疊層氧化鋁基板之兩側 2〇 表面係亦可具有一介電層，以及一電鍍導通孔貫穿貫穿該 些氧化鋁基板及介電層，其中，該導電通孔電性連接該疊 層氧化鋁基板之該第一線路層。該介電層内復可具有複數 導電盲孔，以及第二線路層設置於該介電層表面，該第二 線路層係藉由該些導電盲孔電性連接至該第一線路層。 7 ⑶）/25 ‘ 本發明另提供一種疊層氧化結基板之製法，包括：提 *供複數氧化紹基板，其分別具有一氧化紹層、以及一第一 線路層，其中，該氧化紹層具有複數貫穿之開口區而該 第-線路層係配置並嵌埋於該複數開口區令，且該第一線 5路層係齊平於該氧化紹層相對兩表面；設置一介電層於各 該氧化紹基板之間；以及麼合該些氧化㉝基板及該介電 層’使該些氧化銘基板上下疊層。 /上述製法更可包括於塵合該些氧化铭基板及該介電層 • 《爰’形成-電鍍導通孔貫穿該疊層氧化鋁基板，其中，該 1。4電通孔電性連接該些氧化銘基板之該第—線路層。也可 選擇性包括於壓合該些氧化鋁基板及該介電層後，形成一 第二線路層係配置於該疊層之氧化鋁基板表面，其中，該 第一線路層直接電性連接該第一線路層。而且，此製法也 可再包括於形成該第二線路層後，形成一防焊層覆蓋該些 15疊層之氧化鋁基板表面，其中，該防焊層具有複數開孔顯 露部分該第二線路層以作為電性連接墊。 Φ 本發明更提供一種疊層氧化鋁基板之製法，包括：提 供複數氧化鋁基板’其分別具有一氧化鋁層、以及一第一 線路層’其中，該氧化鋁層具有複數貫穿之開口區，而該 20 第一線路層係配置並嵌埋於該開口區中，且該第一線路層 係齊平於該氧化鋁層相對兩表面；於各該氧化鋁基板之兩 側表面分別設置一介電層；以及壓合該些氧化鋁基板及該 些介電層，使該些氧化鋁基板上下疊層。 1355725 上述製法更可選擇性包括於壓合該些氧化銘基板及該 介電層後，形成一電鍍導通孔貫穿該些氧化鋁基板及介電 . 層，其中，該導電通孔電性連接該些氧化鋁基板之該第一 線路層。也可包括於壓合該些氧化鋁基板及該介電層後， 5 於疊層氧化銘基板之兩側表面的介電層内形成複數導電盲 孔，並於該介電層表面形成第二線路層，該第二線路層係 藉由該些導電盲孔電性連接至該第一線路層。而且，此製 法也可再包括於形成该第一線路層及該些導電盲孔後，形 φ 成一防焊層覆蓋該些疊層之氧化鋁基板表面，其中，該防 10焊層具有複數開孔顯露部分該第二線路層以作為電性連接 墊。 . 由上述疊層氧化鋁基板及其製法得知，因可將線路配 置於氧化鋁層中，故線路佈局密度能因此增加，進而減少 整體封裝基板之厚度，符合輕薄短小之趨勢。此外，所形 15成之疊層氧化鋁基板中，基板間不同線路層可透過導電通 孔貫穿疊層氧化鋁基板，使不同線路層能夠相互電性連 Φ #。另一方面’習知以Βτ樹脂為材質之核心板常因硬度不 足而無法承受增層結構或熱膨脹係數差所產生之不對稱應 力，所會發生基板彎曲情形，並且若要增加線路佈局，則 20必須增加增層結構的層數，此勢必亦會增加封裝基板的厚 度；然而本發明所使用之材質為硬度較高之氣化銘做為基 j，因^可減少上述基板彎曲情形，進而使成品良率及可 罪度提兩，且利用複數内嵌有線路層之氡化鋁基板與介電 9 1355725 並具有較高的線路佈局密 層相互疊層歷合，可減少厚度 度，而具有較高電性功能。 【實施方式】 以下係藉由特定的具體實施例說明本發 f習此技藝之人士可由本說明書所揭示之内容輕： 的:其他優點與功效。本發明亦可藉由其他不同 、體貧_加以騎或助，本㈣書巾的各項細節亦 ==點與應用’在不脖離本發明之精神下進行各 本發明之實施例中該等圖式均為簡化之示意圖。惟該 專圖式僅顯示與本發明有關之元件，其所顯示之元件非為 實際實施時之態樣，其實際實施時之元件數目、形狀等比 例為一選擇性之設計，且其元件佈局型態可能更複雜。 實施例1 % 參考圖2A至圖2N，其為製作本發明氧化鋁基板之流程 示意剖視圖。 首先’如圖2A所示，提供一鋁層21，此鋁層21係具有 ° 一第一表面21 a及一相對之第二表面2lb。接著，如圖2B所 示，形成一形成一第一阻層22於銘層21之第一表面21 a上， 以保護該第一表面21a。形成此第一阻層22之方式，可透過 壓合乾膜或塗佈液態光阻所形成。 1355725 如圖2C所示，利用陽極處理，將未受第一阻層22保護 的鋁層21之第二表面21b氧化’以形成一氧化鋁層23於第二 表面21b。而後’如圖2D所示，形成一圖案化之第二阻層24 於氧化銘層23表面。形成此圖案化之第二阻層24之方式， 5 可透過壓合乾膜或塗佈液態光阻形成阻層，再以曝光顯影 形成圖案化之第·一阻層24。接著’如圖2E所示，透過钱刻 以圖案化氧化鋁層23 ’便使氧化鋁層23具有複數第一開口 區23 1顯露部分鋁層21。本實施例蝕刻方式可為電漿蝕刻 (plasma etching )、化學蝕刻、或電溶解（electrodiss〇luti〇n ) 10 等，以使氧化鋁層23圖案化。 然後’如圖2F所示，移除第一阻層22及第二阻層24。 剝除之方式係可取決於第一阻層22及第二阻層24之材質，In order to achieve the above object, the present invention provides a laminated oxide substrate comprising: a plurality of oxidized 14 substrates each having an __oxidized layer and a first-line layer Λ, the oxygen layer having a plurality of openings a region, wherein the first circuit layer is disposed and embedded in the plurality of open regions, and the first circuit layer is flush with opposite surfaces of the aluminum oxide layer; and a plurality of dielectric layers, wherein each of the dielectric layers The alumina substrate is disposed between the alumina substrates, and the alumina substrates are stacked on top of each other. The laminated oxide substrate may include a conductive via extending through the laminated alumina substrate, wherein the conductive via is electrically connected to the first wiring layer of the laminated aluminum oxide substrate. Alternatively, the laminated alumina substrate 15 may further include a second wiring layer disposed on both side surfaces of the laminated alumina substrate and directly electrically connected to the first wiring layer. The surface of the laminated alumina substrate may be further covered with a solder resist layer, and the solder resist layer has a plurality of openings to expose a portion of the second circuit layer as an electrical connection pad. In the laminated alumina substrate, the two sides of the laminated alumina substrate may have a dielectric layer, and a plating via penetrates through the aluminum substrate and the dielectric layer. The conductive via is electrically connected to the first circuit layer of the laminated alumina substrate. The dielectric layer has a plurality of conductive vias, and the second circuit layer is disposed on the surface of the dielectric layer. The second circuit layer is electrically connected to the first circuit layer by the conductive vias. 7 (3)) / 25 ' The present invention further provides a method for fabricating a laminated oxide junction substrate, comprising: providing a plurality of oxide substrates, each having an oxide layer and a first circuit layer, wherein the oxide layer The first circuit layer is disposed and embedded in the plurality of open areas, and the first line 5 layer is flush with the opposite surfaces of the oxide layer; a dielectric layer is disposed on the first opening layer Between each of the oxide substrates, and the oxide 33 substrate and the dielectric layer 'the oxide substrates are stacked one on top of the other. The above method may further comprise dusting the oxidized substrate and the dielectric layer. The 爰' formation-plating via extends through the laminated alumina substrate, wherein the 4.7 electrical via is electrically connected to the oxidized layer. The first layer of the substrate. Optionally, the method further includes: after pressing the aluminum oxide substrate and the dielectric layer, forming a second circuit layer disposed on the surface of the stacked aluminum oxide substrate, wherein the first circuit layer is directly electrically connected to the The first circuit layer. Moreover, the manufacturing method may further include forming a solder resist layer covering the surface of the 15 stacked aluminum oxide substrates after forming the second circuit layer, wherein the solder resist layer has a plurality of open holes to expose the second line The layer acts as an electrical connection pad. The invention further provides a method for manufacturing a laminated alumina substrate, comprising: providing a plurality of alumina substrates each having an aluminum oxide layer and a first wiring layer, wherein the aluminum oxide layer has a plurality of open regions extending through The first circuit layer is disposed in the open area, and the first circuit layer is flush with the opposite surfaces of the aluminum oxide layer; And electrically pressing the aluminum oxide substrate and the dielectric layers to laminate the aluminum oxide substrates on top of each other. 1355725 The method further includes selectively forming a plated via hole through the aluminum oxide substrate and the dielectric layer after pressing the oxide substrate and the dielectric layer, wherein the conductive via is electrically connected to the conductive via The first circuit layer of the alumina substrate. The method further includes: after pressing the aluminum oxide substrate and the dielectric layer, forming a plurality of conductive blind holes in the dielectric layer on both sides of the laminated oxide substrate, and forming a second surface on the surface of the dielectric layer. The circuit layer is electrically connected to the first circuit layer by the conductive blind vias. Moreover, the method can also be further included after forming the first circuit layer and the conductive vias, and forming a solder mask to cover the surface of the stacked aluminum oxide substrate, wherein the anti-10 solder layer has a plurality of openings The hole exposes a portion of the second circuit layer as an electrical connection pad. According to the above laminated alumina substrate and the method for producing the same, since the wiring can be disposed in the aluminum oxide layer, the wiring layout density can be increased, thereby reducing the thickness of the entire package substrate and conforming to the trend of lightness and thinness. In addition, in the 15% laminated alumina substrate, different circuit layers between the substrates can penetrate the laminated alumina substrate through the conductive vias, so that different circuit layers can be electrically connected to each other. On the other hand, it is known that the core plate made of Βτ resin is often unable to withstand the asymmetry stress caused by the build-up structure or the difference in thermal expansion coefficient due to insufficient hardness, and the substrate bending occurs, and if the circuit layout is to be increased, 20 must increase the number of layers of the build-up structure, which will inevitably increase the thickness of the package substrate; however, the material used in the present invention is a gasification with a higher hardness as the base j, because the bending of the substrate can be reduced, and further The finished product yield and the sinfulness are increased, and the thickness of the aluminum alloy substrate embedded with the circuit layer and the dielectric 9 1355725 and having a high line layout are laminated on each other to reduce the thickness. Has a higher electrical function. [Embodiment] The following is a description of the specifics of the present invention by the specific embodiments of the present invention. The present invention can also be rided or assisted by other different, poor, and the details of the (4) book towel are also in the embodiment of the present invention without departing from the spirit of the present invention. The drawings are simplified schematic diagrams. However, the specific drawing only shows the components related to the present invention, and the components shown therein are not in actual implementation, and the number of components, the shape and the like in actual implementation are a selective design, and the component layout thereof. The pattern may be more complicated. Embodiment 1% Referring to Figures 2A to 2N, there is shown a schematic cross-sectional view of a process for producing an alumina substrate of the present invention. First, as shown in Fig. 2A, an aluminum layer 21 is provided which has a first surface 21a and an opposite second surface 2lb. Next, as shown in FIG. 2B, a first resist layer 22 is formed on the first surface 21a of the inscription layer 21 to protect the first surface 21a. The manner in which the first resist layer 22 is formed can be formed by laminating a dry film or applying a liquid photoresist. 1355725 As shown in Fig. 2C, the second surface 21b of the aluminum layer 21 not protected by the first resist layer 22 is oxidized by anodization to form an aluminum oxide layer 23 on the second surface 21b. Then, as shown in Fig. 2D, a patterned second resist layer 24 is formed on the surface of the oxidized layer 23. The patterned second resist layer 24 is formed by forming a resist layer by laminating a dry film or coating a liquid photoresist, and then forming a patterned first resist layer 24 by exposure and development. Next, as shown in Fig. 2E, the aluminum oxide layer 23 has a plurality of first opening regions 23 1 to expose a portion of the aluminum layer 21 by patterning the aluminum oxide layer 23'. The etching method in this embodiment may be plasma etching, chemical etching, or electrodissolution, or the like, to pattern the aluminum oxide layer 23. Then, as shown in Fig. 2F, the first resist layer 22 and the second resist layer 24 are removed. The manner of stripping may depend on the materials of the first resist layer 22 and the second resist layer 24.
而選擇使用物理性移除或化學性溶除之方式。再參考圖2G 所示，形成一第三阻層26於鋁層21之第一表面21a，形成此 15第三阻層26之方式，可透過壓合乾膜或塗佈液態光阻形成 阻層，並顯露鋁層21之周緣的部分第一表面21a(圖中未 不）。接著’如圖2H所示，利用該鋁層21顯露之部分第三阻 層26所顯露之部分鋁層21導通電流，進行電鍍，形成一第 線路層27於第—開口區231中。其中，第一線路層27與氧 20化紹層23之表面齊平。另外，第一線路層27之材質可選自 銅錫錄、鉻、欽、銅鉻合金、以及錫錯合金所知士、 群組其中之一者。 所組成 如圖21所示，剝除第三阻層26。剝除第三阻層26之方 式可類似前述移除第一阻層22及第二阻層24之方式。接 11 1355725 著，如圖2J所示，蝕刻移除鋁層21。至此，得到一種氧化 鋁基板40。此種氧化鋁基板40包括一氧化鋁層23、以及一 第一線路層27。其中，氧化鋁層23具有複數第一開口區 231，且第一開口區231貫穿氧化鋁層23，而第一線路層27 5 配置並嵌入氧化鋁層23之第一開口區231中，並且第一線路 層27係齊平於氧化鋁層23相對兩表面。 實施例2 參考圖3A至3F，其為製作本發明疊層氧化鋁基板之流 10 程示意剖視圖。 參照圖3A所示，先提供複數氧化鋁基板40。這些氧化 鋁基板40係如實施例1圖2J所示，其分別包括一氧化鋁層 23、以及一第一線路層27，其中，氧化鋁層23具有複數貫 穿之第一開口區231，而第一線路層27係配置並嵌埋於開口 15 區231中，且第一線路層27係齊平於氧化鋁層23相對兩表 面。並且，置放一介電層41於兩氧化鋁基板40之間，此介 電層41之材質可使用感光或非感光有機材料，例如ABF (Ajinomoto Build-up Film )、聯二苯環 丁二烯 (benzocylobutene，BCB )、液晶聚合物（liquid crystal 20 polymer，LCP )、聚亞醢胺（polyimide，PI )、聚乙烯醚 (poly ( phenylene ether ) ，PPE )、聚四默乙浠（poly (tetra-fluoroethylene ) ，PTFE) 、FR4、FR5、雙順丁醯 二酸醯亞胺/三氮拼（bismaleimide triazine，BT )、芳香尼 龍（aramide)、或環氧樹脂與玻璃纖維之混合物。 12 1355725 如圖3B所示，將這些氧化鋁基板40與介電層41相互壓 合，使得介電層41完全填滿兩氧化鋁基板40之間，使該些 氧化鋁基板上下疊層，以形成一疊層氧化鋁基板。後續可 進行下列步驟。例如，利用機械鑽孔，鑽設通孔42貫穿該 5 疊層氧化紹基板。 而後，如圖3C所示，透過物理如蒸鍍或濺鍍或化學方 式，於該該疊層氧化鋁基板之兩側表面及其通孔42内表面 形成一晶種層43。 參考圖3D’透過塗佈或壓合*配合圖案化技術如曝光 10 顯影、雷射蝕孔、機械鑕孔等，形成一圖案化之第四阻層 44，此第四阻層44係具有複數開口區44卜對應疊層氧化鋁 基板表面之第一線路層27及通孔42，並顯露出部份晶種層 43 ° 再參考圖3E，利用晶種層43,導通電流進行電鍍製程， 15 形成第二線路層45，並於通孔42内形成一電鍍導通孔48貫 穿該疊層氧化鋁基板，並導通各該第一線路層27。 再參照圖3F所示，利用填孔技術將導電通孔中填充有 樹脂46 (如環氧樹脂），並且移除第四阻層44及為該第四 阻層44所覆蓋之晶種層43，再形成一防焊層47覆蓋疊層氧 2〇 化鋁基板的表面，且此防焊層47具有開孔472顯露部分第二 線路層45以作為電性連接墊455。 如此，便可得到本發明之疊層氧化鋁基板，其包含複 數氧化鋁基板40，其分別具有一氧化鋁層23、以及一第一 線路層27，其中，該氧化鋁層23具有複數貫穿之開口區 13 1355725 231而该第一線路層27係配置並嵌埋於該開口區23丨中， 且該第一線路層27係齊平於該氧化鋁層23相對兩表面；以 及複數介電層41，其中各該介電層41係設置於各該氧化銘 基板40之間使該些氧化銘基板4〇上下疊層。 5 該疊層氧化銘基板復可包括一電錢導通孔48貫穿該疊 層氧化鋁基板，而此導電通孔電性連接第一線路層27。另 外，第二線路層45形成於疊層氧化鉑基板表面，並直接電 性連接第一線路層43。而疊層氧化鋁基板表面覆蓋有一防 焊層47，此防焊層47具有複數開孔472顯露部分第二線路層 10 45以作為電性連接塾455。 實施例3 參考圖4A至4F，其為製作本發明疊層氧化鋁基板之流 程示意剖視圖。本實施例類似實施例2所述，同樣皆使用氧 15 化紹基板4〇與介電層41疊層進行壓合。不過，本實施例不 同於實施例2的地方，在於氧化鋁基板4〇之兩側係分別設置 一介電層41’此介電層41之材質可使用上述實施例丨所述之 材質。而後’將這些氧化鋁基板40與介電層41相互壓合， 使付兩氧化链基板40之間的介電層41能完全填滿兩氧化銘 20 基板40間的間隙，以形成一疊層氧化鋁基板。 後續的步驟，同樣類似於實施例2所述。例如，利用機 械鑽孔，鑽設通孔42貫穿該些氧化鋁基板40及介電層41。 並且’如圖4C所示，於疊層氧化鋁基板兩侧表面之介電層 41對應第一線路層27的部份位置，開設有盲孔417,此係依 25 據介電層41之材質，利用曝光顯影、雷射蝕孔或機械鎖孔 1355725 的方式形成。接續透過物理如蒸鍍或濺鍍或化學方式，於 疊層氧化鋁基板表面及其通孔42内表面形成一晶種層43。 後續參考圖4D至4F，大致上同於實施例2 ,進行電鍍製程， 於通孔42内形成一電鍍導通孔48貫穿該些氧化鋁基板4〇及 5介電層41，其中，該導電通孔48係電性連接該些氧化鋁基 板4〇之第一線路層27,並於盲孔417内填入金屬層形成導電 盲孔418，並形成第二線路層45於介電層41之表面，該第二 線路層45係藉由導電盲孔418電性連接至第一線路層27，再 使用樹脂46填充電鍍導通孔48，並形成防焊層47。 10 如此’便可得到本實施例之疊層氧化鋁基板，其包含 複數氧化鋁基板40，其分別具有一氧化鋁層23、以及一第 一線路層27 ’其中，該氧化鋁層23具有複數貫穿之開口區 231，而該第一線路層27係配置並嵌埋於該開口區231中， 且該第一線路層27係齊平於該氧化鋁層23相對兩表面；以 15及複數介電層41，其中各該氧化鋁基板40之兩側係具有一 介電層41，使該些氧化鋁基板4〇上下疊層。 該疊層氧化鋁基板復具有一電鍍導通孔48貫穿該些氧 化紹基板40及介電層41，而此導電通孔銘電性連接第一線 路層27。另外，第二線路層45係配置於壓合在疊層氧化鋁 20基板兩側之介電層41表面，並藉由介電層41中之導電盲孔 4is電性連接第二線路層μ及第—線路層η。而疊層氧化铭 基板表面覆蓋有—防焊層47,此防焊層47具有複數開孔472 顯露邛分第二線路層45以作為電性連接墊455。 15 综上所述’本發明使用具優良熱與機械特性之氧化铭 做為基板，因此若需進行習知機械鑽孔加工製作時，其通 孔可由一般之ΙΟΟμϊη等級到10μιη等級，有利於細微化佈 線’從而提高覆晶基板之佈線密度，不會如同習知ΒΤ樹脂 為材質之核心板，因材質限制而造成製作之孔洞直徑無法 低於50 μιη以下，而難以形成更小的孔徑，無法達到更高佈 線密度之缺失。另一方面，本發明製作氧化鋁基板之過程 中，亦利用鋁層、氧化鋁層及非鋁金屬層（如銅）三者不 同之蝕刻選擇性，而於蝕刻過程中僅會使上述其中之一受 到蝕刻，而可進行線路製程，並製得細線路結構，亦可視 所需，將複數氧化鋁基板與介電層進行疊層壓合，以增加 線路佈局，並減少整體封裝基板之厚度，符合輕薄短^之 趨勢。 另外，由於習知以ΒΤ樹脂為材質之核心板常因硬度不 足，而無法承受增層結構或熱膨脹係數差所產生之不對稱 應力’所會發生基板彎曲情形。然而本發明所使用之材質 為硬度較高之氧化純為基板，因此可減少上述基板弯曲 ，形，進而使成品良率及可靠度提高，亦具細微化佈線容 :、尺寸穩定性高等優點。並且，透過使用上述氧化紹基 板與介電層進行疊層壓合所形錢疊層氧化㈣板，其内 線路饰局之密度⑤且厚度薄，同樣可達^上述之優點。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以巾料利_所述 於上述實施你丨。 1355725 44 第四阻層 441 開口區 45 第二線路層 455 電性連接墊 46 樹脂 47, 14 防焊層 472 開孔 48 電鍍導通孔Instead, use physical removal or chemical dissolution. Referring to FIG. 2G, a third resist layer 26 is formed on the first surface 21a of the aluminum layer 21, and the 15th resist layer 26 is formed. The resistive layer can be formed by pressing the dry film or coating the liquid photoresist. And a portion of the first surface 21a of the periphery of the aluminum layer 21 is exposed (not shown). Then, as shown in Fig. 2H, a portion of the aluminum layer 21 exposed by the portion of the third resist layer 26 exposed by the aluminum layer 21 is turned on to perform electroplating to form a first wiring layer 27 in the first opening region 231. The first circuit layer 27 is flush with the surface of the oxygen layer. In addition, the material of the first circuit layer 27 may be selected from the group consisting of copper tin, chromium, chin, copper chrome, and tin alloy. Composition As shown in Fig. 21, the third resist layer 26 is stripped. The manner of stripping the third resist layer 26 may be similar to the manner of removing the first resist layer 22 and the second resist layer 24 as described above. Referring to 11 1355725, as shown in FIG. 2J, the aluminum layer 21 is removed by etching. Thus far, an aluminum oxide substrate 40 is obtained. The alumina substrate 40 includes an aluminum oxide layer 23 and a first wiring layer 27. The aluminum oxide layer 23 has a plurality of first open regions 231, and the first open region 231 penetrates the aluminum oxide layer 23, and the first circuit layer 27 5 is disposed and embedded in the first open region 231 of the aluminum oxide layer 23, and A wiring layer 27 is flush with the opposite surfaces of the aluminum oxide layer 23. Embodiment 2 Referring to Figures 3A to 3F, there are shown schematic cross-sectional views of a flow of a laminated alumina substrate of the present invention. Referring to FIG. 3A, a plurality of alumina substrates 40 are first provided. The aluminum oxide substrate 40 is as shown in FIG. 2J of the first embodiment, and includes an aluminum oxide layer 23 and a first wiring layer 27, wherein the aluminum oxide layer 23 has a plurality of first opening regions 231 penetrating through the first opening region 231. A wiring layer 27 is disposed and embedded in the opening 15 region 231, and the first wiring layer 27 is flush with the opposite surfaces of the aluminum oxide layer 23. Moreover, a dielectric layer 41 is disposed between the two aluminum oxide substrates 40. The material of the dielectric layer 41 can be a photosensitive or non-photosensitive organic material, such as ABF (Ajinomoto Build-up Film), biphenyl butyl hydride. Benzocylobutene (BCB), liquid crystal 20 polymer (LCP), polyimide (PI), poly(phenylene ether), PPE, polytetrazole (poly) Tetra-fluoroethylene ) , PTFE 4 , FR 4 , FR 5 , bismaleimide triazine (BT ), aramide, or a mixture of epoxy resin and glass fiber. 12 1355725 As shown in FIG. 3B, the aluminum oxide substrate 40 and the dielectric layer 41 are pressed together, so that the dielectric layer 41 completely fills the gap between the two alumina substrates 40, and the alumina substrates are stacked one on top of the other. A laminated alumina substrate is formed. The following steps can be followed. For example, by mechanical drilling, a through hole 42 is drilled through the 5 laminated oxide substrate. Then, as shown in Fig. 3C, a seed layer 43 is formed on both side surfaces of the laminated alumina substrate and the inner surface of the through hole 42 by physical deposition such as evaporation or sputtering or chemical method. Referring to FIG. 3D', through a coating or press-fitting patterning technique such as exposure 10 development, laser etching, mechanical boring, etc., a patterned fourth resist layer 44 is formed, the fourth resist layer 44 having a plurality The opening area 44 corresponds to the first circuit layer 27 and the via hole 42 on the surface of the laminated alumina substrate, and a part of the seed layer 43 is exposed. Referring to FIG. 3E, the seed layer 43 is used to conduct current to perform the electroplating process. A second wiring layer 45 is formed, and a plating via 48 is formed in the via hole 42 to penetrate the laminated alumina substrate, and each of the first wiring layers 27 is turned on. Referring again to FIG. 3F, the conductive via is filled with a resin 46 (such as an epoxy resin) by a hole filling technique, and the fourth resist layer 44 and the seed layer 43 covered by the fourth resist layer 44 are removed. A solder resist layer 47 is further formed to cover the surface of the laminated oxygen aluminum oxide substrate, and the solder resist layer 47 has an opening 472 to expose a portion of the second wiring layer 45 as the electrical connection pad 455. Thus, the laminated alumina substrate of the present invention can be obtained, which comprises a plurality of alumina substrates 40 each having an aluminum oxide layer 23 and a first wiring layer 27, wherein the aluminum oxide layer 23 has a plurality of through layers. An open area 13 1355725 231 and the first circuit layer 27 is disposed and embedded in the open area 23 , and the first circuit layer 27 is flush with the opposite surfaces of the aluminum oxide layer 23 ; and a plurality of dielectric layers 41, wherein each of the dielectric layers 41 is disposed between each of the oxidized substrate 40 such that the oxidized substrate 4 is stacked on top of each other. The laminated oxide substrate may include a battery via 48 extending through the stacked aluminum substrate, and the conductive via is electrically connected to the first wiring layer 27. Further, the second wiring layer 45 is formed on the surface of the laminated platinum oxide substrate, and is directly electrically connected to the first wiring layer 43. The surface of the laminated alumina substrate is covered with a solder resist layer 47 having a plurality of openings 472 to expose a portion of the second wiring layer 10 45 as an electrical connection port 455. Embodiment 3 Referring to Figures 4A to 4F, there are shown schematic flow cross-sectional views of a laminated alumina substrate of the present invention. This embodiment is similar to the embodiment 2, and the same is used for lamination of the substrate 4 and the dielectric layer 41. However, the present embodiment is different from the embodiment 2 in that a dielectric layer 41' is disposed on both sides of the alumina substrate 4, and the material of the dielectric layer 41 can be made of the material described in the above embodiment. Then, the alumina substrate 40 and the dielectric layer 41 are pressed together, so that the dielectric layer 41 between the two oxidized chain substrates 40 can completely fill the gap between the oxidized 20 substrates 40 to form a laminate. Alumina substrate. Subsequent steps are also similar to those described in Example 2. For example, through the mechanical drilling, the through holes 42 are drilled through the alumina substrate 40 and the dielectric layer 41. And as shown in FIG. 4C, in a portion of the dielectric layer 41 on both sides of the laminated alumina substrate corresponding to the first circuit layer 27, a blind hole 417 is opened, which is based on the material of the dielectric layer 41. , formed by exposure development, laser etch holes or mechanical keyhole 1355725. A seed layer 43 is formed on the surface of the laminated alumina substrate and the inner surface of the through hole 42 by physical deposition such as evaporation or sputtering or chemical. Referring to FIG. 4D to FIG. 4F, substantially the same as the second embodiment, an electroplating process is performed, and a plating via 48 is formed in the via hole 42 to penetrate the aluminum substrate 4 and the dielectric layer 41. The hole 48 is electrically connected to the first circuit layer 27 of the aluminum oxide substrate 4, and the metal hole is filled in the blind hole 417 to form the conductive blind hole 418, and the second circuit layer 45 is formed on the surface of the dielectric layer 41. The second circuit layer 45 is electrically connected to the first wiring layer 27 through the conductive blind vias 418, and the plating vias 48 are filled with the resin 46, and the solder resist layer 47 is formed. 10 Thus, the laminated alumina substrate of the present embodiment can be obtained, which comprises a plurality of alumina substrates 40 each having an aluminum oxide layer 23 and a first wiring layer 27', wherein the aluminum oxide layer 23 has a plurality The first circuit layer 27 is disposed and embedded in the opening region 231, and the first circuit layer 27 is flush with the opposite surfaces of the aluminum oxide layer 23; The electric layer 41 has a dielectric layer 41 on both sides of the alumina substrate 40, and the alumina substrates 4 are stacked on top of each other. The laminated alumina substrate has a plated via 48 extending through the oxidized substrate 40 and the dielectric layer 41, and the conductive via is electrically connected to the first wiring layer 27. In addition, the second circuit layer 45 is disposed on the surface of the dielectric layer 41 which is pressed on both sides of the substrate of the laminated alumina 20, and is electrically connected to the second circuit layer μ by the conductive via 4is in the dielectric layer 41. The first line layer η. The surface of the laminated oxide substrate is covered with a solder resist layer 47 having a plurality of openings 472 for revealing the second wiring layer 45 as the electrical connection pads 455. 15 In summary, the present invention uses an oxidized etch with excellent thermal and mechanical properties as a substrate. Therefore, if a conventional mechanical drilling process is required, the through hole can be graded from a general ΙΟΟμϊη level to a 10μιη level, which is advantageous for subtle The wiring is adjusted to increase the wiring density of the flip-chip substrate, and it is not like the core plate of the conventional resin. The diameter of the hole to be fabricated cannot be less than 50 μm due to material limitation, and it is difficult to form a smaller aperture. Achieve the lack of higher wiring density. On the other hand, in the process of fabricating the alumina substrate of the present invention, the etching selectivity of the aluminum layer, the aluminum oxide layer and the non-aluminum metal layer (such as copper) is also utilized, and only the above-mentioned ones are used in the etching process. Once etched, the circuit process can be performed, and a fine circuit structure can be obtained. The plurality of aluminum oxide substrates can be laminated and laminated with the dielectric layer as needed to increase the layout of the circuit and reduce the thickness of the entire package substrate. The trend of thin and light ^. In addition, since the core plate made of tantalum resin is often insufficient in hardness and cannot withstand the asymmetric stress caused by the build-up structure or the difference in thermal expansion coefficient, the substrate is bent. However, the material used in the present invention is a substrate having a high hardness and a pure oxidized substrate, thereby reducing the bending and shape of the substrate, thereby improving the yield and reliability of the finished product, and also having the advantages of fine wiring capacity and high dimensional stability. Further, by using the above-mentioned oxide substrate and the dielectric layer for lamination and lamination, the density of the printed wiring (4) plate has a density of 5 and a thin thickness, which is also advantageous. The above-described embodiments are merely exemplified for convenience of explanation, and the scope of the claims of the present invention is intended to be implemented as described above. 1355725 44 Fourth resistive layer 441 Open area 45 Second wiring layer 455 Electrical connection pad 46 Resin 47, 14 Solder mask 472 Opening 48 Plating via
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