200950037 ^ . to ”/3 說明· 【發明所屬之技術領域】 ' 本發明係有關於一種半導體裝置及其製法，尤指一種 -嵌埋半導體晶片之封裝基板及其製法。 ^【先前技術】 隨著半導體封裝技術的演進’除了傳統打線式（w丨 bonding)及覆晶式（Flip chip)半導體封裝技術以外，目 W半導體裝置（Semiconductor device)已開發出不同的 ❺封裝型態，例如直接在一封裝基板（packaging substr^e) 中嵌埋並電性整合一係如具有積體電路之半導體晶片此 種半導體裝置可縮減整體體積並提昇電性功能，遂成為一 種封裝的主流。 呀參閱第1A至1 D圖，係為習知嵌埋半導體晶片之封 裝基板之製法示意圖，其中第1A，圖係為第1A圖之上視 示意圖。 如第1A及1A，圖所示，首先提供一第一承載板u， Ο該第y承載板11具有相對之第一表面Ua及第二表面 lib，並於該第一承載板丨丨形成至少一貫穿該第一及第二 表面lla，llb之矩形開口 11〇，同時提供一第二承載板 12，並將其接合於第一承載板u之第二表面丨比上。 曰如第1B圖所示，接著提供一半導體晶片13，該半導 體晶片13具有相對之作用面13a及非作用面13b，於該 作用面13a上具有複數電極塾13卜且藉由一黏著層η 將該半導體晶之非仙面13b固定於矩形開口 11〇 Π0856 5 200950037 丫日v矛—承載板12上。 , 如第1(:圖所示，然後於該第一承载板11及半導體晶 片13之作用面13a上熱壓形成介電層15，且該介電層15 -亦填入矩形開口 Π0與半導體晶片13之間的間隙中。 如第1D圖所示，最後於介電層15上形成線路層 且於介電層15中形成導電盲孔161，以電性連接半導體 晶片13之電極墊131。 惟，前述習知技術中，由於半導體晶片13與矩形開 ❹口 no的邊緣之間必須預留間隙，在該介電層15進^二 壓％因為壓力或產生氣泡等因素，易使該半導體晶片 13於該矩形開口 11〇中偏移e，而此偏移6會造成導=盲 孔161連接電極墊131之對位偏差，甚至因偏差過大而無 法有效電性連接電極墊13丨。 …、 、因此，鑒於上述之問題，如何避免習知技術中將介 層以熱璧形成在半導體晶片及第一承载板上時，容易導致 半導體晶片偏移’產生該導電盲孔與該半導體晶片之對位 偏差，甚至因偏移過大而無法有效電性連接，造成產品 廢’降低製程良率，實已成為目前亟欲解決的課題。 【發明内容】 馨於上述習知技術之缺失，本發明之一目的係提供一 種嵌埋半導體晶片之封裂基板及其製法， 片之定位狀態。 什千導體曰曰 110856 6 200950037 ::上述目的及其它目的’本發明 ，一片之封裝基板之製法，係包括 ：¥ 其具有相對之第一表面、第 =第-承載板， -板Γ顺形成連通開口之填塞孔-該 一弟承載板第二表面結合一第_ 片，並置於第U弟—承载板；提供一半導體晶 之作用面及對應位於開口中’其具有相對 ®φ R„ 上具有電極墊；以及將 千置於填基孔巾及開口巾，則 再提供另一種嵌埋丰I邮日μ罪千導體曰日片 ®包括.接祖⑨日片之封裝基板之製法，係 結合一第二承載板;提供一半導體:第片一 3板f二表面 =上且對應位於開口中，而與開 = 有相對之作用面及非作用面^ m杨，且其具 及將面6亥作用面上具有電極墊；以 及將固又於間隙中，以抵靠半導體晶片。 於刖述之製法φ + ©第-及第二承載板係可為：：體晶片為基本需求’該 板、介電層或金屬板，且;第t ^路之核心板、多層線路 承载板係可藉由第-黏著層結合第一承載板之第 一表面，而該半導·§#曰弟 結合於第二承载板或Μ第一黏著作声用上面則可藉由第二黏著層 :前=製法中’以固定件抵靠半導體晶片為基本需 …' P具有固疋形狀，若為樹脂混合填 110856 7 200950037^... ^ ^ -凡州，π路错由低溫加熱而具有固定形狀；且該固定件係 可為柱狀、球狀、錐狀或不規則立體狀，並無特定限制。 • 於前述之製法中，該開口係可呈曲線組合任意形、圓 形或橢圓形；當然，該開口之形狀亦可呈方形、矩形或多 邊形’以使該第-承载板係可具有連通開σ邊緣及角落之 複數個填塞孔。 此外，則述之製法復可包括於該第一承載板之第一表 面及該半導體晶片之作用面上形成增層結構，係包括至少 ❹介電層、形成於介電層上之線路層、形成於介電層中且 電性連接線路層及電極塾 之-性接銀孰η 及設於增層結構上 =接觸墊4於增層結構上設有防焊層，並形成開 虚半導體曰月之門接觸塾其中’該介電層可填入開口 ::片之間，以強化固定半導體晶片於開口中。 基板，^ = 作—種嵌埋半導體晶片之封裝 二表面、貫穿兮第触’係具有相對之第—表面及第 貝穿該第一及第二表面之開口 。填塞孔;半導禮晶片，係容 =:: 用面及非作用面’且該作用面具 ==作 係固設於填塞孔及開口中，以抵靠及固疋件， 依前述之製法，亦可製作s #山等篮曰曰片 裝基板，係包括H = 7㈣料導體晶片之封 第二表面、貫穿4 具有相對之第-表面及 貝芽。亥第一及第二表面之. 係容置於開口中且與開口之’：片， 用面及非作用面，且該 1隙其具有相對之作 乍用面具有琶極墊；以及固定件， 110856 8 200950037 -贫'凹5又《間隙，以抵靠半導體晶片。 . 於前述之封裝基板中’以嵌埋半導體晶片為基本需 求’該第一承载板係可為具雙面線路之核心板、多層線路 •板、介電層、或金屬板。 - 於前述之封裝基板中，以固定件抵靠半導體晶片為基 本需求’該固定件之材料若為樹脂、金屬、陶瓷、有機材 質或固化膠質，其無需加熱即具有固定形狀，若為樹脂混 真充;=1]則其需藉由低溫加熱而具有固定形狀；且該固 ©定件係可為柱狀、球狀、錐狀或不規則立體狀，並盔特定 限制。 、 於鈿述之封裝基板中，該開口係可呈曲線組合任意 形、圓形或橢圓形；當然，該開口之形狀亦可呈方形、矩 升夕邊形，以使該第一承載板係可具有連通開口邊緣及 角落之複數個填塞孔。 於前述之封裝基板中，以嵌埋半導體晶片為基本需 求復可包括設於第一承載板之第二表面及半導體晶片之 第一承載板，其係可為絕緣板、具雙面線路之核心板多 路板、介電層、或金屬板。又，該第二承載板係可藉 黏著層結合第一承載板之第二表面，而該半導體晶 之非作用面則可藉由第二黏著層結合於第二承載板或 第一黏著層上。 此外，前述之封裝基板復可包括設於該第一承載板之 f面及該半導體晶片之作用面上之增層結構，其可包 至少一介電層、設於介電層上之線路層、設於介電層中 110856 9 200950037 儿▼电，江逆接線路層及電極塾 上之電性接鈣瓿 之導包目孔、及設於增層結構 孔，以顯露電性接_。 ；層’並具有開 :導體晶片之間。 ”中4介電層可填人開口與半 - 本發明嵌埋半導體晶片之封梦其也甘制+ 由固定件之設計，t半導 ^板及—法，主要藉 與開口之間具有間；：二於開口時，半導體晶片 曰y ”將固疋件设於間隙中以抵靠半導體 日日片，可避免半導體曰_ 導體 较. 曰曰片％外力影響而於開口内產生偏 <’：達到確保半導體晶片之定位狀態之目的， 率之目的。 連接位置不佳，以達到提昇電性良 【實施方式】 2下藉由特冑白勺具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由太^日曰舍 Μ ^之只施方 a* ^ , ^ n 了由本5兒明書所揭示之内容輕易地 瞭解本發明之其他優點及功效。 d封心以至2D圖’係為本發明後埋半導體晶片之 ©封裝基板的製法之示意圖。 如f 2A及2A圖所不，其中第2A，圖係為第2a圖之 視不思圖；首先，提供—第—承餘2卜其且有相對 之第一表面21a及笫二矣而91h、…a …、有相對 弟表面21b，亚形成至少一貫穿第一 表面21a及第二表面21b之矩形開口 2iq;又該開口训 之形狀亦可呈方形或多邊形等有稜角之輪廓，並不限於上 述。 孔 210a 再於開口 21〇之四個邊緣（side)e成填塞 110856 10 200950037 、叩四调哄塞孔21〇a均連通開口 21 位# 且其輪廓係為弧形。 第：第一承載板21之第二表面21b上塗覆- 、第IS:合一第二承載板22;於本實施例中， * :弟―黏者層24並未附著於開口⑽中之第二 ^ 所述之第—承載板21及第二承載板&均為具雙面線 路之核心板、多層線路板、介電声、” ^ 承載板22亦可為絕緣板。缺，曰於山反且該第一 ^ . , _ ., …、有關於嵌埋半導體晶片所 ❹用之封衣基板之種類繁多，惟乃業界所周知，且盆 技術特徵，故不再贅述，特此述明。 ，、卜本尔 之作圖所示，提供一半導體晶片23，其具有相對 數雷托轨州 作用面咖上具有複 電㈣231，將該半導體晶片23置於開口 21〇中，且 =導體晶片23之非作用面23b藉由第二點著層25結合 载板22上’以使該半導體晶片23之非作用面 23b與第一承載板21之第二表面2比同側。 如第2C及2C，圖所示，其中第2C，圖係為第％圖之 視不意亦於填塞孔21〇a中置入固定件26，且該固定 26對應填塞孔21Ga之輪廟而呈圓柱狀並凸出至開口 21〇,以便使該固定件26抵靠在該半導體晶片23之四個 側邊，雖然該開口 210與半導體晶片23之間具有間隙d， 使該半，體晶片23易受後續製程之外力遷合而產生偏 移，但藉由該固定件26先抵靠在該半導體晶片23之側 邊，而有效加強半導體晶片23於開口 21〇中之定位能力， π 110856 200950037 •付从避兄習知技術中偏移現象 之發生 如第2D圖所示，於該第一承载板21之第-表面2la _及半導體晶片23之作用面23a上形成增層結構& ，戶斤述之增層結構27係包括至少—介電層271、 -於介電層m上之線路層m、及複數形成於介電層⑺ 中且電性連接線路層272之導雨亡力97Q ^ . 電盲孔273a電性連接半導體/目 ^埶部份之導 牧干日日片23之電極墊231。且辩 外層W2%具有複數電性接觸^ ❹：且有：Γ構27上形成有防…^ 開孔28G，以對應顯露各該電性接觸塾274。 增層結構27最内層之部份介電層27 開口 210與半導體sy00 具入 所-、⑮ 曰曰片23之間的間隙d中（如第2C，圖 所不），以將該半導體晶片23強化固定於該開口 21〇中圖 於本實施例中’亦可於㈣—承載板2卜第二 承载板22及增層結構27中 二 於導電通m__M，im(pTH)，而關 ❹其非本案技術特徵，二技術乃業界所周知，又 故未圖不且不再詳述，特此述明。 冉者’睛參閱第2D，圖，#盔筮^ „ 實施態樣；如圖所亍，j 為弟一黏者層24的另- 板22上及對庫於門、以弟一黏著層24形成於第二承載 半導體晶片23藉由第1菩居9ς—承載板22上，使得該 於開口 _中^ 5將其非作用面23b結合 ζιυ中的弟—黏著層24上。 設二Sr?’本發明係藉由該固定件26置入 2U)之四個側邊的填塞孔2i〇a，以抵靠設於 110856 12 200950037 -成叩p。10中之半導體晶片23側邊，使該固定件2β與半 .導體晶片23相互緊配合以產生定位效果，·相較於習^技 術，本發明藉由固定# 26之設置，得以避免後續製程之 ,=電層271a熱壓合於第一承載板21及半導體晶片㈡上 時，半導體晶片23產生偏移，而影響導電盲孔273a電性 連接電極塾231之現象發生。 請參閱第3圖，係為本實施例之另一實施態樣，其差 異僅在於填塞孔2l〇a之位置及數量，其餘相關製程與結 ❹構均相同，因此不再重複說明相同部份 下僅說明其相減，料㈣ (snle)設有兩個填塞孔21〇a，且於四個角落（c〇ner)亦形 成填塞孔21〇a’使得該固定件26設於填塞孔21〇&之後， 因該固定件26的數量及半導體晶片23周圍抵靠力的提 升，而得以增強半導體晶片23於開口 21〇中之定位能力。 請一併參閱第4A至4E圖，所述之固定件26係由樹 脂、金屬、陶瓷、固化膠質或有機材質所組成，其無需加 ❹熱即具有固定形狀，而其結構為柱狀、球狀、錐狀或不規 則立體狀（如第4E圖所示），以使該固定件26置入填塞 孔21 Oa中有效產生抵靠效果。然，於其他實施例中該 口疋件26可由樹脂混合填充劑所組成，但其需藉由低溫 加熱以具有所需之固定形狀。 依上述製法，本發明得以提供一種嵌埋半導體晶片之 封裝基板，係包括：第一承载板21、半導體晶片23以及 固定件26。 110856 13 200950037 Γ；1地之第一承載板21具有相對之第一表面21a及第 •二表面21b、至少一貫穿第一表面21a及第二表面2lb之 _開口 210 '及連通開口 210之填塞孔2l〇a。 所述之半導體晶片23設於開口 210中，且具有相對 '之作用面23a及非作用面23b,該作用面23a上具有複數 電極墊231。 首所述之固定件26設於填塞孔2l0a中，以抵靠固定半 導體晶片23，而使半導體晶片23定位於開口 21〇中。200950037 ^ . to ”/3 Description· [Technical Field of the Invention] The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a package substrate in which a semiconductor wafer is embedded and a method of fabricating the same. The evolution of semiconductor packaging technology 'In addition to the traditional wire-wound and flip-chip semiconductor packaging technology, the semiconductor device has developed different package types, such as directly A package substrate (embedded substr^e) is embedded and electrically integrated into a semiconductor wafer such as an integrated circuit. Such a semiconductor device can reduce the overall volume and enhance electrical functions, and becomes a mainstream of packaging. 1A to 1D are schematic diagrams of a conventional method for embedding a package substrate of a semiconductor wafer, wherein FIG. 1A is a top view of FIG. 1A. As shown in FIGS. 1A and 1A, a first a carrier board u, the first y-carrier board 11 has a first surface Ua and a second surface lib opposite to each other, and forms at least one through the first and the first board a rectangular opening 11 of the two surfaces 11a, 11b, while providing a second carrier 12 and bonding it to the second surface ratio of the first carrier u. As shown in FIG. 1B, a semiconductor is provided. The wafer 13 has a facing surface 13a and an inactive surface 13b. The active surface 13a has a plurality of electrodes 13b and the non-fairy surface 13b of the semiconductor crystal is fixed to the rectangle by an adhesive layer η. Opening 11〇Π0856 5 200950037 丫日v spear-bearing plate 12, as shown in Fig. 1 (Fig., then heat-pressing the dielectric layer 15 on the first carrier plate 11 and the active surface 13a of the semiconductor wafer 13 And the dielectric layer 15 - is also filled in the gap between the rectangular opening Π 0 and the semiconductor wafer 13. As shown in FIG. 1D, a wiring layer is finally formed on the dielectric layer 15 and a conductive layer is formed in the dielectric layer 15. The blind hole 161 is electrically connected to the electrode pad 131 of the semiconductor wafer 13. However, in the prior art, since a gap must be reserved between the edge of the semiconductor wafer 13 and the rectangular opening no, the dielectric layer 15 is advanced. ^Two pressure % because of pressure or bubble generation, etc. The conductor chip 13 is offset by e in the rectangular opening 11 ,, and the offset 6 causes the alignment of the conductive hole 161 to be connected to the electrode pad 131, and the electrode pad 13 无法 cannot be electrically connected even if the deviation is too large. In view of the above problems, how to avoid the prior art when the dielectric layer is formed on the semiconductor wafer and the first carrier by enthalpy, the semiconductor wafer is easily offset to generate the conductive blind via and the semiconductor wafer. The deviation of the alignment, even if the offset is too large, can not be effectively connected electrically, resulting in product waste 'lowering process yield, which has become a problem that is currently being solved. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, it is an object of the present invention to provide a sealed substrate in which a semiconductor wafer is embedded, a method of manufacturing the same, and a state in which the sheet is positioned.千千导体曰曰110856 6 200950037 ::The above object and other objects' The present invention, a method for manufacturing a package substrate, includes: ¥ has a first surface, a first - carrier plate, - a plate is formed a filling hole of the communication opening - the second surface of the first carrier plate is bonded to a first piece and placed on the U-bearing plate; the surface of the semiconductor crystal is provided and correspondingly located in the opening, which has a relative orientation of φ φ Having an electrode pad; and placing a thousand in the base hole and the opening towel, and then providing another method of encapsulating the substrate, including the package substrate of the 9th piece of the ancestor Combining a second carrier plate; providing a semiconductor: the first plate 3 plate f two surface = upper and correspondingly located in the opening, and the opening = opposite active surface and non-active surface ^ m Yang, and its facing The 6-well action surface has an electrode pad; and the solid surface is placed in the gap to abut the semiconductor wafer. The method of φ + ©-the first and second carrier plates can be: the body wafer is a basic requirement' a board, a dielectric layer or a metal plate, and a core plate of the t-th road, The multi-layer line carrier board can be coupled to the first surface of the first carrier board by the first adhesive layer, and the semi-conducting §# 曰 结合 结合 结合 结合 结合 结合 结合 结合 结合The second adhesive layer: in the front = manufacturing method, 'the basic requirement of the fixing member against the semiconductor wafer...' P has a solid shape, if the resin is mixed and filled 110856 7 200950037^... ^ ^ - Fanzhou, π-path error The fixing member has a fixed shape; and the fixing member may be columnar, spherical, tapered or irregular, and is not particularly limited. • In the above method, the opening may be in a curved combination of any shape, Circular or elliptical; of course, the shape of the opening may also be square, rectangular or polygonal 'so that the first carrier plate may have a plurality of filling holes connecting the edges and corners of the σ. Further, the method of manufacturing is described. The method further includes forming a build-up structure on the first surface of the first carrier and the active surface of the semiconductor wafer, comprising at least a germanium dielectric layer, a circuit layer formed on the dielectric layer, and being formed in the dielectric layer Electrical connection circuit layer and electrode孰η and on the build-up structure = contact pad 4 is provided with a solder resist layer on the build-up structure, and forms a gate contact of the open semiconductor month. [The dielectric layer can be filled into the opening:: between the sheets To strengthen the fixed semiconductor wafer in the opening. The substrate, ^= is a type of embedded semiconductor wafer package surface, the through-theft touch system has a relative first surface and the first and second surfaces of the first and second surfaces Opening; filling hole; semi-guided wafer, system =:: using face and non-active surface 'and the action mask == is fixed in the filling hole and opening to abut and secure the piece, according to the above The method can also be used to make a basket substrate such as s #山, including the second surface of the H = 7 (four) material conductor wafer, the through surface 4 having the opposite first surface and the shell bud. The first and second surfaces of the hai. The system is placed in the opening and the opening of the ': piece, the surface and the non-active surface, and the 1 gap has the opposite surface with the bungee pad; and the fixing piece , 110856 8 200950037 - Poor 'concave 5 and 'gap, to abut semiconductor wafers. In the foregoing package substrate, 'the basic requirement of embedding a semiconductor wafer' may be a core board having a double-sided line, a multilayer wiring board, a dielectric layer, or a metal plate. - In the above-mentioned package substrate, the basic requirement is that the fixing member abuts against the semiconductor wafer. If the material of the fixing member is resin, metal, ceramic, organic material or cured colloid, it has a fixed shape without heating, if it is a resin mixture True charge; = 1] then it needs to have a fixed shape by low temperature heating; and the solid member can be columnar, spherical, tapered or irregular, and the helmet is specifically limited. In the package substrate of the above description, the opening may be in a curved combination of any shape, a circle or an ellipse; of course, the shape of the opening may also be square, abrupt, so that the first carrier is There may be a plurality of plug holes that connect the edges and corners of the opening. In the foregoing package substrate, the second surface of the first carrier plate and the first carrier plate of the semiconductor chip are included in the basic requirement of embedding the semiconductor wafer, which may be an insulating plate and a core with a double-sided circuit. Board multiplex, dielectric layer, or metal plate. Moreover, the second carrier can be bonded to the second surface of the first carrier by an adhesive layer, and the non-active surface of the semiconductor crystal can be bonded to the second carrier or the first adhesive layer by the second adhesive layer. . In addition, the package substrate may include a build-up structure disposed on the f-plane of the first carrier and the active surface of the semiconductor wafer, and may include at least one dielectric layer and a circuit layer disposed on the dielectric layer. It is located in the dielectric layer 110856 9 200950037 儿 ▼ electric, Jiang reverse connection layer and the electrode on the electrode 电 接 导 导 导 、 、 、 、 、 、 、 、 、 、 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 ; layer 'and has an opening: between the conductor wafers. The middle 4 dielectric layer can fill the opening and the half - the invention is embedded in the semiconductor wafer, and it is also made by the design of the fixed part, the semi-conducting plate and the method, mainly between the opening and the opening. ;: two, when the opening, the semiconductor wafer 曰 y ” ” 疋 设 设 设 设 设 设 设 设 设 设 设 设 设 设 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体 半导体': The purpose of ensuring the positioning state of the semiconductor wafer is achieved. The connection position is not good, so as to improve the electrical conductivity. [Embodiment] 2 Embodiments of the present invention will be described by way of specific embodiments, and those skilled in the art may use only the prescriptions of a* ^ , ^ n Other advantages and effects of the present invention are readily understood from the disclosure of the present invention. The d-hearted and even 2D diagram is a schematic diagram of the method of manufacturing the package substrate of the semiconductor wafer after the invention. For example, f 2A and 2A do not, in which the 2A, the figure is the second picture of Figure 2; firstly, the first - the remaining 2 is provided and has a first surface 21a and a second surface and 91h a ... a ... having a relatively younger surface 21b, sub-formed at least one rectangular opening 2iq extending through the first surface 21a and the second surface 21b; and the shape of the opening training may also be an angular contour such as a square or a polygon, and Limited to the above. The hole 210a is further filled with the four sides of the opening 21〇 into the 110856 10 200950037, and the four-way plug hole 21〇a is connected to the opening 21 position # and its contour is curved. The second surface 21b of the first carrier plate 21 is coated with -, IS: a second carrier plate 22; in the embodiment, *: the second layer of the adhesive layer 24 is not attached to the opening (10) The first carrier board 21 and the second carrier board & are both core boards with double-sided lines, multi-layer circuit boards, dielectric sounds, "^ the carrier board 22 can also be an insulating board. The mountain and the first ^., _., ..., there are many kinds of sealing substrates used for embedding semiconductor wafers, but they are well known in the industry, and the technical characteristics of the basin, so will not be described again, hereby stated As shown in the drawing of Buben, a semiconductor wafer 23 is provided having a relative number of Leito rail states having a re-powering (four) 231, placing the semiconductor wafer 23 in the opening 21, and = conductor The non-active surface 23b of the wafer 23 is bonded to the carrier 22 by the second landing layer 25 such that the non-active surface 23b of the semiconductor wafer 23 is on the same side as the second surface 2 of the first carrier 21. And 2C, as shown in the figure, wherein the 2C, the figure is the % map, and the fixing member 26 is placed in the filling hole 21〇a, and the The slit 26 corresponds to the wheel temple of the plug hole 21Ga and is formed in a cylindrical shape and protrudes to the opening 21A so that the fixing member 26 abuts on the four sides of the semiconductor wafer 23, although the opening 210 and the semiconductor wafer 23 are With the gap d, the half, the body wafer 23 is easily biased by the force of the subsequent process, but the semiconductor wafer 23 is effectively strengthened by the fixing member 26 first abutting on the side of the semiconductor wafer 23. Positioning ability in the opening 21〇, π 110856 200950037 • The occurrence of the offset phenomenon in the technique of the accommodating brother is as shown in FIG. 2D, on the first surface 2a _ of the first carrier 21 and the semiconductor wafer 23 Forming a build-up structure on the active surface 23a, wherein the build-up structure 27 includes at least a dielectric layer 271, a circuit layer m on the dielectric layer m, and a plurality of layers formed in the dielectric layer (7). The rain-failure force of the electrical connection circuit layer 272 is 97Q ^ . The electric blind hole 273a is electrically connected to the electrode pad 231 of the semiconductor/mesh portion of the semiconductor wafer 23, and the outer layer W2% has a plurality of electrical properties. Contact ^ ❹: and: The Γ structure 27 is formed with an anti-...^ opening 28G to correspondingly reveal The electrical contact 塾 274. The portion of the innermost layer of the dielectric layer 27 of the build-up structure 27 is formed in the gap d between the opening 211 and the semiconductor sy00 (as shown in FIG. 2C, FIG. 2). The semiconductor wafer 23 is reinforced and fixed in the opening 21 图 in the present embodiment. In the fourth embodiment, the carrier plate 2 and the second carrier plate 22 and the build-up structure 27 are electrically conductive. m__M,im(pTH) ), and it is not the technical characteristics of this case. The second technology is well known in the industry, and it is not illustrated and will not be described in detail. The latter's eyesight refers to the 2D, Fig., #helmet筮^ „ implementation aspect; as shown in the figure, j is the other layer 22 of the viscous layer 24 The second carrier semiconductor wafer 23 is formed on the first pedestal-bearing plate 22 such that the non-active surface 23b of the opening _5 is bonded to the squeezing layer 24 of the ζιυ. 'The present invention is placed on the four sides of the plug hole 2i〇a by the fixing member 26 into the 2U) to abut the side of the semiconductor wafer 23 disposed in 110856 12 200950037 - 叩p. The fixing member 2β and the semi-conductor wafer 23 are tightly fitted to each other to produce a positioning effect. Compared with the prior art, the present invention can be avoided by the setting of the fixing #26, and the electric layer 271a is thermally pressed. When the carrier chip 21 and the semiconductor wafer (2) are mounted, the semiconductor wafer 23 is displaced, and the conductive blind via 273a is electrically connected to the electrode 231. Referring to FIG. 3, another embodiment of the embodiment is shown. The difference is only in the position and quantity of the plug hole 2l〇a, and the other related processes are the same as the knot structure, so Repeatedly, the same part will be described as only the subtraction. The material (s) is provided with two filling holes 21〇a, and the filling holes 21〇a' are also formed at the four corners (c〇ner) so that the fixing member After being provided in the plugging holes 21〇&, the positioning ability of the semiconductor wafer 23 in the opening 21〇 is enhanced by the number of the fixing members 26 and the abutting force around the semiconductor wafer 23. Please refer to the 4A together. As shown in FIG. 4E, the fixing member 26 is composed of a resin, a metal, a ceramic, a cured colloid or an organic material, and has a fixed shape without adding heat, and the structure is columnar, spherical, tapered or not. The rule is three-dimensional (as shown in FIG. 4E), so that the fixing member 26 is placed in the stuffing hole 21 Oa to effectively generate an abutting effect. However, in other embodiments, the mouth piece 26 may be composed of a resin mixed filler. However, it needs to be heated by low temperature to have a desired fixed shape. According to the above method, the present invention provides a package substrate embedded with a semiconductor wafer, comprising: a first carrier 21, a semiconductor wafer 23, and a fixing member 26. 110856 13 200950037 Γ; The first carrier 21 of the first floor has a first surface 21a and a second surface 21b, at least one opening 210' extending through the first surface 21a and the second surface 21b, and a filling hole 210a of the communication opening 210. The semiconductor wafer 23 is disposed in the opening 210 and has a pair of opposing surfaces 23a and a non-acting surface 23b. The active surface 23a has a plurality of electrode pads 231. The first fixing member 26 is disposed in the filling hole 2110a. To position the semiconductor wafer 23 against the fixed semiconductor wafer 23, the semiconductor wafer 23 is positioned in the opening 21A.
—另外，所述之封裝基板復包括第二承載板22，其藉 由第-黏著層24結合於第一承載板21之第二表面抓， 而半導體晶片23之非作用® 23b則藉由第二黏著層25 結合於第二承载板22上。 又，該封裝基板包括增層結構27，其設於第一承载 板21之帛表® 2la及半導體晶片23之作用面23a上。In addition, the package substrate further includes a second carrier 22, which is bonded to the second surface of the first carrier 21 by the first adhesive layer 24, and the non-active® 23b of the semiconductor wafer 23 is The second adhesive layer 25 is bonded to the second carrier plate 22. Further, the package substrate includes a build-up structure 27 which is provided on the surface of the first carrier 21 and the active surface 23a of the semiconductor wafer 23.
雷廢所述之增層結構27包括至少—介電層271、設於介 271上之線路層272、及複數設於介電層中且電 ::線路層之導電盲孔273;其中部份之導電盲孔π% 声=接半導體晶片㈡之電極墊23ι，而最外層之線路 二古8貝】具有複數電性接觸整274，且於增層結構27上 Λ l防焊層28中具有複數開孔280，以對 應顯露各該電性接觸墊274。 Γ 1第5A至5C圖，係為本發明嵌埋半導體晶片之 圖：：f法之另-實施例，其中第5C，圖係為第5C • 思圖，其與上述實施例之差異僅在於本製法並 14 110856 200950037 .之設計，故其餘㈣製程與結構大致相同，因此 •不再贅述’僅以簡述說明其相異處，特此敛明。 如第5A圖所示’·首先，提供—第一承編】，其具 m第-表面51a及第二表面51b，並形成至少一貫 一面5ia及弟二表面训之開0 51〇;接著，於第 :板51之第二表面51b上以第一黏著層⑷吉合一第 一承載板5 2。 圖所示，提供一半導體晶片53，其具有相對 ❹=用面53a及非作用Φ咖，於該作用面…上具有複 數％極塾531，將該半導體晶片53置於開口 51〇中，且 2導f晶片53之非作用面53b藉由第二黏著層55結合 與第-承葡m /一 片53之非作用面53b 之弟一表面51b同侧，且其與開口 510 之間具有間隙d。 圖·;及5C圖所不’其中* 5C,圖係為上視示意 圖，於間隙d中罟人mu ❾導ϋ曰Μ & 口疋件56，以便使固定件56抵靠半 曰曰片，雖然開口 51〇與半導體晶片Μ之間具有間 丰C固定件56抵靠半導體晶片53,而有效加強 於開口 51°中之定位能力，得以避免習知 技術中偏移現象之發生。 升；，Π卜，於本實施例中’該開口 510呈曲線組合任意 二Ρ:广’亦可呈圓形或橢圓形等無稜角之輪廓，並無特 卽二:贫X後續製程可如第2D圖之增層結構27製程， 即於该第一承载板51之第一表面51a及半導體晶片53 110856 15 200950037 cn 〜.,P/T3㈤5%上形成增層結構27’故不再贅述。 • 依此實施例，本發明形成另—種嵌埋半導體晶片之封 裝基板，係包括：第一承載板51 、 ' 板51丰導體晶片53以及固 •疋：56。该弟一承載板51具有相對之第一表面51 •二表面训、及貫穿該第一及第二表面叫训之開口 510，6亥半導體晶片53容置;^ Rln oa _ 置κ開口 5】〇中且與開口 5】fl 之間具有間隙d，而且具有相對之作 r〇K „ _ ., m 卞用面53a及非作用面 ’且该作用面53a具有複數電_ 53ι ;該固定件％ ❹in設㈣隙d’以抵靠固定該半導體晶片53。 本發明嵌埋半導體晶片之封裝基板及其製法， 由將固定件置入丰導體ay日 文稽 从，土… 牛導肢日日片與開口之間之間隙，以使固定 “半導體晶片之側邊’俾將半導體晶片固定於開口 中，以避免後續之介電層熱屢合時，半導體晶片於開口之 内產生偏移，以達到確保半導體晶片之定位狀離之目的· 使導電盲孔得以準確連接電姉，而達频昇電性 良率之目的。 β 上述貫施例係用以例示性說明本發明之原理及其功 效，而非用於限制本發明。任何熟習此項技藝之人士^可 在不違背本發明之精神及範Β壽下，對上述實施例進行修 口此本發明之權利保護範圍，應如後述之中請專 圍所列。 【圖式簡單説明】 第1AS1D圖係為習知散埋半導體晶片之封裝基板的 製法示意圖mA，圖係為上視示意圖； 110856 16 200950037 - 矛乙A至圖係為本私a日山、丨…* . Λ月肷埋半導體晶J4夕44·脖且4c 的製法示意圖；其中，筮 θ片之封裝基板 • 弟2Α圖係為第2Α Fi L、s - 土 圖；第2C，圖係為第2C圖 立·Α圖之上視不思 圖係為本發明嵌曰 L之示查圓. “心曰片之封裝基板之另 *對於第2D圖之另-實施態樣· "思圖’第2D’圖係為相 第 實施態樣之示意圖； 之：之至二=:;:埋半導體“之封— 〇 嵌埋半導體晶片之封裝基板 第5C’圖係為第5C圖之上 弟5 A至5 C圖係為本發明 的製法之另一實施例·，其中， 視不意圖。 【主要元件符號說明】 第一承載板 矩形開口 第一表面 第二表面 第二承載板 半導體晶片 電極塾 作用面 非作用面 點著層 介電層 線路層 11 、 21 、 51 110 11a、21a、51a lib、21b、51b ® 12 、 22 、 52 13 、 23 、 53 131 、 23卜 531 13a、23a、53a 13b、23b、53b 14 15 、 271 、 271a 16 、 272 、 272a 110856 17 200950037 丄 υ jl ^ > 273a導電盲孔 210 、 510 * 開口 210a 填塞孔 -24 、 54 第一黏著層 .25 、 55 第二黏著層 26、56 固定件 27 增層結構 274 電性接觸墊 ^ 28 ❹ 防焊層 280 開孔 d 間隙 e 偏移 18 110856The additive layer structure 27 includes at least a dielectric layer 271, a circuit layer 272 disposed on the dielectric layer 271, and a plurality of conductive blind vias 273 disposed in the dielectric layer and electrically: a circuit layer; The conductive blind hole π% sound = the electrode pad 23 ι of the semiconductor wafer (2), and the outermost layer of the circuit 2 gu 8 has a plurality of electrical contact 274, and has a build-up structure 27 Λ l solder resist layer 28 A plurality of openings 280 are formed to correspondingly expose each of the electrical contact pads 274. Γ 1 5A to 5C are diagrams of the embedded semiconductor wafer of the present invention: another embodiment of the f method, wherein the 5C, the figure is the 5th, and the difference from the above embodiment is only The design of this method is 14 110856 200950037. Therefore, the rest of the process is basically the same as the structure. Therefore, it is not necessary to repeat the description of the differences. As shown in Fig. 5A, 'first, provide - first contraction', which has m-surface 51a and second surface 51b, and forms at least one side of 5ia and the second surface of the surface of the 50th; On the second surface 51b of the first plate 51, a first carrier plate 52 is combined with a first adhesive layer (4). As shown, a semiconductor wafer 53 is provided having a relative ❹=face 53a and a non-acting Φ, having a plurality of poles 531 on the active surface, the semiconductor wafer 53 being placed in the opening 51〇, and The non-acting surface 53b of the 2-via f-chip 53 is bonded to the side of the first surface 51b of the non-active surface 53b of the first-carrying m/pone 53 by the second adhesive layer 55, and has a gap d with the opening 510. . Figure 5; and 5C Figure does not 'where * 5C, the diagram is a top view, in the gap d in the gap mu ❾ guide & port 56, in order to make the fixture 56 against the half-chip Although the opening 51 〇 and the semiconductor wafer 具有 have the intervening C fixing member 56 against the semiconductor wafer 53, and effectively strengthen the positioning ability in the opening 51°, the occurrence of the offset phenomenon in the prior art can be avoided. In the present embodiment, the opening 510 is a curved combination of any two turns: wide can also be a circular or elliptical contour without an angle, and there is no special feature: the lean X subsequent process can be as The process of the build-up structure 27 of FIG. 2D, that is, the first surface 51a of the first carrier 51 and the semiconductor wafer 53 110856 15 200950037 cn~., P/T3 (five) 5% form a build-up structure 27', and therefore will not be described again. In accordance with this embodiment, the present invention forms a package substrate for another embedded semiconductor wafer, comprising: a first carrier plate 51, a 'plate 51 abundance conductor wafer 53 and a solid: 56. The carrier-bearing plate 51 has a first surface 51 opposite to each other, and an opening 510 extending through the first and second surfaces, and the semiconductor wafer 53 is accommodated; ^ Rln oa _ κ opening 5] There is a gap d between the 〇 and the opening 5] fl, and has a relative surface 53 _ _ ., m 卞 surface 53a and an inactive surface 'and the active surface 53a has a plurality of electric _ 53 ι; % ❹in is set to (4) the gap d' to fix the semiconductor wafer 53. The package substrate for embedding the semiconductor wafer of the present invention and the method for preparing the same are provided by placing the fixing member into the abundance conductor ay Japanese, from the earth... a gap between the opening and the opening, so that the semiconductor chip is fixed in the opening by the side of the semiconductor wafer, so as to avoid the thermal interference of the subsequent dielectric layer, the semiconductor wafer is offset within the opening to achieve To ensure the positioning of the semiconductor wafer away from the purpose of the purpose of making the conductive blind hole accurately connected to the power, and to achieve the purpose of the rate of power rise. The above-described embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any person skilled in the art can revise the above-described embodiments without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be as listed below. BRIEF DESCRIPTION OF THE DRAWINGS The 1AS1D diagram is a schematic diagram of a method for fabricating a package substrate of a conventional semiconductor wafer, and the diagram is a top view; 110856 16 200950037 - Spear B A to the map is a private mountain, 丨...* . 制月肷 buried semiconductor crystal J4 夕44· neck and 4c schematic diagram; wherein, 筮θ sheet of the package substrate • 2 Α diagram is the second Α Fi L, s - soil map; 2C, the diagram is The 2C diagram of the 2C diagram and the diagram is the inspection circle of the invention. The "encapsulation substrate of the heart-shaped film is another * for the 2D figure - the implementation aspect · " '2D' is a schematic diagram of the first embodiment; the: to the second =:;: buried semiconductor "sealing - the embedded substrate of the buried semiconductor wafer 5C' map is the 5C figure The 5A to 5C drawings are another embodiment of the manufacturing method of the present invention, wherein, it is not intended. [Description of main component symbols] First carrier plate rectangular opening first surface second surface second carrier plate semiconductor wafer electrode 塾 active surface non-active surface dot layer dielectric layer circuit layer 11, 21, 51 110 11a, 21a, 51a Lib, 21b, 51b ® 12, 22, 52 13 , 23 , 53 131 , 23 531 13a, 23a, 53a 13b, 23b, 53b 14 15 , 271 , 271a 16 , 272 , 272a 110856 17 200950037 丄υ jl ^ > 273a conductive blind hole 210, 510 * opening 210a filling hole - 24, 54 first adhesive layer. 25, 55 second adhesive layer 26, 56 fixing member 27 build-up structure 274 electrical contact pad ^ 28 ❹ solder resist layer 280 Opening d gap e offset 18 110856