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TWI388041B - Semiconductor package with heat dissipation structure - Google Patents

Semiconductor package with heat dissipation structure Download PDF

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Publication number
TWI388041B
TWI388041B TW097143464A TW97143464A TWI388041B TW I388041 B TWI388041 B TW I388041B TW 097143464 A TW097143464 A TW 097143464A TW 97143464 A TW97143464 A TW 97143464A TW I388041 B TWI388041 B TW I388041B
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Taiwan
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heat dissipation
heat
dissipation structure
semiconductor package
adhesive
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TW097143464A
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Chinese (zh)
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TW201019429A (en
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蔡芳霖
蔡和易
黃建屏
賴正淵
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矽品精密工業股份有限公司
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    • H10W72/0198
    • H10W72/877
    • H10W74/15
    • H10W90/724
    • H10W90/754

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Description

具散熱結構之半導體封裝件 Semiconductor package with heat dissipation structure

本發明係關於一種具散熱件之半導體封裝件,尤係關於一種藉散熱件以逸散半導體晶片所產生之熱量至大氣中的半導體封裝件。 BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor package having a heat sink, and more particularly to a semiconductor package in which a heat sink is used to dissipate heat generated by a semiconductor wafer into the atmosphere.

隨著電子產品在功能及處理速度之需求的提升,作為電子產品之核心組件的半導體晶片即須設有更高密度之電子元件(Electronic Components)及電子電路(Electronic Circuits)。但半導體晶片之積體化密度(Integrated Density)越高,其在運作時所產生之熱量即越大,若不能有效逸散所產生之熱量,則會對半導體晶片造成損害。故遂有於半導體封裝件中加設散熱片(Heat Sink或Heat Spreader)之設計發展出,以藉散熱片逸散出半導體晶片所產生之熱量。 As the demand for electronic products in terms of function and processing speed increases, semiconductor chips, which are the core components of electronic products, must be equipped with higher-density electronic components and electronic circuits (Electronic Circuits). However, the higher the integrated density of the semiconductor wafer, the greater the heat generated during operation, and if the heat generated is not effectively dissipated, the semiconductor wafer may be damaged. Therefore, the design of a heat sink (Heat Sink or Heat Spreader) in a semiconductor package has been developed to dissipate the heat generated by the semiconductor wafer by the heat sink.

具有散熱片之半導體封裝件已揭露於第5,883,430、5,604,978、6,008,536、6,376,907、6,403,882、6,472,762及6,504,723號等美國專利中。該等美國專利揭露出不同型態之散熱片之使用,但以散熱片之頂面外露出封裝膠體或直接外露於大氣中為佳,俾取得較佳之散熱效果。然而,若散熱片僅以頂面外露出封裝膠體而未直接黏接至半導體晶片,而使半導體晶片與散熱片間為封裝膠體所充填,則會因形成封裝膠體之如環氧樹脂(Epoxy Resin)之封裝化合物(Mold Compound)的熱傳導 性甚差,使半導體晶片產生之熱量仍無法有效傳遞至散熱片而逸散至大氣中;故遂亦有先前技藝提出將散熱片藉散熱膠黏置於半導體晶片上,以使半導體晶片所產生之熱量能藉熱傳導性較佳之散熱膠傳遞至散熱片以逸散至大氣中,如第8圖所示。 A semiconductor package having a heat sink is disclosed in U.S. Patent Nos. 5,883,430, 5,604,978, 6, 008, 536, 6, 376, 907, 6, 403, 882, 6, 472, 762 and 6, 504, 723. These U.S. patents disclose the use of different types of heat sinks, but it is preferred to expose the encapsulant on the top surface of the heat sink or directly exposed to the atmosphere to achieve better heat dissipation. However, if the heat sink only exposes the encapsulant on the top surface and does not directly adhere to the semiconductor wafer, and the semiconductor wafer and the heat sink are filled with the encapsulant, the epoxy resin (Epoxy Resin) is formed by the encapsulant. Thermal conductivity of the compound compound (Mold Compound) Very poor, so that the heat generated by the semiconductor wafer can not be effectively transmitted to the heat sink and escape to the atmosphere; therefore, it has also been proposed in the prior art to heat the heat sink on the semiconductor wafer to make the semiconductor wafer The heat can be transferred to the heat sink by the heat transfer adhesive with better thermal conductivity to escape to the atmosphere, as shown in Fig. 8.

第8圖所示之半導體封裝件8之散熱片80雖係以散熱膠81黏結至半導體晶片82,然而,散熱膠81為一昂貴之材料,雖能提升散熱效率,但會導致封裝成本之大幅提高;且,散熱片80、散熱膠81及半導體晶片82之熱膨脹係數(Coefficient of Thermal Expansion,CTE)均不同,故在封裝製程之溫度循環(Temperature Cycle)中,往往會因熱膨脹係數差異(CTE Mismatch)所產生之熱應力(Thermal Stress)導致散熱件80與散熱膠81間之介面及/或散熱膠81與半導體晶片82間之介面發現脫層(Delamination)現象,一旦脫層現象發生,半導體晶片82所產生熱量即無法有效逸散,並亦會隨之影響製成品之信賴性。此外,將散熱片80藉散熱膠81黏置於半導體晶片82上時,由於散熱膠81尚未固化(Cured),故不易控制該散熱片80相對於半導體晶片82或承載該半導體晶片82之基板83的水平度(Planity),當散熱片80產生傾斜時,會影響至製成品之外觀,且形成用以包覆該散熱片80及半導體晶片82之封裝膠體84的封裝化合物會溢膠至該散熱片80之頂面80a上,而影響至該散熱片80之散熱效率。 The heat sink 80 of the semiconductor package 8 shown in FIG. 8 is bonded to the semiconductor wafer 82 by the heat dissipating adhesive 81. However, the heat dissipating adhesive 81 is an expensive material, which can improve the heat dissipation efficiency, but causes a large packaging cost. Moreover, the coefficient of thermal expansion (CTE) of the heat sink 80, the heat sink 81 and the semiconductor wafer 82 are different, so in the temperature cycle of the packaging process, the coefficient of thermal expansion is often different (CTE). The thermal stress generated by Mismatch causes the interface between the heat sink 80 and the heat sink 81 and/or the interface between the heat sink 81 and the semiconductor wafer 82 to be delaminated. Once the delamination occurs, the semiconductor The heat generated by the wafer 82 cannot be effectively dissipated, and the reliability of the finished product is also affected. In addition, when the heat sink 80 is adhered to the semiconductor wafer 82 by the heat sink 81, since the heat sink 81 is not cured, it is difficult to control the heat sink 80 relative to the semiconductor wafer 82 or the substrate 83 carrying the semiconductor wafer 82. The gradation of the heat sink 80 affects the appearance of the finished product, and the encapsulating compound forming the encapsulant 84 for covering the heat sink 80 and the semiconductor wafer 82 overflows to the heat dissipation. The top surface 80a of the sheet 80 affects the heat dissipation efficiency of the heat sink 80.

此外,第5,166,772號美國專利提出一種具有網狀金屬罩蓋之半導體封裝件。如第9圖所示,該第5,166,772號美國專利所揭示之半導體封裝件9係在基板90上接置一網狀金屬罩蓋(Meshed Metallic Lasip)92,將半導體晶片91收納其中,再以封裝膠體93將該網狀金屬罩體92及半導體晶片91完全包覆。該半導體封裝件9係藉由該網狀金屬罩體92之提供,以遮蔽半導體晶片91所產生之電磁干擾(EMI)或由外部裝置所產生之電磁干擾,因該網狀金屬罩體92係包覆於封裝膠體93中,故無習知技術之在封裝件外加設金屬罩而造成體積過大及成本增加的問題。 No. 5,166,772 discloses a semiconductor package having a mesh metal cover. As shown in FIG. 9, the semiconductor package 9 disclosed in U.S. Patent No. 5,166,772 is attached to a substrate 90 with a mesh metal cover (Meshed Metallic Lass) 92, and the semiconductor wafer 91 is housed therein, and then packaged. The colloid 93 completely covers the mesh metal cover 92 and the semiconductor wafer 91. The semiconductor package 9 is provided by the mesh metal cover 92 to shield electromagnetic interference (EMI) generated by the semiconductor wafer 91 or electromagnetic interference generated by an external device, because the mesh metal cover 92 is Covered in the encapsulant 93, there is no known problem in that a metal cover is added to the package to cause an excessive volume and an increase in cost.

然而,第9圖所示之半導體封裝件9雖能解決電磁干擾之問題,但由於該網狀金屬罩體92係完全為封裝膠體93所包覆,且未能與半導體晶片91連接,故半導體晶片91所產生之熱量的傳遞途徑須經過導熱性甚差的封裝膠體,將使高積體化之半導體晶片所產生之熱量無法有效逸散出去,致會損及該半導體晶片91;且網狀金屬罩體92完全包覆於封裝膠體93中而無任何外露於大氣之部分,自當無法有效地產生散熱效果。更何況第6,504,723號美國專利已提出將半導體晶片完全包覆於金屬罩體中,毋須封裝膠體之使用,除能解決電磁干擾之問題,復可提升散熱效率,自較該第5,166,772號美國專利所揭示之裝置為佳;惟第6,504,723號美國專利所揭示之裝置仍存在前述之須使用昂貴之散熱膠及金屬罩體之水平度不易控制等 問題。 However, although the semiconductor package 9 shown in FIG. 9 can solve the problem of electromagnetic interference, since the mesh metal cover 92 is completely covered by the encapsulant 93 and cannot be connected to the semiconductor wafer 91, the semiconductor The heat generated by the wafer 91 is transmitted through a poorly thermally conductive encapsulant, so that the heat generated by the highly integrated semiconductor wafer cannot be effectively dissipated, thereby damaging the semiconductor wafer 91; and the mesh The metal cover 92 is completely covered in the encapsulant 93 without any exposed portion of the atmosphere, since the heat dissipation effect cannot be effectively produced. What is more, U.S. Patent No. 6,504,723, the entire disclosure of which is incorporated herein by reference in its entirety, the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all The device disclosed is preferred; however, the device disclosed in U.S. Patent No. 6,504,723 still has the aforementioned level of difficulty in controlling the use of expensive heat-dissipating glue and metal cover. problem.

因而,如何使散熱片與半導體晶片之結合不致產生前述之問題,乃成封裝業界一亟待解決之課題。 Therefore, how to combine the heat sink and the semiconductor wafer does not cause the aforementioned problems, which is an urgent problem to be solved in the packaging industry.

為解決前揭問題,本發明乃提供一種具散熱結構之半導體封裝件,能免除昂貴散熱膠之使用而降低封裝成本,能避免脫層之發生而提升散熱效率,並能解決散熱片黏置於半導體晶片上時,散熱片之平面度不易控制之問題。 In order to solve the above problems, the present invention provides a semiconductor package with a heat dissipation structure, which can reduce the cost of packaging by eliminating the use of expensive heat-dissipating glue, can avoid the occurrence of delamination, improve the heat dissipation efficiency, and can solve the heat sink adhesion. When the semiconductor wafer is mounted, the flatness of the heat sink is not easily controlled.

本發明所提供之具散熱結構之半導體封裝件,係包括一基板、至少一設置於該基板上並與基板電性連接之半導體晶片;以及黏設於該半導體晶片上之散熱結構,該散熱結構係由黏著劑、與該黏著劑結合且具有頂面與底面之第一散熱件(First Heat Dissipating Member)、以及黏結於該黏著劑上且具有頂面與底面之第二散熱件(Second Heat Dissipating Member)所構成,且該散熱結構係藉黏著劑黏置於該半導體晶片上,使該黏著劑位於該第二散熱件及半導體晶片間,並使該第一散熱件分別觸接至該第二散熱件之底面及半導體晶片,且該第一散熱件具有複數貫通第一散熱件之頂面及底面之通道,以供該黏著劑充填其中,而使該黏著劑之厚度相當於該第一散熱件自其頂面至底面之高度,俾令該黏著劑能分別與第二散熱件及半導體晶片黏結,並使該第一散熱件之頂面及底面同時觸接至第二散熱件及半導體晶片。 The semiconductor package with a heat dissipation structure provided by the present invention comprises a substrate, at least one semiconductor wafer disposed on the substrate and electrically connected to the substrate; and a heat dissipation structure adhered to the semiconductor wafer, the heat dissipation structure A first heat dissipating member combined with the adhesive and having a top surface and a bottom surface, and a second heat dissipating member having a top surface and a bottom surface bonded to the adhesive (Second Heat Dissipating) Member, wherein the heat dissipating structure is adhered to the semiconductor wafer by an adhesive, so that the adhesive is located between the second heat dissipating member and the semiconductor wafer, and the first heat dissipating member is respectively connected to the second a bottom surface of the heat dissipating member and the semiconductor wafer, and the first heat dissipating member has a plurality of passages penetrating through the top surface and the bottom surface of the first heat dissipating member for filling the adhesive, and the thickness of the adhesive is equivalent to the first heat dissipation The height of the piece from the top surface to the bottom surface allows the adhesive to be bonded to the second heat sink and the semiconductor wafer, respectively, and the top surface and the bottom surface of the first heat sink are simultaneously touched To a second heat sink and the semiconductor wafer.

該第一散熱件係以導熱性良好之金屬材料製成,其形 狀得為網狀金屬片體、形成有多數開孔之金屬片體、由波浪狀金屬線材組成之片狀結構或以多數成彎曲狀之短金屬線材組接而成之片狀結構。前述形狀均須具有多數通道形成於其中之特徵,以使黏著劑能充填於各該通道中而與第一散熱件形成良好之結合關係,同時能使該黏著劑之上表面與第一散熱件之頂面齊平及使該黏著劑之下表面與第一散熱件之底面齊平,俾令該黏著劑能分別與該第二散熱件與半導體晶片有效黏結。因此,由於該第一散熱件係與該黏著劑結合,故能有效釋除在後續之溫度循環中所產生之熱效應,而避免黏著劑與半導體晶片及黏著劑與第二散熱件間發生脫層現象。同時,由於該第一散熱件係分別觸接至該第二散熱件及半導體晶片,故該半導體晶片所產生之熱量能藉由該第一散熱件傳遞至第二散熱件,而由第二散熱件之頂面逸散至大氣中,所以本發明之半導體封裝件的散熱效率能進一步提升。再者,由於該第一散熱件係夾設於第二散熱件與半導體晶片間,故該第二散熱件藉該黏著劑黏置於半導體晶片上時,第二散熱件會為第一散熱件所支撐,遂無發生傾斜之顧慮,且不致有外觀問題(Appearance Issue)之發生。此外,該第一散熱件之熱傳導性較該黏著劑或習用之散熱膠為佳,故能免除習知之散熱膠的使用,而能降低封裝成本。 The first heat dissipating member is made of a metal material having good thermal conductivity, and its shape The shape is a mesh-shaped metal sheet body, a metal sheet body formed with a plurality of openings, a sheet-like structure composed of a wavy metal wire or a sheet-like structure in which a plurality of short metal wires are formed in a curved shape. The foregoing shapes are all required to have a plurality of channels formed therein, so that the adhesive can be filled in each of the channels to form a good bonding relationship with the first heat dissipating member, and at the same time, the upper surface of the adhesive and the first heat dissipating member can be formed. The top surface of the adhesive is flush and the lower surface of the adhesive is flush with the bottom surface of the first heat dissipating member, so that the adhesive can be effectively bonded to the second heat dissipating member and the semiconductor wafer, respectively. Therefore, since the first heat dissipating member is combined with the adhesive, the thermal effect generated in the subsequent temperature cycle can be effectively released, and the delamination between the adhesive and the semiconductor wafer and the adhesive and the second heat dissipating member can be avoided. phenomenon. At the same time, since the first heat dissipating member is respectively connected to the second heat dissipating member and the semiconductor wafer, the heat generated by the semiconductor chip can be transferred to the second heat dissipating member by the first heat dissipating member, and the second heat dissipating portion is The top surface of the device is dissipated into the atmosphere, so the heat dissipation efficiency of the semiconductor package of the present invention can be further improved. Furthermore, since the first heat dissipating member is interposed between the second heat dissipating member and the semiconductor wafer, when the second heat dissipating member is adhered to the semiconductor wafer by the adhesive, the second heat dissipating member is the first heat dissipating member. Supported, there is no concern about tilting, and there is no Appearance Issue. In addition, the thermal conductivity of the first heat dissipating member is better than that of the adhesive or the conventional thermal dissipating adhesive, so that the use of the conventional thermal dissipating adhesive can be eliminated, and the packaging cost can be reduced.

該第一散熱件之面積得相當於或大於黏著劑所敷設之面積。當第一散熱件之面積大於黏著劑之敷設面積時,係使該第一散熱件之至少一側或一部分能延伸至基板 上,而與基板上之被動元件或接地墊(Ground Pads)或接地環(Ground Ring)電性連接,以進一步提升本發明之半導體封裝件的電性;此外,該第一散熱件亦得向外延展至足以將半導體晶片包覆住之程度,俾對該半導體晶片提供抗電磁干擾(EMI Resistance)的功效。 The area of the first heat sink is equivalent to or larger than the area where the adhesive is applied. When the area of the first heat dissipating member is larger than the laying area of the adhesive, at least one side or a portion of the first heat dissipating member can extend to the substrate And electrically connected to a passive component or a ground pad or a ground ring on the substrate to further improve the electrical properties of the semiconductor package of the present invention; in addition, the first heat sink is also The extension is extended to the extent that the semiconductor wafer is covered, and the semiconductor wafer is provided with an EMI resistance.

以下係藉由特定的具體實施例說明本發明之實施方式,所屬技術領域中具有通常知識者可由本說明書所揭示之內容輕易瞭解本發明之功效及特點。 The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand the functions and features of the present invention from the disclosure of the present disclosure.

並須說明的是,本說明書中所敘述之“頂面”與“底面”及“上表面”與“下表面”並非絕對之空間概念,而係隨構成要件之空間關係而變化,亦即,倒置本案圖式中所示之半導體封裝件時,“頂面”即成“底面”而“底面”即成“頂面”,其它亦同。故該等“頂面”、“底面”、“上表面”與“下表面”名詞之使用,係用以說明本發明所揭示之半導體封裝件中構成要件間之連結關係,使本發明所揭示之半導體封裝件在等效之範圍內具有合理之變化與替換,而非用以限定本發明之可實施範圍於一特定之態樣(Embodiment)。 It should be noted that the "top surface" and "bottom surface" and "upper surface" and "lower surface" described in this specification are not absolute spatial concepts, but vary with the spatial relationship of the constituent elements, that is, When inverting the semiconductor package shown in the drawings, the "top surface" becomes the "bottom surface" and the "bottom surface" becomes the "top surface", and the others are the same. Therefore, the use of the terms "top surface", "bottom surface", "upper surface" and "lower surface" is used to describe the connection relationship between constituent elements in the semiconductor package disclosed in the present invention, so as to be disclosed by the present invention. The semiconductor package has reasonable variations and substitutions within the equivalent scope, and is not intended to limit the scope of the invention to a particular aspect.

第一實施例First embodiment

如第1A圖所示者,為本發明第一實施例之半導體封裝件之剖視圖。該第一實施例之半導體封裝件1係由基板10、黏設於該基板10上之半導體晶片11、黏設於該半導體晶片11上之散熱結構12、以及形成於該基板10上、以包覆該半導體晶片11與部分之散熱結構12之封裝膠體 13所構成者。 A first embodiment of the present invention is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention. The semiconductor package 1 of the first embodiment is composed of a substrate 10, a semiconductor wafer 11 adhered to the substrate 10, a heat dissipation structure 12 adhered to the semiconductor wafer 11, and a package formed on the substrate 10. a package colloid covering the semiconductor wafer 11 and a portion of the heat dissipation structure 12 13 members.

該基板10在本實施例中為習用之覆晶基板,以供該半導體晶片11以覆晶方式(Flip Chip)藉複數銲錫凸塊(Solder Bumps)14電性連接至該基板10之上表面100之預設位置上;同時,相對於該上表面100之下表面101上,則植設有複數顆成陣列(Array)方式排列的銲球(Solder Balls)15,以使該半導體晶片11能藉由該銲球15而與外界裝置(如印刷電路板)電性連接。由於該基板10為習知者,且以覆晶方式將半導體晶片11設於基板10與銲球之植接亦為習用技術,故在此不予贅述。 The substrate 10 is a conventional flip-chip substrate in this embodiment, so that the semiconductor wafer 11 is electrically connected to the upper surface 100 of the substrate 10 by a Flip Chip by a plurality of solder bumps 14 . At the same time, at the same time, relative to the lower surface 101 of the upper surface 100, a plurality of Arrays of solder balls 15 are arranged to enable the semiconductor wafer 11 to be borrowed. The solder ball 15 is electrically connected to an external device such as a printed circuit board. Since the substrate 10 is a conventional one, and the semiconductor wafer 11 is provided on the substrate 10 and the solder ball in a flip chip manner, it is also a conventional technique, and thus will not be described herein.

該散熱結構12係由黏著劑120、結合於該黏著劑120中之第一散熱件121、及黏結於該黏著劑120上之第二散熱件122所構成。該黏著劑120得使用如銀膠(Silver Paste)或環氧樹脂黏膠(Epoxy Resin Adhesive)之習用者。該第一散熱件121在本實施例係為一由金屬線材所編組而成之網狀片體,具有頂面121a及相對之底面121b,如第1B圖所示;該第一散熱件121由於係為金屬線材所構成,故具有多數個網目(Meshes),而形成供該黏著劑120通過並充填於其中的通道121c,使黏著劑120能藉由該等通道121c之提供而與第一散熱件121充分結合。同時,該第一散熱件121具有高度與該黏著劑120之厚度H相同的高度,使該黏著劑120與第一散熱件121結合後,該黏著劑120之上表面120a與第一散熱件121之頂面121a能齊平,且該黏著劑120之下表面120b與第一散熱 件121之底面121b能齊平,以令該第一散熱件121能以其頂面121a及底面121b分別抵接至該第二散熱件122之底面122b及半導體晶片11,俾使該半導體晶片11所產生之熱量能經由該第一散熱件121有效地傳遞至該第二散熱件122,再由該第二散熱件122將熱量逸散至大氣中。此外,由於該黏著劑120之上表面120a係與第一散熱件121之頂面121a齊平,而由第一散熱件121之通道(網目)121c中外露出,故能有效地以該黏著劑120將第二散熱件122黏結於該散熱結構12中;且,該黏著劑120之下表面120b係與第一散熱件121之底面121b齊平,而由第一散熱件121之通道121c中外露出,故能有效地藉由該黏著劑120將該散熱結構12黏固於該半導體晶片11上。 The heat dissipation structure 12 is composed of an adhesive 120, a first heat dissipation member 121 coupled to the adhesive 120, and a second heat dissipation member 122 bonded to the adhesive 120. The adhesive 120 is used by a conventional manufacturer such as Silver Paste or Epoxy Resin Adhesive. In the embodiment, the first heat dissipating member 121 is a mesh sheet formed by a metal wire, and has a top surface 121a and an opposite bottom surface 121b, as shown in FIG. 1B. The first heat sink 121 is The wire is made of a metal wire, so that there are a plurality of meshes (Meshes), and a channel 121c for the adhesive 120 to pass through and fill therein is formed, so that the adhesive 120 can be provided with the first heat dissipation by the channels 121c. The piece 121 is fully combined. At the same time, the first heat dissipating member 121 has the same height as the thickness H of the adhesive 120. After the adhesive 120 is combined with the first heat dissipating member 121, the upper surface 120a of the adhesive 120 and the first heat dissipating member 121 The top surface 121a can be flush, and the lower surface 120b of the adhesive 120 and the first heat dissipation The bottom surface 121b of the member 121 can be flushed so that the first heat dissipating member 121 can abut the bottom surface 122b of the second heat dissipating member 122 and the semiconductor wafer 11 with the top surface 121a and the bottom surface 121b, respectively. The generated heat can be efficiently transmitted to the second heat sink 122 via the first heat sink 121, and the heat is dissipated into the atmosphere by the second heat sink 122. In addition, since the upper surface 120a of the adhesive 120 is flush with the top surface 121a of the first heat sink 121 and exposed outside the channel (mesh) 121c of the first heat sink 121, the adhesive 120 can be effectively used. The second heat dissipating member 122 is adhered to the heat dissipating structure 12; and the lower surface 120b of the adhesive 120 is flush with the bottom surface 121b of the first heat dissipating member 121, and is exposed from the channel 121c of the first heat dissipating member 121. Therefore, the heat dissipation structure 12 can be effectively adhered to the semiconductor wafer 11 by the adhesive 120.

該第二散熱件122則得由如銅或其合金之金屬材料製成之金屬片體所構成,其厚度不限,係依設計上之選擇而定。該第二散熱件122之頂面122a在該封裝膠體13形成後係外露出該封裝膠體13而直接與大氣接觸,且其底面122b係與該第一散熱件121相接,故該半導體晶片11所產生之熱量遂能如上述之由第一散熱件121傳遞至第二散熱件122,進而由第二散熱件122外露於大氣之頂面122a逸散出。 The second heat dissipating member 122 is formed of a metal sheet made of a metal material such as copper or an alloy thereof, and the thickness thereof is not limited, and is determined by design choice. The top surface 122a of the second heat dissipating member 122 is exposed to the outside of the encapsulant 13 after the encapsulant 13 is formed, and the bottom surface 122b is in contact with the first heat dissipating member 121. Therefore, the semiconductor wafer 11 is The generated heat energy can be transmitted from the first heat sink 121 to the second heat sink 122 as described above, and then escaped by the second heat sink 122 exposed to the top surface 122a of the atmosphere.

此外,由圖可知,該散熱結構12藉由黏著劑120黏固於半導體晶片11上後,該黏著劑120與第一散熱件121係夾置(interposed)於第二散熱件122及半導體晶片11 之間。該第一散熱件121之面積得小於黏著劑120或半導體晶片11,使該第一散熱件121係完全結合於該黏著劑120中,如第1A圖所示;該第一散熱件121之面積亦得與黏著劑120或半導體晶片11之面積相當,使該第一散熱件121之周邊得外露出黏著劑120,但為簡化說明起見,在此不予圖示;當然,亦能令該第一散熱件121之面積大於黏著劑120或半導體晶片11之面積,此時,第一散熱件121能與封裝膠體13結合,而能藉由該第一散熱件121結合於封裝膠體13中之部分強化散熱結構12與封裝膠體13間的結合性,但為求簡化起見,在此亦不予圖示。然須知,第一散熱件121亦能延展至基板10上,以與基板10形成接地關係,此一結構將以另一實施例詳述之。 In addition, as shown in the figure, after the heat dissipating structure 12 is adhered to the semiconductor wafer 11 by the adhesive 120, the adhesive 120 and the first heat dissipating member 121 are interposed on the second heat dissipating member 122 and the semiconductor wafer 11. between. The area of the first heat sink 121 is smaller than that of the adhesive 120 or the semiconductor wafer 11, so that the first heat sink 121 is completely bonded to the adhesive 120, as shown in FIG. 1A; the area of the first heat sink 121 It is also required to have an area corresponding to the adhesive 120 or the semiconductor wafer 11, so that the periphery of the first heat dissipating member 121 is exposed to the adhesive 120, but for simplification of the description, it will not be shown here; of course, The area of the first heat sink 121 is greater than the area of the adhesive 120 or the semiconductor wafer 11. In this case, the first heat sink 121 can be combined with the encapsulant 13 and can be coupled to the encapsulant 13 by the first heat sink 121. The combination of the heat-dissipating structure 12 and the encapsulant 13 is partially reinforced, but it is not illustrated here for the sake of simplicity. It should be noted that the first heat dissipating member 121 can also be extended to the substrate 10 to form a grounding relationship with the substrate 10. This structure will be described in detail in another embodiment.

由上述之說明可知,本發明第一實施例之半導體封裝件1中的散熱結構12,係在用以黏結該第二散熱件122與半導體晶片11之黏著劑120中結合有第一散熱件121,藉由第一散熱件121具有與黏著劑120之厚度H相同之高度設計,使第一散熱件121能同時抵接至頂面122a外露出封裝膠體13的第二散熱件122及半導體晶片11,使半導體晶片11所產生之熱量能經由第一散熱件121及第二散熱件122構成之散熱途徑有效地逸散至大氣中,故毋須使用昂貴的散熱膠作為黏著劑來達成所欲之散熱效果,而以一般習用之黏著劑來黏結第二散熱件122與半導體晶片11即可,遂能降低封裝成本。再者,由於第一散 熱件121形成有多數之通道121c供黏著劑120充填並通過其中,所以能藉由第一散熱件121之金屬特性降低在後續之溫度循環中熱應力之產生對黏著劑120的影響,而避免熱應力之影響造成黏著劑120與半導體晶片11間之結合介面以及黏著劑120與第二散熱件122間之結合介面發生脫層現象,遂使脫層之產生所造成之散熱效率變差與信賴性問題(Reliability Concern)不致發生。此外,因有第一散熱件121夾置於第二散熱件122與半導體晶片11間,且第一散熱件121係與黏著劑120結合,故使第二散熱件122藉黏著劑120黏結至半導體晶片11上時,得有第一散熱件121之支撐不致產生偏斜(Tilt)之現象,而有效解決習知技術在散熱片與半導體晶片間僅有黏著層而不易控制散熱片之水平度的問題。 It can be seen from the above description that the heat dissipation structure 12 in the semiconductor package 1 of the first embodiment of the present invention is combined with the first heat dissipation member 121 in the adhesive 120 for bonding the second heat dissipation member 122 and the semiconductor wafer 11. The first heat dissipating member 121 has the same height design as the thickness H of the adhesive 120, so that the first heat dissipating member 121 can simultaneously abut the top surface 122a to expose the second heat dissipating member 122 of the encapsulant 13 and the semiconductor wafer 11. Therefore, the heat generated by the semiconductor wafer 11 can be effectively dissipated into the atmosphere through the heat dissipation path formed by the first heat sink 121 and the second heat sink 122, so that it is not necessary to use an expensive heat sink adhesive as an adhesive to achieve the desired heat dissipation. The effect is to bond the second heat sink 122 and the semiconductor wafer 11 with a conventional adhesive, which can reduce the packaging cost. Again, because of the first The heat member 121 is formed with a plurality of channels 121c for the adhesive 120 to be filled and passed therethrough, so that the influence of the generation of thermal stress on the adhesive 120 in the subsequent temperature cycle can be reduced by the metal characteristic of the first heat sink 121, thereby avoiding The influence of the thermal stress causes the bonding interface between the adhesive 120 and the semiconductor wafer 11 and the bonding interface between the adhesive 120 and the second heat sink 122 to delaminate, and the heat dissipation efficiency caused by the delamination is deteriorated and trusted. Reliability Concern does not happen. In addition, since the first heat dissipating member 121 is interposed between the second heat dissipating member 122 and the semiconductor wafer 11, and the first heat dissipating member 121 is bonded to the adhesive 120, the second heat dissipating member 122 is bonded to the semiconductor by the adhesive 120. When the wafer 11 is on the surface, the support of the first heat dissipating member 121 does not cause a tilt (Tilt) phenomenon, and the conventional technology effectively solves the problem that only the adhesive layer between the heat sink and the semiconductor wafer is not easy to control the level of the heat sink. problem.

第二實施例Second embodiment

如第2A圖所示者,為本發明第二實施例之半導體封裝件之剖視圖。如圖所示,該第二實施例之半導體封裝件2之結構與前述第一實施例所揭示者大致相同,其不同處在於第一散熱件221係成一波浪狀之片體構造。由第2B圖之第一散熱件221的立體圖可知,該第一散熱件221形成有多數之開孔221d,以與任兩相鄰之波浪間形成的溝槽221e共同構成供黏著劑220通過並充填其中的通道。該具波浪狀之第一散熱件221與前述第一實施例中所揭示之第一散熱件121相同,均具有可彈性形變而延展之特性的波浪狀構造,故使第一散熱件221能有彈性地夾置 於第二散熱件222與半導體晶片21間,而有效地避免將散熱結構22經由黏著劑220黏固至半導體晶片21上時不慎壓損半導體晶片21的發生。 As shown in Fig. 2A, a cross-sectional view of a semiconductor package in accordance with a second embodiment of the present invention. As shown, the structure of the semiconductor package 2 of the second embodiment is substantially the same as that disclosed in the first embodiment, except that the first heat sink 221 is formed into a wavy sheet structure. As can be seen from the perspective view of the first heat dissipating member 221 of FIG. 2B, the first heat dissipating member 221 is formed with a plurality of openings 221d, which together with the grooves 221e formed between any two adjacent waves constitute the adhesive 220. Fill in the passages. The undulating first heat dissipating member 221 is identical to the first heat dissipating member 121 disclosed in the first embodiment, and has a wave-like structure that can be elastically deformed and extended, so that the first heat dissipating member 221 can have Elastically placed Between the second heat sink 222 and the semiconductor wafer 21, the occurrence of the semiconductor wafer 21 is inadvertently damaged when the heat dissipation structure 22 is adhered to the semiconductor wafer 21 via the adhesive 220.

第三實施例Third embodiment

如第3A圖所示者,為本發明第三實施例之半導體封裝件之剖視圖。如圖所示,該第三實施例之半導體封裝件3之結構與前述第一實施例所揭示者大致相同,其不同處在於第一散熱件321係成平板狀之金屬片體所構成。如第3B圖之該第一散熱件321的立體圖可知,該第一散熱件321形成有多數之通道321c,以供黏著劑320通過並充填其中,該通道321c在圖示中係呈矩形,惟如圓形、橢圓形、多邊形等任何幾何形狀亦均適用。 As shown in Fig. 3A, a cross-sectional view of a semiconductor package in accordance with a third embodiment of the present invention. As shown in the figure, the structure of the semiconductor package 3 of the third embodiment is substantially the same as that disclosed in the first embodiment, except that the first heat sink 321 is formed into a flat metal sheet. As shown in the perspective view of the first heat sink 321 of FIG. 3B, the first heat sink 321 is formed with a plurality of channels 321c for the adhesive 320 to pass through and fill therein. The channel 321c is rectangular in the figure. Any geometric shape such as a circle, an ellipse, or a polygon is also applicable.

第四實施例Fourth embodiment

如第4A圖所示者,為本發明第四實施例之半導體封裝件之剖視圖。如圖所示,該第四實施例之半導體封裝件4之結構與前述第一實施例所揭示者大致相同,不同之處係在於其第一散熱件421係由複數根呈不規則形狀或規則形狀之短金屬線材所構成。由第4B圖所示之第四實施例之第一散熱件421的立體圖可知,該由多數不規則形狀或具弧形之規則形狀之短金屬線材經壓合成的第一散熱件421,會具有複數亦呈不規則大小的通道421c,以供黏著劑420通過並充填其中。構成該第一散熱件421之短金屬線材能使用任何金屬材料於加工後產生之廢材或廢料,故能降低材料成本;且由於係由短金屬線材交錯結合 而成第一散熱件421,故第一散熱件421亦能具有良好之彈性變形的特性,在將由黏著劑420、第一散熱件421與第二散熱件422構成之散熱結構42經黏著劑420黏固至半導體晶片41上時,即不致壓損半導體晶片41。 As shown in Fig. 4A, a cross-sectional view of a semiconductor package in accordance with a fourth embodiment of the present invention. As shown in the figure, the structure of the semiconductor package 4 of the fourth embodiment is substantially the same as that disclosed in the first embodiment, except that the first heat dissipating member 421 is formed by a plurality of irregular shapes or rules. The shape is composed of short metal wires. As can be seen from the perspective view of the first heat dissipating member 421 of the fourth embodiment shown in FIG. 4B, the first heat dissipating member 421 which is pressed and synthesized by a plurality of irregularly shaped or curved regular shaped short metal wires may have The plural also has an irregularly sized passage 421c for the adhesive 420 to pass through and fill therein. The short metal wire constituting the first heat dissipating member 421 can use any metal material to generate waste materials or scraps after processing, thereby reducing the material cost; and because the short metal wires are interlaced The first heat dissipating member 421 is formed, so that the first heat dissipating member 421 can also have good elastic deformation characteristics. The heat dissipating structure 42 composed of the adhesive 420, the first heat dissipating member 421 and the second heat dissipating member 422 is adhered to the heat dissipating agent 420. When bonded to the semiconductor wafer 41, the semiconductor wafer 41 is not damaged.

第五實施例Fifth embodiment

如第5A圖所示者,為本發明第五實施例之半導體封裝件之剖視圖,如圖所示,該第五實施例之半導體封裝件5之結構與前述第一實施例所揭示者大致相同,不同之處係在於其第一散熱件521係由具多數通道521c之金屬片體構成,具有平面部521f及自平面部521f向外延伸之延伸部521g,如第5B圖所示。該延伸部521g乃延伸至基板50上,以與該基板50上之接地墊或接地環電性連接,俾藉該延伸部521g使第一散熱件521與基板50接地,而提升該半導體封裝件5之電性(Electrical Performance)。同時,該由延伸部521g及平面部521f構成之第一散熱件521係形成一將半導體晶片51罩覆住之罩體,能夠遮蔽電磁干擾(Electromagnetic Interference,EMI),故能進一步提升該半導體封裝件5之電性。當然,該延伸部521g亦能接地於設置在基板50上之被動元件(未圖示),同樣能達到接地效果;且該延伸部521g亦能僅形成於該平面部521f之一側,或相對之兩側(未圖示),而毋須形成於平面部521f之四側上。 As shown in FIG. 5A, a cross-sectional view of a semiconductor package according to a fifth embodiment of the present invention. As shown, the structure of the semiconductor package 5 of the fifth embodiment is substantially the same as that disclosed in the first embodiment. The difference is that the first heat dissipating member 521 is formed of a metal sheet body having a plurality of channels 521c, and has a flat portion 521f and an extending portion 521g extending outward from the flat portion 521f as shown in FIG. 5B. The extending portion 521g extends to the substrate 50 to be electrically connected to the ground pad or the grounding ring on the substrate 50. The first heat sink 521 and the substrate 50 are grounded by the extending portion 521g, and the semiconductor package is lifted. 5 Electrical properties (Electrical Performance). At the same time, the first heat dissipating member 521 composed of the extending portion 521g and the flat portion 521f forms a cover covering the semiconductor wafer 51, and can shield electromagnetic interference (EMI), thereby further enhancing the semiconductor package. The electrical properties of piece 5. Of course, the extending portion 521g can also be grounded to a passive component (not shown) disposed on the substrate 50, and can also achieve a grounding effect; and the extending portion 521g can also be formed only on one side of the planar portion 521f, or Both sides (not shown) are formed on the four sides of the flat portion 521f.

第六實施例Sixth embodiment

如第6圖所示者,為本發明第六實施例之半導體封裝 件之剖視圖。如圖所示,該第六實施例之半導體封裝件6之結構與前述第一實施例所稱示者大致相同,不同之處在於其半導體晶片61係藉多數之銲線64電性連接至基板60,為避免由黏著劑620、第一散熱件621與第二散熱件622構成之散熱結構62碰觸或干擾到銲線64而造成短路問題,係在該半導體晶片61上先黏結一假晶片(Dummy Chip)66,再將該散熱結構62藉黏著劑620黏置於該假晶片66上,如此,散熱結構62即不致碰觸或干擾到銲線64。且,假晶片66係以廢晶圓或廢晶片為材料,與半導體晶片61同為矽材料,故半導體晶片61所產生之熱量仍能有效地藉該假晶片66傳遞至散熱結構62,而無影響散熱效率之虞。須知圖中所示之第一散熱件621係以具通道之金屬片體態樣呈現,其僅係用以例示,其它本發明所揭示之態樣或其等效之變化或改變亦均能適用。 As shown in FIG. 6, the semiconductor package of the sixth embodiment of the present invention A cross-sectional view of the piece. As shown in the figure, the structure of the semiconductor package 6 of the sixth embodiment is substantially the same as that of the first embodiment, except that the semiconductor wafer 61 is electrically connected to the substrate by a plurality of bonding wires 64. 60. In order to avoid the short circuit problem caused by the heat sink structure 62 formed by the adhesive 620, the first heat sink 621 and the second heat sink 622 touching or interfering with the bonding wire 64, a dummy wafer is bonded on the semiconductor wafer 61. (Dummy Chip) 66, the heat dissipation structure 62 is adhered to the dummy wafer 66 by the adhesive 620, so that the heat dissipation structure 62 does not touch or interfere with the bonding wire 64. Moreover, the dummy wafer 66 is made of waste wafer or waste wafer, and is the same as the semiconductor wafer 61. Therefore, the heat generated by the semiconductor wafer 61 can be effectively transferred to the heat dissipation structure 62 by the dummy wafer 66 without Affects the efficiency of heat dissipation. It is to be understood that the first heat dissipating member 621 shown in the drawings is in the form of a metal sheet body having a passage, which is merely for exemplification, and other variations or modifications of the disclosed aspects or equivalents thereof are also applicable.

第七實施例Seventh embodiment

如第7圖所示者,為本發明第七實施例之半導體封裝件之剖視圖。如圖所示,該第七實施例之半導體封裝件7之結構與前述第一實施例所揭示者大致相同,不同之處在於其第二散熱件722係成一金屬罩蓋(Metallic Casing),在藉黏著劑720黏固於半導體晶片71上後,即罩覆住該半導體晶片71,且該第二散熱件722之腳部722e係藉黏著材料77黏固於基板70上,而使該半導體晶片71為該第二散熱件722氣密地封罩住(Hermically Sealed),故毋須形成封裝膠體來包覆該半導體晶片71。 As shown in Fig. 7, a cross-sectional view of a semiconductor package of a seventh embodiment of the present invention. As shown in the figure, the structure of the semiconductor package 7 of the seventh embodiment is substantially the same as that disclosed in the first embodiment, except that the second heat sink 722 is formed as a metal cover (Metallic Casing). After the adhesive 720 is adhered to the semiconductor wafer 71, the semiconductor wafer 71 is covered, and the leg portion 722e of the second heat sink 722 is adhered to the substrate 70 by the adhesive material 77. 71 is hermetically sealed for the second heat sink 722, so that it is not necessary to form an encapsulant to cover the semiconductor wafer 71.

在本實施例中所顯示之第一散熱件721亦係以具通道之金屬片體之態樣呈現,其僅係用以例示,其它本發明所揭示之態樣或其等效之變化或改變亦均適用。 The first heat dissipating member 721 shown in this embodiment is also presented in the form of a metal piece having a channel, which is merely for illustration, and other aspects of the present invention or equivalent changes or changes thereof. Also applicable.

上述實施例僅例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修飾與改變。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。 The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the claims described below.

1、2、3、4、5、6、7、8、9‧‧‧半導體封裝件 1, 2, 3, 4, 5, 6, 7, 8, 9‧‧‧ semiconductor packages

10、50、60、70、83、90‧‧‧基板 10, 50, 60, 70, 83, 90‧‧‧ substrates

100、120a‧‧‧上表面 100, 120a‧‧‧ upper surface

101、120b‧‧‧下表面 101, 120b‧‧‧ lower surface

11、21、41、61、71、82、91‧‧‧半導體晶片 11, 21, 41, 61, 71, 82, 91‧‧‧ semiconductor wafers

12、62‧‧‧散熱結構 12, 62‧‧‧ heat dissipation structure

120、220、320、420、620、720‧‧‧黏著劑 120, 220, 320, 420, 620, 720‧‧‧ adhesives

121、221、321、421、521、621、721‧‧‧第一散熱件 121, 221, 321, 421, 521, 621, 721‧‧‧ first heat sink

121a、122a‧‧‧頂面 121a, 122a‧‧‧ top

121b、122b‧‧‧底面 121b, 122b‧‧‧ bottom

121c、321c、421c、521c‧‧‧通道 121c, 321c, 421c, 521c‧‧‧ channels

122、222、422、622、722‧‧‧第二散熱件 122, 222, 422, 622, 722‧‧‧ second heat sink

13、84、93‧‧‧封裝膠體 13,84,93‧‧‧Package colloid

14‧‧‧銲錫凸塊 14‧‧‧ solder bumps

15‧‧‧銲球 15‧‧‧ solder balls

22、42‧‧‧散熱結構 22, 42‧‧‧ heat dissipation structure

221d‧‧‧開孔 221d‧‧‧Opening

221e‧‧‧溝槽 221e‧‧‧ trench

521f‧‧‧平面部 521f‧‧‧Flat Department

521g‧‧‧延伸部 521g‧‧‧Extension

64‧‧‧銲線 64‧‧‧welding line

66‧‧‧假晶片 66‧‧‧false wafer

722e‧‧‧腳部 722e‧‧‧foot

77‧‧‧黏著材料 77‧‧‧Adhesive material

80‧‧‧散熱片 80‧‧‧ Heat sink

80a‧‧‧頂面 80a‧‧‧ top

81‧‧‧散熱膠 81‧‧‧Solution glue

92‧‧‧金屬罩體 92‧‧‧Metal cover

第1A圖係本發明第一實施例之半導體封裝件之剖視圖;第1B圖係第1A圖所繪示之第一散熱件之立體示意圖;第2A圖係本發明第二實施例之半導體封裝件之剖視圖;第2B圖係第2A圖所繪示之第一散熱件之立體示意圖;第3A圖係本發明第三實施例之半導體封裝件之剖視圖;第3B圖係第3A圖所繪示之第一散熱件之立體示意圖;第4A圖係本發明第四實施例之半導體封裝件之剖視圖;第4B圖係第4A圖所繪示之第一散熱件之立體示意 圖;第5A圖係本發明第五實施例之半導體封裝件之剖視圖;第5B圖係第5A圖所繪示之第一散熱件之立體示意圖;第6圖係本發明第六實施例之半導體封裝件之剖視圖;第7圖係本發明第七實施例之半導體封裝件之剖視圖;第8圖係習知半導體封裝件之剖視圖;以及第9圖係另一習知半導體封裝件之剖視圖。 1A is a cross-sectional view of a semiconductor package of a first embodiment of the present invention; FIG. 1B is a perspective view of the first heat sink shown in FIG. 1A; and FIG. 2A is a semiconductor package of a second embodiment of the present invention; 2B is a perspective view of the first heat sink illustrated in FIG. 2A; FIG. 3A is a cross-sectional view of the semiconductor package of the third embodiment of the present invention; FIG. 3B is a diagram of FIG. 3A FIG. 4A is a cross-sectional view of a semiconductor package according to a fourth embodiment of the present invention; FIG. 4B is a perspective view of the first heat sink illustrated in FIG. 4A 5A is a cross-sectional view of a semiconductor package of a fifth embodiment of the present invention; FIG. 5B is a perspective view of the first heat sink shown in FIG. 5A; and FIG. 6 is a semiconductor of a sixth embodiment of the present invention; Figure 7 is a cross-sectional view of a semiconductor package of a seventh embodiment of the present invention; Figure 8 is a cross-sectional view of a conventional semiconductor package; and Figure 9 is a cross-sectional view of another conventional semiconductor package.

1‧‧‧半導體封裝件 1‧‧‧Semiconductor package

10‧‧‧基板 10‧‧‧Substrate

100、120a‧‧‧上表面 100, 120a‧‧‧ upper surface

101、120b‧‧‧下表面 101, 120b‧‧‧ lower surface

11‧‧‧半導體晶片 11‧‧‧Semiconductor wafer

12‧‧‧散熱結構 12‧‧‧ Heat dissipation structure

120‧‧‧黏著劑 120‧‧‧Adhesive

121‧‧‧第一散熱件 121‧‧‧First heat sink

121a、122a‧‧‧頂面 121a, 122a‧‧‧ top

121b、122b‧‧‧底面 121b, 122b‧‧‧ bottom

122‧‧‧第二散熱件 122‧‧‧second heat sink

13‧‧‧封裝膠體 13‧‧‧Package colloid

14‧‧‧銲錫凸塊 14‧‧‧ solder bumps

15‧‧‧銲球 15‧‧‧ solder balls

Claims (15)

一種具散熱結構之半導體封裝件,係包括:基板;至少一設於該基板上並與該基板電性連接之半導體晶片;以及黏設於該半導體晶片上之該散熱結構,該散熱結構包括:黏著劑;與該黏著劑結合且具有頂面與底面之第一散熱件,該第一散熱件並具有貫連該頂面與底面之複數通道,以供該黏著劑充填其中;以及黏結於該黏著劑上之第二散熱件,其中,該黏著劑及該第一散熱件係夾置於該第二散熱件與半導體晶片間,以使該第二散熱件與半導體晶片能直接與該黏著劑黏結。 A semiconductor package having a heat dissipation structure includes: a substrate; at least one semiconductor wafer disposed on the substrate and electrically connected to the substrate; and the heat dissipation structure adhered to the semiconductor wafer, the heat dissipation structure comprising: An adhesive; a first heat sink combined with the adhesive and having a top surface and a bottom surface, the first heat sink having a plurality of passages connecting the top surface and the bottom surface for filling the adhesive; and bonding to the adhesive a second heat dissipating member on the adhesive, wherein the adhesive and the first heat dissipating member are interposed between the second heat dissipating member and the semiconductor wafer, so that the second heat dissipating member and the semiconductor wafer can directly contact the adhesive Bonding. 如申請專利範圍第1項之具散熱結構之半導體封裝件,復包括形成於該基板上、以包覆該半導體晶片及部分之散熱結構之封裝膠體,但使該散熱結構之第二散熱件的頂面外露出該封裝膠體。 The semiconductor package having a heat dissipation structure according to claim 1, further comprising an encapsulant formed on the substrate to cover the semiconductor wafer and a portion of the heat dissipation structure, but the second heat dissipation member of the heat dissipation structure is The encapsulant is exposed on the top surface. 如申請專利範圍第1項之具散熱結構之半導體封裝件,復包括複數個植接於該基板上之銲球,該基板供植接銲球之表面係相對於其供該半導體晶片設置之表面。 A semiconductor package having a heat dissipation structure according to claim 1, further comprising a plurality of solder balls implanted on the substrate, wherein the substrate is provided with a surface of the solder ball relative to a surface on which the semiconductor wafer is disposed . 如申請專利範圍第1項之具散熱結構之半導體封裝件,其中,充填於該第一散熱件中之黏著劑能外露出 該第一散熱件之頂面及底面,而使該第一散熱件之頂面至底面之高度相同於該黏著劑之厚度,且該第一散熱件之頂面與底面係分別抵接至該第二散熱件與半導體晶片。 The semiconductor package with a heat dissipation structure according to claim 1, wherein the adhesive filled in the first heat dissipation member can be exposed a top surface and a bottom surface of the first heat dissipating member, wherein a height from a top surface to a bottom surface of the first heat dissipating member is the same as a thickness of the adhesive, and a top surface and a bottom surface of the first heat dissipating member are respectively abutted to the The second heat sink and the semiconductor wafer. 如申請專利範圍第1項之具散熱結構之半導體封裝件,其中,該第一散熱件係為網狀金屬片體,具有複數個作為該通道之網目。 The semiconductor package having a heat dissipation structure according to claim 1, wherein the first heat dissipation member is a mesh metal sheet having a plurality of meshes as the channel. 如申請專利範圍第5項之具散熱結構之半導體封裝件,其中,該網狀金屬片體係具有呈波浪狀之線材。 A semiconductor package having a heat dissipation structure according to claim 5, wherein the mesh metal sheet system has a wavy wire. 如申請專利範圍第1項之具散熱結構之半導體封裝件,其中,該第一散熱件係為具有多數作為該通道用之開孔的金屬片體。 A semiconductor package having a heat dissipation structure according to claim 1, wherein the first heat dissipation member is a metal sheet having a plurality of openings for the channel. 如申請專利範圍第7項之具散熱結構之半導體封裝件,其中,該金屬片體係呈波浪狀。 A semiconductor package having a heat dissipation structure according to claim 7 of the patent application, wherein the metal piece system has a wave shape. 如申請專利範圍第1項之具散熱結構之半導體封裝件,其中,該第一散熱件係由複數根規則或不規則之短金屬線材構成者。 A semiconductor package having a heat dissipation structure according to claim 1, wherein the first heat dissipation member is composed of a plurality of regular or irregular short metal wires. 如申請專利範圍第1項之具散熱結構之半導體封裝件,其中,該第一散熱件復具有向外延伸之延伸部。 A semiconductor package having a heat dissipation structure according to claim 1, wherein the first heat dissipation member has an outwardly extending extension. 如申請專利範圍第10項之具散熱結構之半導體封裝件,其中,該延伸部係延伸至該基板,以與該基板形成接地關係。 A semiconductor package having a heat dissipation structure according to claim 10, wherein the extension extends to the substrate to form a ground relationship with the substrate. 如申請專利範圍第1項之具散熱結構之半導體封裝件,其中,該第一散熱件係一金屬罩蓋,用以將該半 導體晶片氣密地封蓋於該基板上。 The semiconductor package with a heat dissipation structure according to claim 1, wherein the first heat dissipation member is a metal cover for the half The conductor wafer is hermetically sealed on the substrate. 如申請專利範圍第1項之具散熱結構之半導體封裝件,其中,該半導體晶片係藉複數銲錫凸塊以覆晶方式電性連接至該基板。 A semiconductor package having a heat dissipation structure according to claim 1, wherein the semiconductor wafer is electrically connected to the substrate by a plurality of solder bumps in a flip chip manner. 如申請專利範圍第1項之具散熱結構之半導體封裝件,其中,該半導體晶片係藉複數銲線電性連接至該基板。 A semiconductor package having a heat dissipation structure according to claim 1, wherein the semiconductor wafer is electrically connected to the substrate by a plurality of bonding wires. 如申請專利範圍第14項之具散熱結構之半導體封裝件,復包括一黏固於該半導體晶片上之假晶片,以供該散熱結構黏設於該假晶片上。 A semiconductor package having a heat dissipation structure according to claim 14 of the patent application, comprising a dummy wafer adhered to the semiconductor wafer, wherein the heat dissipation structure is adhered to the dummy wafer.
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