TWI393231B - Package substrate embedded with semiconductor wafer and preparation method thereof - Google Patents

Description

Package substrate embedded with semiconductor wafer and preparation method thereof

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a package substrate embedded with a semiconductor wafer and a method of fabricating the same.

With the evolution of semiconductor packaging technology, in addition to conventional wire bonding and Flip chip semiconductor packaging technologies, semiconductor devices have been developed in different package types, such as directly in a package. A semiconductor substrate having an integrated circuit is embedded and electrically integrated in a packaging substrate. Such a semiconductor device can reduce the overall volume and enhance electrical functions, and becomes a mainstream of packaging.

Referring to FIGS. 1A to 1D, there is shown a schematic diagram of a conventional method for embedding a package substrate of a semiconductor wafer, wherein the 1A' is a top view of FIG.

As shown in FIGS. 1A and 1A', a first carrier plate 11 is provided. The first carrier plate 11 has a first surface 11a and a second surface 11b opposite to each other and forms at least one through hole in the first carrier plate 11. The rectangular openings 110 of the first and second surfaces 11a, 11b simultaneously provide a second carrier plate 12 and are joined to the second surface 11b of the first carrier plate 11.

As shown in FIG. 1B, a semiconductor wafer 13 is provided. The semiconductor wafer 13 has an opposite active surface 13a and an inactive surface 13b. The active surface 13a has a plurality of electrode pads 131 and is adhered by an adhesive layer 14. The non-active surface 13b of the semiconductor wafer 13 is fixed to the rectangular opening 110 On the second carrier plate 12 in the middle.

As shown in FIG. 1C, a dielectric layer 15 is then thermally formed on the first carrier 11 and the active surface 13a of the semiconductor wafer 13, and the dielectric layer 15 is also filled between the rectangular opening 110 and the semiconductor wafer 13. In the gap.

As shown in FIG. 1D, a wiring layer 16 is formed on the dielectric layer 15, and a conductive via hole 161 is formed in the dielectric layer 15 to electrically connect the electrode pads 131 of the semiconductor wafer 13.

However, in the prior art, since a gap must be reserved between the semiconductor wafer 13 and the edge of the rectangular opening 110, when the dielectric layer 15 is subjected to hot pressing, the semiconductor wafer 13 is easily caused by pressure or bubble generation. The offset e is offset in the rectangular opening 110, and the offset e causes the alignment defect of the conductive blind via 161 to be connected to the electrode pad 131, and the electrode pad 131 cannot be electrically connected to the electrode pad 131 even if the deviation is too large.

Therefore, in view of the above problems, how to avoid the prior art when the dielectric layer is formed by hot pressing on the semiconductor wafer and the first carrier, the semiconductor wafer is easily offset, and the conductive blind via is paired with the semiconductor wafer. The bit deviation, even if the offset is too large, can not be effectively electrically connected, resulting in product scrapping and lowering the yield of the process, which has become a problem that is currently being solved.

In view of the above-mentioned deficiencies of the prior art, it is an object of the present invention to provide a package substrate embedded with a semiconductor wafer and a method of fabricating the same to ensure the positioning state of the semiconductor wafer.

Another object of the present invention is to provide a package substrate embedded with a semiconductor wafer and a method of fabricating the same to improve process yield.

To achieve the above and other objects, the present invention discloses a method for fabricating a package substrate embedded with a semiconductor wafer, comprising: providing a first carrier plate having a first surface, a second surface, and a first and a second Opening a second surface of the first carrier plate; forming a second carrier plate on the second surface of the first carrier; providing a semiconductor wafer on the second carrier plate and correspondingly located at the opening Wherein, it has opposite active and non-active surfaces, and the active surface has an electrode pad; and the fixing member is placed in the filling hole and in the opening to abut against the semiconductor wafer.

Further, a method for fabricating a package substrate embedded with a semiconductor wafer includes: providing a first carrier plate having opposite first and second surfaces, and openings through the first and second surfaces; The second surface of the carrier plate is coupled to a second carrier plate; a semiconductor wafer is disposed on the second carrier plate and correspondingly located in the opening, and has a gap between the opening and the opposite surface and the non-active surface. The active surface has an electrode pad; and the fixing member is disposed in the gap to abut the semiconductor wafer.

In the foregoing method, the semiconductor chip is embedded as a basic requirement, and the first and second carrier boards can be a core board having a double-sided line, a multilayer circuit board, a dielectric layer or a metal board, and the second carrier The plate may also be an insulating plate; in addition, the second carrier may be coupled to the second surface of the first carrier by the first adhesive layer, and the non-active surface of the semiconductor wafer may be bonded to the second adhesive layer The second carrier or the first adhesive layer.

In the above method, the basic requirement is that the fixing member abuts against the semiconductor wafer. If the material of the fixing member is resin, metal, ceramic, organic material or cured colloid, it has a fixed shape without heating, if the resin is mixed and filled. The charging agent needs to have a fixed shape by heating at a low temperature; and the fixing member may be columnar, spherical, tapered or irregular, and is not particularly limited.

In the above method, the opening may be in a curved combination of any shape, a circle or a circular shape; of course, the shape of the opening may also be square, rectangular or polygonal so that the first carrier can have a communication opening. A plurality of filling holes at the edges and corners.

In addition, the foregoing method may include forming a build-up structure on the first surface of the first carrier and the active surface of the semiconductor wafer, comprising at least one dielectric layer, a circuit layer formed on the dielectric layer, and forming And a conductive contact hole electrically connected to the circuit layer and the electrode pad, and an electrical contact pad disposed on the build-up structure, and a solder resist layer is formed on the build-up structure, and an opening is formed to Corresponding to the exposed electrical contact pads. Wherein, the dielectric layer can be filled between the opening and the semiconductor wafer to strengthen the fixed semiconductor wafer in the opening.

According to the foregoing method, a package substrate embedded with a semiconductor wafer can be fabricated, comprising: a first carrier plate having opposite first and second surfaces, openings through the first and second surfaces, and communication a filling hole of the opening; the semiconductor wafer is placed in the opening and has a relative active surface and an inactive surface, and the active surface has an electrode pad; and the fixing member is fixed in the filling hole and the opening to resist By semiconductor wafers.

According to the foregoing method, another package substrate embedded with a semiconductor wafer may be fabricated, comprising: a first carrier plate having opposite first and second surfaces, openings extending through the first and second surfaces; and a semiconductor The wafer is placed in the opening and has a gap with the opening, and has an opposite active surface and an inactive surface, and the active surface has an electrode pad; and a fixing member, Secured to the gap to abut the semiconductor wafer.

In the foregoing package substrate, a basic requirement is to embed a semiconductor wafer, which may be a core board having a double-sided line, a multilayer wiring board, a dielectric layer, or a metal plate.

In the above-mentioned package substrate, it is a basic requirement that the fixing member abuts against the semiconductor wafer. If the material of the fixing member is resin, metal, ceramic, organic material or cured colloid, it has a fixed shape without heating, and is filled with resin. The agent needs to have a fixed shape by heating at a low temperature; and the fixing member may be columnar, spherical, tapered or irregular, and is not particularly limited.

In the foregoing package substrate, the opening may be in a curved combination of any shape, a circle or an ellipse; of course, the shape of the opening may also be square, rectangular or polygonal so that the first carrier can have a communication opening. A plurality of filling holes at the edges and corners.

In the foregoing package substrate, in order to embed the semiconductor wafer as a basic requirement, the second substrate including the second surface of the first carrier and the second carrier of the semiconductor chip may be used as an insulating board and have a double-sided line. Core board, multilayer wiring board, dielectric layer, or metal board. Moreover, the second carrier layer can be coupled to the second surface of the first carrier board by the first adhesive layer, and the non-active surface of the semiconductor wafer can be coupled to the second carrier board or the first layer by the second adhesive layer. Adhesive layer.

In addition, the package substrate may include a build-up structure disposed on the first surface of the first carrier and the active surface of the semiconductor chip, and may include at least one dielectric layer and a circuit disposed on the dielectric layer. Layer, located in the dielectric layer And electrically connecting the circuit layer and the conductive blind hole of the electrode pad, and the electrical contact pad disposed on the build-up structure, the build-up structure has a solder resist layer, and has an opening to expose the electrical contact pad. Wherein, the dielectric layer can be filled between the opening and the semiconductor wafer.

The package substrate embedding the semiconductor wafer of the present invention and the manufacturing method thereof are mainly provided by the design of the fixing member. When the semiconductor wafer is disposed in the opening, the semiconductor wafer has a gap between the opening and the opening, and the fixing member is disposed in the gap to abut the semiconductor wafer. The semiconductor wafer can be prevented from being affected by an external force and generated in the opening to ensure the positioning state of the semiconductor wafer, thereby avoiding the connection position of the conductive blind hole and the electrode pad to improve the electrical yield. The purpose.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

Please refer to FIGS. 2A to 2D, which are schematic diagrams showing the manufacturing method of the package substrate in which the semiconductor wafer is embedded.

2A and 2A', wherein FIG. 2A' is a top view of FIG. 2A; first, a first carrier 21 is provided having an opposite first surface 21a and a second surface 21b, and At least one rectangular opening 210 penetrating through the first surface 21a and the second surface 21b is formed; and the shape of the opening 210 may also be an angular contour such as a square or a polygon, and is not limited to the above.

Forming a plug hole 210a at four sides of the opening 210, The four plug holes 210a are all connected to the opening 210, and the outline thereof is curved.

Then, a first adhesive layer 24 is coated on the second surface 21b of the first carrier 21 to bond a second carrier 22; in the embodiment, the first adhesive layer 24 is not attached to the opening 210. On the second carrier plate 22.

The first carrier board 21 and the second carrier board 22 are both a core board having a double-sided line, a multilayer circuit board, a dielectric layer, or a metal board, and the second carrier board 22 may also be an insulating board. However, there are many types of package substrates for embedding semiconductor wafers, but they are well known in the art, and they are not technical features of the present invention, and therefore will not be described again.

As shown in FIG. 2B, a semiconductor wafer 23 is provided having an opposite active surface 23a and an inactive surface 23b. The active surface 23a has a plurality of electrode pads 231, and the semiconductor wafer 23 is placed in the opening 210. The non-active surface 23b of the semiconductor wafer 23 is bonded to the second carrier 22 by the second adhesive layer 25 such that the non-active surface 23b of the semiconductor wafer 23 is on the same side as the second surface 21b of the first carrier 21.

2C and 2C', wherein the 2C' is a top view of FIG. 2C; a fixing member 26 is placed in the filling hole 210a, and the fixing member 26 is cylindrical corresponding to the contour of the filling hole 210a. And protruding to the opening 210 so that the fixing member 26 abuts against the four sides of the semiconductor wafer 23; although the opening 210 has a gap d between the semiconductor wafer 23, the semiconductor wafer 23 is susceptible to subsequent processes. The external force is pressed to cause an offset, but by the fixing member 26 first abutting on the side of the semiconductor wafer 23, the positioning ability of the semiconductor wafer 23 in the opening 210 is effectively enhanced. It is necessary to avoid the occurrence of offset phenomena in the prior art.

As shown in FIG. 2D, a buildup structure 27 is formed on the first surface 21a of the first carrier 21 and the active surface 23a of the semiconductor wafer 23.

The build-up structure 27 includes at least one dielectric layer 271, a circuit layer 272 formed on the dielectric layer 271, and a conductive blind via 273 formed in the dielectric layer 271 and electrically connected to the circuit layer 272. A part of the conductive blind holes 273a are electrically connected to the electrode pads 231 of the semiconductor wafer 23. The circuit layer 272a of the outermost layer of the build-up structure 27 has a plurality of electrical contact pads 274, and a solder resist layer 28 is formed on the build-up structure 27, and the solder resist layer 28 has a plurality of openings 280 to correspondingly expose the respective layers. Electrical contact pads 274.

In addition, a portion of the dielectric layer 271a of the innermost layer of the build-up structure 27 is also filled in the gap d between the opening 210 and the semiconductor wafer 23 (as shown in FIG. 2C') to strengthen the semiconductor wafer 23 to the semiconductor wafer 23. In the opening 210.

In this embodiment, conductive vias (PTH) can also be formed in the first carrier 21, the second carrier 22, and the build-up structure 27, and the method for manufacturing the conductive vias is various, and the technology is It is well known in the industry, and it is not a technical feature of the present invention. Therefore, it is not shown in the drawings and will not be described in detail.

Furthermore, please refer to FIG. 2D', which is another embodiment of the first adhesive layer 24; as shown, the first adhesive layer 24 is formed on the second carrier 22 and corresponds to the opening 210. The second carrier 22 is such that the semiconductor wafer 23 bonds its inactive surface 23b to the first adhesive layer 24 in the opening 210 by the second adhesive layer 25.

Therefore, according to the above manufacturing method, the present invention is disposed on the four side edges of the opening 210 by the fixing member 26 to abut against The side of the semiconductor wafer 23 in the opening 210 is such that the fixing member 26 and the semiconductor wafer 23 are tightly fitted to each other to produce a positioning effect. Compared with the prior art, the present invention can be used to avoid subsequent processes by the fixing member 26. When the dielectric layer 271a is thermally pressed onto the first carrier 21 and the semiconductor wafer 23, the semiconductor wafer 23 is displaced, and the conductive blind via 273a is electrically connected to the electrode pad 231.

Please refer to FIG. 3 , which is another embodiment of the present embodiment. The difference is only in the position and the number of the filling holes 210 a. The other related processes and structures are the same, so the process and structure of the same part will not be repeated. In the following, only the differences will be described. Herein, the two sides of the opening 210 are provided with two filling holes 210a, and the four holes (coner) also form the filling holes 210a, so that the fixing member 26 After the filling hole 210a is provided, the positioning ability of the semiconductor wafer 23 in the opening 210 is enhanced by the number of the fixing members 26 and the abutment force around the semiconductor wafer 23.

Referring to Figures 4A to 4E together, the fixing member 26 is composed of resin, metal, ceramic, cured colloid or organic material, and has a fixed shape without heating, and the structure is columnar, spherical, Cone or irregular shape (as shown in Fig. 4E), so that the fixing member 26 is placed in the stuffing hole 210a to effectively produce an abutting effect. However, in other embodiments, the fixing member 26 may be composed of a resin mixed filler, but it needs to be heated at a low temperature to have a desired fixed shape.

According to the above method, the present invention provides a package substrate embedded with a semiconductor wafer, comprising: a first carrier 21, a semiconductor wafer 23, and a fixing member 26.

The first carrier plate 21 has a first surface 21a and a second surface 21b opposite to each other, at least one opening 210 extending through the first surface 21a and the second surface 21b, and a filling hole 210a connecting the opening 210.

The semiconductor wafer 23 is disposed in the opening 210 and has an opposite active surface 23a and an inactive surface 23b. The active surface 23a has a plurality of electrode pads 231 thereon.

The fixing member 26 is disposed in the stuffing hole 210a to fix the semiconductor wafer 23, and the semiconductor wafer 23 is positioned in the opening 210.

In addition, the package substrate further includes a second carrier 22 that is bonded to the second surface 21b of the first carrier 21 by the first adhesive layer 24, and the second surface 23b of the semiconductor wafer 23 is second. The adhesive layer 25 is bonded to the second carrier plate 22.

Moreover, the package substrate includes a build-up structure 27 disposed on the first surface 21a of the first carrier 21 and the active surface 23a of the semiconductor wafer 23.

The build-up structure 27 includes at least one dielectric layer 271, a circuit layer 272 disposed on the dielectric layer 271, and a plurality of conductive blind vias 273 disposed in the dielectric layer 271 and electrically connected to the circuit layer; The conductive via 273a is electrically connected to the electrode pad 231 of the semiconductor wafer 23, and the outermost circuit layer 272a has a plurality of electrical contact pads 274, and the build-up structure 27 is provided with a solder resist layer 28, the solder resist The layer 28 has a plurality of openings 280 therein to correspondingly expose the respective electrical contact pads 274.

5A to 5C are another embodiment of a method for fabricating a package substrate for embedding a semiconductor wafer according to the present invention, wherein FIG. 5C' is a top view of FIG. 5C; the difference from the above embodiment is only In this system There is no design of the plug hole, so the other related processes and structures are substantially the same, so they will not be described again. The differences are only described briefly, and are hereby stated.

As shown in FIG. 5A, first, a first carrier plate 51 is provided having opposite first and second surfaces 51a, 51b, and at least one opening 510 extending through the first surface 51a and the second surface 51b; A second carrier 52 is coupled to the second surface 51b of the first carrier 51 by a first adhesive layer 54.

As shown in FIG. 5B, a semiconductor wafer 53 is provided having an opposite active surface 53a and a non-active surface 53b. The active surface 53a has a plurality of electrode pads 531, and the semiconductor wafer 53 is placed in the opening 510. The non-active surface 53b of the semiconductor wafer 53 is bonded to the second carrier 52 by the second adhesive layer 55 such that the non-active surface 53b of the semiconductor wafer 53 is on the same side as the second surface 51b of the first carrier 51, and There is a gap d between it and the opening 510.

5C and 5C', wherein FIG. 5C' is a top view; a fixing member 56 is placed in the gap d to make the fixing member 56 abut against the semiconductor wafer 53; although the opening 510 and the semiconductor wafer 53 are There is a gap d, but the positioning ability of the semiconductor wafer 53 in the opening 510 is effectively enhanced by the fixing member 56 against the semiconductor wafer 53, so as to avoid the occurrence of the offset phenomenon in the prior art.

In addition, in the embodiment, the opening 510 has a curved shape and a random shape. Of course, it may have a non-angular contour such as a circular shape or an elliptical shape, and is not particularly limited. Moreover, the subsequent process can be as described in the layered structure 27 of FIG. 2D, that is, the first surface 51a of the first carrier 51 and the semiconductor wafer 53. The buildup structure 27 is formed on the active surface 53a, and therefore will not be described again.

According to this embodiment, the present invention forms another package substrate embedded with a semiconductor wafer, comprising: a first carrier plate 51, a semiconductor wafer 53, and a fixing member 56. The first carrier plate 51 has a first surface 51a and a second surface 51b opposite to each other, and an opening 510 extending through the first and second surfaces 51a, 51b. The semiconductor wafer 53 is received in the opening 510 and the opening 510 There is a gap d, and has an opposite active surface 53a and an inactive surface 53b, and the active surface 53a has a plurality of electrode pads 531; the fixing member 56 is fixed to the gap d to fix the semiconductor wafer 53.

The package substrate embedding the semiconductor wafer of the present invention and the method for manufacturing the same, mainly by placing the fixing member in the gap between the semiconductor wafer and the opening, so that the fixing member abuts against the side of the semiconductor wafer, and fixing the semiconductor wafer in the opening In order to avoid the subsequent dielectric layer thermal compression, the semiconductor wafer is offset within the opening to achieve the purpose of ensuring the positioning state of the semiconductor wafer; thereby, the conductive blind hole can be accurately connected to the electrode pad to achieve the improvement The purpose of electrical yield.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

11, 21, 51‧‧‧ first carrier board

110‧‧‧ rectangular opening

11a, 21a, 51a‧‧‧ first surface

11b, 21b, 51b‧‧‧ second surface

12, 22, 52‧‧‧ second carrier board

13, 23, 53‧‧‧ semiconductor wafers

131, 231, 531‧‧ ‧ electrode pads

13a, 23a, 53a‧‧‧ action surface

13b, 23b, 53b‧‧‧ non-active surfaces

14‧‧‧Adhesive layer

15,271,271a‧‧‧ dielectric layer

16,272,272a‧‧‧circuit layer

161, 273, 273a‧‧‧ conductive blind holes

210, 510‧‧‧ openings

210a‧‧‧fill hole

24, 54‧‧‧ first adhesive layer

25, 55‧‧‧ second adhesive layer

26, 56‧‧‧ fixing parts

27‧‧‧Additional structure

274‧‧‧Electrical contact pads

28‧‧‧ solder mask

280‧‧‧ openings

D‧‧‧ gap

E‧‧‧Offset

1A to 1D are schematic diagrams of a conventional method for embedding a package substrate of a semiconductor wafer; wherein the 1A' diagram is a top view; 2A to 2D are schematic views showing a method of fabricating a package substrate in which a semiconductor wafer is embedded; wherein, FIG. 2A' is a top view of FIG. 2A; and FIG. 2C' is a top view of FIG. 2C; 2D' is a schematic view of another embodiment of the package substrate embedding the semiconductor wafer; FIG. 4A to FIG. 4E are diagrams of the present invention; FIG. 5A to FIG. 5C are another embodiment of a method for fabricating a package substrate embedded with a semiconductor wafer; wherein FIG. 5C is a 5Cth diagram; The top view is schematic.

21‧‧‧First carrier board

210‧‧‧ openings

22‧‧‧Second carrier board

23‧‧‧Semiconductor wafer

23a‧‧‧Action surface

231‧‧‧electrode pads

26‧‧‧Fixed parts

D‧‧‧ gap

Claims (48)

A package substrate embedded with a semiconductor wafer, comprising: a first carrier plate having opposite first and second surfaces, an opening extending through the first and second surfaces, and at least one plugging hole communicating with the opening; a semiconductor wafer, the system is disposed in the opening, having an opposite active surface and a non-active surface, and the active surface has an electrode pad; a second carrier plate is coupled to the second surface of the first carrier plate and the An inactive surface of the semiconductor wafer is bonded to the second surface of the first carrier by a first adhesive layer; and a fixing member is fixed in the filling hole and a portion of the opening to be fixed The semiconductor wafer. The package substrate for embedding a semiconductor wafer according to claim 1, wherein the first carrier is a core board having a double-sided line, a multilayer circuit board, a dielectric layer, or a metal plate. The package substrate for embedding a semiconductor wafer according to claim 1, wherein the opening is square, rectangular, or polygonal. The package substrate for embedding a semiconductor wafer according to claim 3, wherein the first carrier plate has a plurality of plugging holes that communicate with the opening and the coner. The package substrate for embedding a semiconductor wafer according to claim 1, wherein the opening is a curved combination of any shape, a circle or an ellipse. The encapsulation base of the embedded semiconductor wafer as claimed in claim 1 The plate, wherein the fixing member is a resin, a metal, a ceramic, an organic material or a cured gel, and has a fixed shape without heating. A package substrate for embedding a semiconductor wafer according to claim 1, wherein the fixing member is a resin mixed filler and has a fixed shape by heating at a low temperature. The package substrate for embedding a semiconductor wafer according to claim 1, wherein the fixing member is columnar, spherical, tapered or irregular. The package substrate of the embedded semiconductor wafer of claim 1, wherein the non-active surface of the semiconductor wafer is bonded to the second carrier by a second adhesive layer. The package substrate for embedding a semiconductor wafer according to claim 1, wherein the second carrier is an insulating plate, a core plate having a double-sided circuit, a multilayer wiring board, a dielectric layer, or a metal plate. The package substrate for embedding a semiconductor wafer according to claim 1, further comprising a build-up structure disposed on the first surface of the first carrier and the active surface of the semiconductor wafer, and including at least one dielectric layer a circuit layer disposed on the dielectric layer, a conductive via hole disposed in the dielectric layer and electrically connected to the circuit layer and the electrode pad, and an electrical contact pad disposed on the build-up structure, and The build-up structure is provided with a solder resist layer, and the solder resist layer has openings to expose the electrical contact pads. The package substrate of the embedded semiconductor wafer of claim 11, wherein the dielectric layer is filled between the opening and the semiconductor wafer. A package substrate embedded with a semiconductor wafer, comprising: The first carrier has an opposite first surface and a second surface, and an opening extending through the first surface and the second surface; the semiconductor wafer is disposed in the opening and has a gap between the opening and the opening Having a plurality of opposing surfaces and a non-active surface, the active surface having a plurality of electrode pads; a second carrier plate coupled to the second surface of the first carrier and the non-active surface of the semiconductor wafer, and by a The first adhesive layer is bonded to the second surface of the first carrier; and a fixing member is fixed to the gap to fix the semiconductor wafer. The package substrate for embedding a semiconductor wafer according to claim 13 , wherein the first carrier is a core board having a double-sided line, a multilayer circuit board, a dielectric layer, or a metal plate. The package substrate for embedding a semiconductor wafer according to claim 13, wherein the opening is square, rectangular, or polygonal. The package substrate for embedding a semiconductor wafer according to claim 13 , wherein the opening is a curved combination of any shape, a circle or an ellipse. The package substrate for embedding a semiconductor wafer according to claim 13, wherein the fixing member is a resin, a metal, a ceramic, an organic material or a cured gel, and has a fixed shape without heating. The package substrate for embedding a semiconductor wafer according to claim 13, wherein the fixing member is a resin mixed filler and has a fixed shape by low-temperature heating. The package substrate for embedding a semiconductor wafer according to claim 13, wherein the fixing member is columnar, spherical, tapered or irregular. The package substrate of the embedded semiconductor wafer of claim 13, wherein the non-active surface of the semiconductor wafer is bonded to the second carrier by a second adhesive layer. The package substrate for embedding a semiconductor wafer according to claim 13 , wherein the second carrier is an insulating plate, a core plate having a double-sided circuit, a multilayer wiring board, a dielectric layer, or a metal plate. The package substrate of the embedded semiconductor wafer of claim 13 further comprising a build-up structure disposed on the first surface of the first carrier and the active surface of the semiconductor wafer, and including at least one dielectric layer a circuit layer disposed on the dielectric layer, a conductive via hole disposed in the dielectric layer and electrically connected to the circuit layer and the electrode pad, and an electrical contact pad disposed on the build-up structure, and The build-up structure is provided with a solder resist layer, and the solder resist layer has openings to expose the electrical contact pads. A package substrate for embedding a semiconductor wafer according to claim 22, wherein the dielectric layer is filled in the gap. A method of fabricating a package substrate for embedding a semiconductor wafer, comprising: providing a first carrier plate having opposite first and second surfaces and having at least one opening extending through the first and second surfaces; The first carrier plate forms at least one filling hole that communicates with the opening; Bonding a second carrier to the second surface of the first carrier; providing a semiconductor wafer on the second carrier and correspondingly located in the opening of the first carrier, and the semiconductor wafer has a relative function And a non-active surface having an electrode pad; and a plug fixing member in the filling hole and a portion of the opening to fix the semiconductor wafer. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 24, wherein the first carrier plate is a core plate having a double-sided circuit, a multilayer circuit board, a dielectric layer, or a metal plate. The method of fabricating a package substrate for embedding a semiconductor wafer according to claim 24, wherein the opening is square, rectangular, or polygonal. The method of fabricating a package substrate for embedding a semiconductor wafer according to claim 26, wherein the first carrier plate has a plurality of plug holes that communicate with the opening and the coner. The method of fabricating a package substrate for embedding a semiconductor wafer according to claim 24, wherein the opening is a curved combination of any shape, a circle or an ellipse. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 24, wherein the second carrier is an insulating plate, a core plate having a double-sided circuit, a multilayer wiring board, a dielectric layer, or a metal plate. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 24, wherein the second surface of the first carrier is provided with a first adhesive layer to bond the second carrier, and the semiconductor wafer is not The active surface is bonded to the second carrier plate by a second adhesive layer. The method of fabricating a package substrate for embedding a semiconductor wafer according to claim 24, wherein the second carrier layer is bonded to the second surface of the first carrier by a first adhesive layer, and the semiconductor wafer is not The active surface is bonded to the first adhesive layer by a second adhesive layer. The method of manufacturing a package substrate for embedding a semiconductor wafer according to claim 24, wherein the fixing member is a resin, a metal, a ceramic, an organic material or a cured gel, and has a fixed shape without heating to fix the semiconductor wafer. The method of manufacturing a package substrate for embedding a semiconductor wafer according to claim 24, wherein the fixing member is a resin mixed filler and has a fixed shape by low-temperature heating to fix the semiconductor wafer. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 24, wherein the fixing member is columnar, spherical, tapered or irregular. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 24, comprising forming a build-up structure on the first surface of the first carrier and the active surface of the semiconductor wafer, comprising at least one dielectric layer a circuit layer disposed on the dielectric layer, a conductive via hole disposed in the dielectric layer and electrically connected to the circuit layer and the electrode pad, and an electrical contact pad disposed on the build-up structure, and The build-up structure is provided with a solder resist layer, and the solder resist layer has openings to expose the electrical contact pads. The encapsulation base of the embedded semiconductor wafer as claimed in claim 35 The method of manufacturing a board, wherein the dielectric layer fills a gap between the opening and the semiconductor wafer to strengthen the semiconductor wafer in the opening. A method of fabricating a package substrate for embedding a semiconductor wafer, comprising: providing a first carrier plate having opposite first and second surfaces and having at least one opening extending through the first and second surfaces; The second surface of the first carrier is coupled to a second carrier; a semiconductor wafer is disposed on the second carrier and correspondingly located in the opening of the first carrier, and the semiconductor wafer and the opening have a gap, and the semiconductor wafer has opposing active and non-active surfaces, the active surface having an electrode pad; and a plug fastener in the gap to abut the semiconductor wafer. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 37, wherein the first carrier is a core board having a double-sided line, a multilayer circuit board, a dielectric layer, or a metal plate. The method of fabricating a package substrate for embedding a semiconductor wafer according to claim 37, wherein the opening is square, rectangular, or polygonal. The method for fabricating a package substrate for embedding a semiconductor wafer according to claim 37, wherein the opening is a curved combination of any shape, a circle or an ellipse. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 37, wherein the second carrier plate is an insulating plate and has two sides. The core board of the line, the multilayer circuit board, the dielectric layer, or the metal board. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 37, wherein the second surface of the first carrier is provided with a first adhesive layer to bond the second carrier, and the semiconductor wafer is inactive. The surface is bonded to the second carrier by a second adhesive layer. The method of fabricating a package substrate for embedding a semiconductor wafer according to claim 37, wherein the second carrier is bonded to the second surface of the first carrier by a first adhesive layer, and the semiconductor wafer is not The active surface is bonded to the first adhesive layer by a second adhesive layer. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 37, wherein the fixing member is a resin, a metal, a ceramic, an organic material or a cured gel, and has a fixed shape without heating to fix the semiconductor wafer. The method of fabricating a package substrate for embedding a semiconductor wafer according to claim 37, wherein the fixing member is a resin mixed filler and has a fixed shape by low temperature heating to fix the semiconductor wafer. The method of manufacturing a package substrate for embedding a semiconductor wafer according to claim 37, wherein the fixing member is columnar, spherical, tapered or irregular. The method for manufacturing a package substrate for embedding a semiconductor wafer according to claim 37, comprising forming a build-up structure on the first surface of the first carrier and the active surface of the semiconductor wafer, comprising at least one dielectric layer a circuit layer disposed on the dielectric layer, disposed in the dielectric layer Electrically connecting the circuit layer and the conductive blind via of the electrode pad, and the electrical contact pad disposed on the build-up structure, and the build-up structure is provided with a solder resist layer, and the solder resist layer has an opening The electrical contact pad is exposed. The method of claim 47, wherein the dielectric layer is filled in the gap to strengthen the semiconductor wafer in the opening.