TWI548098B - Semiconductor device and manufacturing method of the same - Google Patents

Description

Semiconductor component and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same.

As the degree of integration of semiconductor components increases, the component size continues to shrink. The size of each component in the component is getting smaller and smaller, and the distance between them is getting closer and closer. In general, the components are separated from each other by an isolation structure. The more commonly used isolation structure today is shallow trench isolation (STI). In the memory element, a suitable shallow trench isolation structure can improve the gate coupling ratio (GCR), reduce interference between adjacent memory elements, and at the same time provide good reliability of the memory element.

The present invention provides a semiconductor device and a method of manufacturing the same, which are capable of improving a gate coupling ratio, reducing interference between adjacent memory elements, and providing semiconductor devices with good reliability.

The invention provides a semiconductor component comprising a substrate and a plurality of first dielectrics a layer, a plurality of first conductor layers, and a plurality of isolation structures. The substrate has a plurality of trenches. The first dielectric layer is respectively disposed on the substrate between two adjacent trenches. The first conductor layer is disposed on the first dielectric layer. The isolation structure is located in the trench, and each isolation structure includes a flat region and a recessed region, and an upper surface of the flat region is higher than an upper surface of the first dielectric layer.

According to an embodiment of the invention, the recessed area is U-shaped, V-shaped, ladder-shaped, nipple-shaped, W-shaped or stepped.

According to an embodiment of the invention, the bottom surface of the recessed region is lower than the upper surface of the flat region and higher than the upper surface of the first dielectric layer.

According to an embodiment of the invention, the semiconductor device further includes: a second conductor layer and a second dielectric layer. The second conductor layer is disposed on the first conductor layer and the isolation structure; the second dielectric layer is disposed between the first conductor layer and the second conductor layer, and between the isolation structure and the second conductor layer between.

The present invention further provides a method of fabricating a semiconductor device, comprising: sequentially forming a first dielectric layer and a first conductor layer on a substrate. The first conductor layer and the first dielectric layer are patterned, and a plurality of trenches are formed in the substrate. A plurality of layers of isolation material are formed in the trench. A portion of the layer of isolation material is removed to form a plurality of isolation layers that expose sidewalls of the first conductor layer. A portion of the isolation layer is removed to form a plurality of isolation structures, each isolation structure including a flat region and a recessed region.

According to an embodiment of the invention, the step of removing a portion of the isolation layer includes forming a first liner spacer on a sidewall of each of the first conductor layers. The isolation layer is etched by using the first liner spacer as a mask. Removing the first liner gap wall.

According to an embodiment of the invention, the method of etching the isolation layer includes a dry etching method.

According to an embodiment of the invention, the method of removing the first liner spacer includes a wet etching method.

According to an embodiment of the invention, the method of fabricating the semiconductor device further includes forming a second liner spacer on a sidewall of the first liner spacer wall before removing the first liner spacer. Part of the isolation layer is etched by using the first liner spacer and the second liner spacer as a mask. The first liner spacer and the second liner spacer are removed.

According to an embodiment of the invention, a method of removing a portion of the above-described spacer material layer includes a dry etching method.

The semiconductor device of the present invention and the method of manufacturing the same can improve the gate coupling ratio, reduce interference between adjacent floating gates, and have good reliability of the semiconductor element.

The above described features and advantages of the invention will be apparent from the following description.

102, 102a‧‧‧ base

104, 104a‧‧‧ first dielectric layer

106, 106a‧‧‧ first conductor layer

108‧‧‧ Ditch

110‧‧‧Separation material layer

110a, 710b, 710c‧‧‧ isolation layer

110b, 210b, 310b, 410b, 510b, 610b, 710d‧‧‧ isolation structure

111a‧‧‧flat area

111b, 611b, 711b‧‧‧ recessed area

112‧‧‧ lining material layer

112a, 618a, 620a, 718a, 720a‧‧‧ lining spacer

114‧‧‧Second dielectric layer

116‧‧‧Second conductor layer

Θ‧‧‧ angle

1A-1H are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

2 to 5 are schematic cross-sectional views showing a semiconductor device in accordance with another embodiment of the present invention.

6A-6B are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

7A-7D are cross-sectional views showing a manufacturing process of a semiconductor device according to still another embodiment of the present invention.

1A-1H are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

Referring to FIG. 1A, a first dielectric layer 104 is formed on the substrate 102. The substrate 102 is, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor over insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide. The substrate 102 may have a doping, and the doping of the substrate 102 may be a P-type or an N-type. The P-type doping may be a Group IIIA ion, such as a boron ion. The N-type doping may be a Group VA ion such as arsenic or phosphorus.

The first dielectric layer 104 can be composed of a single material layer. The single material layer is, for example, a low dielectric constant material or a high dielectric constant material. The low dielectric constant material is a dielectric material having a dielectric constant of less than 4, such as ruthenium oxide or ruthenium oxynitride. High dielectric constant material having a dielectric constant higher than the dielectric material 4 is, for example, hafnium aluminum oxide (HfAlO), hafnium oxide (HfO _2), aluminum oxide (Al ₂ O ₃₎ or silicon nitride (Si ₃ N ₄ ). The first dielectric layer 104 may also be a two-layer stacked structure or a multi-layer stacked structure. The two-layer stacked structure is, for example, a two-layer stacked structure (represented by a low dielectric constant material/high dielectric constant material) composed of a low dielectric constant material and a high dielectric constant material, such as yttrium oxide/yttrium oxide yttrium oxide.矽/铪 铪 or 矽/矽 nitride. The multilayer stacked structure is, for example, a multilayer stack structure composed of a low dielectric constant material, a high dielectric constant material, and a low dielectric constant material (represented by a low dielectric constant material/high dielectric constant material/low dielectric constant material), For example, yttria/tantalum nitride/yttria or yttrium oxide/alumina/yttria. The method of forming the first dielectric layer 104 is, for example, a thermal oxidation method or a chemical vapor deposition method.

Thereafter, a first conductor layer 106 is formed on the first dielectric layer 104. The material of the first conductor layer 106 is, for example, a stacked layer of a doped polysilicon, a polycrystalline metal or a combination thereof, a metal layer or an applicable conductor, and the formation method is, for example, a chemical vapor deposition method or a physical vapor deposition method.

Then, referring to FIG. 1B, the first conductor layer 106 and the first dielectric layer 104 are patterned to form a first conductor layer 106a and a first dielectric layer 104a, and a plurality of trenches 108 are formed in the substrate 102a. The patterning method can form a patterned mask layer (not shown) on the first conductor layer 106. The patterned mask layer can be a single material layer or a two layer material layer, and the patterned mask layer is, for example, a patterned photoresist layer. Next, an etching process is performed by patterning the mask layer as a mask, and the etching process includes an anisotropic etching method, such as a dry etching method. After that, the patterned mask layer is removed. The method of removing the patterned mask layer 105 is, for example, a dry removal method, a wet removal method, or a combination thereof.

Thereafter, referring to FIG. 1C, an isolation material layer 110 is formed in the trench 108. The method of forming the isolation material layer 110 may be to form an insulating material on the trench 108 and the first conductor layer 106a. The insulating material is, for example, cerium oxide or borophosphon glass, and the method of forming it is, for example, a chemical vapor deposition method. Thereafter, the insulating material on the first conductor layer 106a is removed by chemical mechanical polishing (CMP) or etch back.

Then, referring to FIGS. 1C and 1D, an etch back process is performed to remove a portion of the isolation material layer 110 in the trench 108 to form the isolation layer 110a. The upper surface of the isolation layer 110a is lower than the upper surface of the first conductor layer 106a and higher than the upper surface of the first dielectric layer 104a, and the sidewall of the first conductor layer 106a is exposed. In one embodiment, the distance between the upper surface of the isolation layer 110a and the upper surface of the first dielectric layer 104a is between about 200 angstroms and 500 angstroms. A method of removing a portion of the isolation material layer 110 is, for example, a dry etching method.

Next, referring to FIG. 1E, a lining material layer 112 is formed on the substrate 102a to cover the first conductor layer 106a, the sidewall of the first conductor layer 106a, and the isolation material layer 110a. The material of the lining material layer 112 is different from the constituent material of the isolating material layer 110. The lining material layer 112 may be a single layer or multiple layers. The material of the lining material layer 112 includes an oxide, a nitride, an oxynitride, or an oxynitride such as cerium oxide, cerium nitride, cerium oxynitride or cerium oxynitride. The formation method of the lining material layer 112 is, for example, a low temperature thermal oxidation method, a thermal oxidation method, an atomic layer deposition method, or a chemical vapor phase vapor deposition method. The thickness of the lining material layer 112 is, for example, from 1 nm to 20 nm.

Thereafter, referring to FIG. 1F, an anisotropic etching process is performed to remove a portion of the liner material layer 112, and a liner spacer 112a is formed on the sidewall of each of the first conductor layers 106a. Then, using the spacer spacer 112a as a mask, the etchback process is performed again, and the shift process is performed. In addition to the isolation layer 110a, an isolation structure 110b is formed. The method of removing the isolation layer 110a is, for example, a dry etching method.

Next, referring to FIG. 1G, the liner spacer 112a is removed to expose the upper surface of the isolation structure 110b in the trench 108. The method of removing the spacer spacer 112a includes a wet etching method, for example, using hydrofluoric acid. Each of the isolation structures 110b has a flat region 111a and a recessed region 111b. The upper surface of the flat region 111a is higher than the upper surface of the first dielectric layer 104a by 200 angstroms to 500 angstroms; the bottom surface of the recessed region 111b is lower than the upper surface of the flat region 111a and higher than the upper surface of the first dielectric layer 104a. In one embodiment, the recessed region 111b has a width of 2 nm to 15 nm and has a side wall adjacent to the flat region 111a, the angle θ of the sidewall from the upper surface of the flat region 111a being 5 to 178 degrees.

Thereafter, referring to FIG. 1H, a second dielectric layer 114 and a second conductor layer 116 are sequentially formed on the substrate 102a. The second dielectric layer 114 may be a single layer or a plurality of layers, and the material thereof includes ruthenium oxide, tantalum nitride or other insulating materials, and the formation method is, for example, chemical vapor deposition. The material of the second conductor layer 116 may be the same as or different from the first conductor layer 106a, for example, a stacked layer of a doped polysilicon, a polycrystalline metal or a combination thereof, a metal layer or an applicable conductor, which is formed by, for example, utilizing chemistry. Vapor deposition or physical vapor deposition.

In other embodiments of the present invention, the recessed regions may be formed in a plurality of types, and in addition to the U-shape shown in FIG. 1G, it may be formed such as a V-shape by controlling etching conditions, thickness of the spacer spacers, and the like (FIG. 2). , ladder type (Figure 3), nipple type (Figure 4), W type (Figure 5) and other types.

6A-6B are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to another embodiment of the present invention.

Referring to FIG. 6A and FIG. 6B, in another embodiment of the present invention, the first liner spacer wall 112a, the second liner spacer wall 618a, and the third liner spacer wall 620a may be sequentially formed on the sidewall of the first conductor layer 106a. And after forming the first, second, and third liner spacers 112a, 618a, and 620a, the isolation layer is etched, respectively, to form a stepped isolation structure. More specifically, a first liner spacer 112a is formed on the sidewall of the first conductor layer 106a, and the spacer is etched with the first liner spacer 112a as a mask. Next, a second liner spacer wall 618a is formed on the sidewall of the first liner spacer 112a, and the first liner spacer wall 112a and the second liner spacer wall 618a are used as a mask to etch the isolation layer again. Thereafter, a third liner spacer 620a is formed on the sidewall of the second liner spacer 618a, and the first liner spacer 112a, the second liner spacer 618a, and the third liner spacer 620a are used as a mask to re-etch the chamber. The isolation layer. Next, the first liner spacer 112a, the second liner spacer 618a, and the third liner spacer 620a are removed to form an isolation structure 610b having a stepped recessed region 611b (FIG. 6B).

7A-7D are schematic cross-sectional views showing a manufacturing process of a semiconductor device according to still another embodiment of the present invention.

Referring to FIG. 7A, in another embodiment, a first liner spacer 112a is formed on a sidewall of the first conductor layer 106a, and the first liner spacer 112a is used as a mask to etch the isolation layer to form a first step. The isolation layer 710b of the recessed region.

Next, referring to Figures 7A and 7B, the first liner spacer 112a is removed. Re-forming the second liner spacer 718a on the sidewall of the first conductor layer 106a, and second The spacer spacer 718a is a mask, and the isolation layer 710b is etched again to form an isolation layer 710c having a two-step recess.

Thereafter, referring to Figures 7B and 7C, the second liner spacer 718a is removed. The third liner spacer 720a is formed again on the sidewall of the first conductor layer 106a, and the spacer layer 710c is etched again with the third liner spacer 720a as a mask to form the isolation structure 710d having the third-order recess.

Next, referring to FIGS. 7C and 7D, the third liner spacer 720a is removed to expose the isolation structure 710d having the third-order stepped recess 711b.

Referring again to FIG. 1H, the semiconductor device of the embodiment of the present invention is disposed on the substrate 102 and includes a first conductor layer 106a, a first dielectric layer 104a, an isolation structure 110b, a second dielectric layer 114, and a second conductor layer 116.

The substrate 102 has a plurality of trenches 108. A plurality of first dielectric layers 104a are respectively disposed on the substrate 102 between the adjacent two trenches 108. The first dielectric layer 104a can serve as a tunneling dielectric layer. The first conductor layer 106a is located on the first dielectric layer and can serve as a floating gate of the semiconductor component.

The second conductor layer 116 covers the first conductor layer 106a and covers the isolation structure 110b, which can serve as a control gate of the semiconductor element. The second dielectric layer 114 is located between the first conductor layer 106a and the second conductor layer 116 and between the isolation structure 110b and the second conductor layer 116, and can serve as a dielectric layer between the gates.

A plurality of isolation structures 110b are located in the trenches 108 of the substrate 102a on both sides of the first conductor layer 106a to isolate adjacent two components. Each of the isolation structures 110b includes a flat region 111a and a recessed region 111b, and an upper surface of the flat region 111a is higher than the first surface The upper surface of the dielectric layer 104a is 200 angstroms to 500 angstroms, and the bottom surface of the recessed region 111b is lower than the upper surface of the flat region 111a and higher than the upper surface of the first dielectric layer 104a. The recessed region 111b may be U-shaped, V-shaped, ladder-shaped, nipple-shaped, W-shaped or stepped, has a width of 2 nm to 15 nm, and has a side wall adjacent to the flat region 111a. The angle θ between the side wall and the upper surface of the flat region 111a is 5 degrees to 178 degrees.

In summary, the present invention can form an isolation structure having a recessed region by forming a spacer spacer and an etching process in the process, thereby increasing the gate coupling ratio, reducing interference between adjacent floating gates, and simultaneously making components. Has good reliability. And the process of the present invention can be integrated with existing processes.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

102a‧‧‧Base

104a‧‧‧First dielectric layer

106a‧‧‧First conductor layer

108‧‧‧ Ditch

110b‧‧‧Isolation structure

111a‧‧‧flat area

111b‧‧‧ recessed area

Θ‧‧‧ angle

Claims (9)

A semiconductor device comprising: a substrate having a plurality of trenches; a plurality of first dielectric layers respectively disposed on the substrate between two adjacent trenches; a plurality of first conductor layers, configured On the first dielectric layer; and a plurality of isolation structures in the trench, each isolation structure including a flat region and a recessed region, the upper surface of the flat region being higher than the first dielectric layer An upper surface, wherein a bottom surface of the recessed region is lower than an upper surface of the flat region and higher than an upper surface of the first dielectric layer. The semiconductor device according to claim 1, wherein the recessed region is U-shaped, V-shaped, ladder-shaped, nipple-shaped, W-shaped or stepped. The semiconductor device of claim 1, further comprising: a second conductor layer disposed on the first conductor layer and the isolation structure; and a second dielectric layer disposed on the first conductor Between the layer and the second conductor layer and between the isolation structure and the second conductor layer. A method of fabricating a semiconductor device, comprising: sequentially forming a first dielectric layer and a first conductor layer on a substrate; patterning the first conductor layer and the first dielectric layer, and forming in the substrate a plurality of trenches; forming a plurality of layers of insulating material in the trenches; Removing a portion of the isolation material layer to form a plurality of isolation layers, exposing sidewalls of the first conductor layer; and removing portions of the isolation layer to form a plurality of isolation structures, each isolation structure including a flat region And a recessed region, wherein a bottom surface of the recessed region is lower than an upper surface of the flat region and higher than an upper surface of the first dielectric layer. The method of manufacturing a semiconductor device according to claim 4, wherein the removing the portion of the isolation layer comprises: forming a first liner spacer on a sidewall of each of the first conductor layers; The liner spacer is a mask, the isolation layer is etched; and the first liner spacer is removed. The method of manufacturing a semiconductor device according to claim 5, wherein the method of etching the spacer layer comprises a dry etching method. The method of manufacturing a semiconductor device according to claim 5, wherein the method of removing the first liner spacer comprises a wet etching method. The method for manufacturing a semiconductor device according to claim 5, further comprising: forming a second liner spacer on a sidewall of the first liner spacer before removing the first liner spacer; The first liner spacer and the second liner spacer are masks, etching the isolation layer; and removing the first liner spacer and the second liner spacer. The method of manufacturing a semiconductor device according to claim 4, wherein the method of removing a portion of the spacer material layer comprises a dry etching method.