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RU2378683C2 - Method of parallel boolean summation of user analogue signals of components equivalent to binary number system - Google Patents

Method of parallel boolean summation of user analogue signals of components equivalent to binary number system Download PDF

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RU2378683C2
RU2378683C2 RU2006144610/09A RU2006144610A RU2378683C2 RU 2378683 C2 RU2378683 C2 RU 2378683C2 RU 2006144610/09 A RU2006144610/09 A RU 2006144610/09A RU 2006144610 A RU2006144610 A RU 2006144610A RU 2378683 C2 RU2378683 C2 RU 2378683C2
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logical
analog signal
analogue signal
sum
level
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RU2006144610/09A
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RU2006144610A (en
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Лев Петрович Петренко (UA)
Лев Петрович Петренко
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Лев Петрович Петренко
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Abstract

FIELD: physics; computer engineering.
SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out arithmetic operations in position-sign codes. The method involves the following: from input analogue signals ni and mi in the ith bit, analogue signals of the first intermediate logical sum S1 i through logical functions OR1 and a second intermediate logic sum S2 i through logical functions AND1; a positive derived analogue signal +S3 i is formed through logical function AND2 from a pre-modified function NOT1 on the level of the analogue signal S 1 i and the first intermediate sum S1 i-1 of the (i-1)th bit, and a conditionally negative derived analogue signal -S3 i is formed through logical function AND3 from analogue signal S1 i and a pre-modified function NOT2 on the level of analogue signal S1 i-1 of the first intermediate sum S1 i-1 of the (i-1)th bit; analogue signal +S3 i is combined with analogue signal +S2 i through logical function OR2 and the level of the analogue signal of the resultant argument +S*i is modified, which corresponds to the procedure of removing the active logical zero, which forms if the composite analogue signal +S*i and the conditionally negative derived analogue signal -S3 i simultaneously assume active analogue signal levels; the active analogue signal level is removed when the conditionally negative derived analogue signal -S3 i coincides with the analogue signal of the second intermediate sum +S2 i.
EFFECT: faster operation.
5 dwg

Description

Текст описания приведен в факсимильном виде.

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The text of the description is given in facsimile form.
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Claims (1)

Способ параллельного логического суммирования аналоговых сигналов слагаемых эквивалентных двоичной системе счисления, включающий поразрядное выполнение преобразований аналоговых сигналов слагаемых [ni] и [mi], которые принимают либо условно высокий или активный уровень, либо условно низкий сигнал или неактивный уровень, при этом из входных аналоговых сигналов ni и mi в «i» разряде формируют аналоговые сигналы первой промежуточной логической суммы S1 i, посредством логических функций f1(})-ИЛИ и второй промежуточной логической суммы S2 i, посредством логических функций f1(&)-И, из которых формируют аналоговый сигнал Si результата логического суммирования, отличающийся тем, что аналоговый сигнал первой промежуточной логической суммы S1 i логически дифференцируют с одновременным формированием производных аналоговых сигналов положительного +S3 i и условно отрицательного -S3 i, при этом положительный производный аналоговый сигнал +S3 i формируют посредством логической функции f2(&)-И из предварительно измененного функцией f1(&)-HE по уровню аналогового сигнала S 1 i первой промежуточной суммы S1 i «i» разряда и первой промежуточной суммы S1 i-1 «i-1» разряда, а условно отрицательный производный аналоговый сигнал -S3 i формируют посредством логической функции f3(&)-И из аналогового сигнала первой промежуточной суммы S1 i «i» разряда и предварительно измененного функцией f2(&)-HE по уровню аналогового сигнала S 1 i-1 первой промежуточной суммы S1 i-1 «i-1» разряда, после чего в «i» разряде положительный производный аналоговый сигнал +S1 i совмещают с аналоговым сигналом второй промежуточной суммы +S2 i посредством логической функции f2(})-ИЛИ и выполняют изменение уровня аналогового сигнала результирующего аргумента +S*i, что соответствует процедуре удаления активного логического нуля f1(+1/-1→0), которые формируется, если совмещенный аналоговый сигнал +S*i и условно отрицательный производный аналоговые сигналы -S3 i принимают одновременно активные уровни аналогового сигнала, при этом выполняют изменение (удаление) активного уровня аналогового сигнала f2(+1/-1→0) при совпадении условно отрицательного производного аналогового сигнала S3 i с аналоговым сигналом второй промежуточной
суммы +S2 i в соответствии с математической моделью вида
Figure 00000019

где
Figure 00000020

логические функции f1(&)-И и f1(})-ИЛИ;
Figure 00000021

функциональная структура удаления активного логического нуля при одновременно активных аналоговых сигналов;
«=& 1=» - логическая функция изменения уровня аналогового сигнала f1(&)-НЕ. A method for parallel logical summation of analog signals of terms equivalent to the binary number system, including bitwise conversion of analog signals of the terms [n i ] and [m i ], which take either a conditionally high or active level, or a conditionally low signal or inactive level, while from the input analog signals n i and m i in the "i" category form the analog signals of the first intermediate logical sum S 1 i , through the logical functions f 1 (}) - OR and the second intermediate logical sum S 2 i , by means of the logical functions f 1 (&) - And, from which the analog signal Si of the logical summation result is formed, characterized in that the analog signal of the first intermediate logical sum S 1 i is logically differentiated with the simultaneous formation of the derived analog signals of positive + S 3 i and conditionally negative -S 3 i , while the positive derivative analog signal + S 3 i is formed by the logical function f 2 (&) - And from the previously changed function f 1 ( & ) -HE according to the level of the analog signal S 1 i of the first intermediate the exact sum S 1 i “i” of the discharge and the first intermediate sum S 1 i-1 “i-1” of the discharge, and the conditionally negative derivative analog signal -S 3 i is formed by the logical function f 3 (&) - And from the analog signal of the first the intermediate sum S 1 i “i” of the discharge and previously changed by the function f 2 ( & ) -HE according to the level of the analog signal S 1 i-1 of the first intermediate sum S 1 i-1 of the “i-1” discharge, and then to the “i” the discharge, the positive derived analog signal + S 1 i is combined with the analog signal of the second intermediate sum + S 2 i by means of a logical function f 2 (}) - OR and change the level of the analog signal of the resulting argument + S * i , which corresponds to the procedure for removing the active logical zero f 1 (+ 1 / -1 → 0), which is formed if the combined analog signal + S * i and conditionally negative derivative, the analog signals -S 3 i simultaneously receive active levels of the analog signal, while changing (deleting) the active level of the analog signal f 2 (+ 1 / -1 → 0) when the conditionally negative derivative of the analog signal S 3 i coincides with analog signal second prom diate
sums + S 2 i in accordance with a mathematical model of the form
Figure 00000019

Where
Figure 00000020

logical functions f 1 (&) - AND and f 1 (}) - OR;
Figure 00000021

functional structure for removing active logical zero with simultaneously active analog signals;
"= & 1 =" is a logical function of changing the level of the analog signal f 1 ( & ) -НЕ.
RU2006144610/09A 2006-12-15 2006-12-15 Method of parallel boolean summation of user analogue signals of components equivalent to binary number system RU2378683C2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2446443C1 (en) * 2010-07-22 2012-03-27 Лев Петрович Петренко METHOD FOR PERFORMING BOOLEAN SUMMATION OF POSITION ARGUMENTS OF ANALOGUE SIGNALS OF TERMS [ni]f(2n) AND [mi]f(2n) OF PARTIAL PRODUCTS IN PRE-ADDER fΣ[ni]&[mi](2n) OF PARALLEL-SERIAL MULTIPLIER fΣ(Σ) USING DOUBLE BOOLEAN DIFFERENTIATION d/dn+ AND d/dn- OF INTERMEDIATE SUMS AND GENERATION OF RESULTANT SUM [Si]f(2n) IN POSITION FORMAT (RUSSIAN LOGIC)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU997032A1 (en) * 1981-07-22 1983-02-15 Таганрогский радиотехнический институт им.В.Д.Калмыкова Device for adding in redundancy binary notation
SU1594523A1 (en) * 1986-01-13 1990-09-23 Таганрогский радиотехнический институт им.В.Д.Калмыкова Parallel adder
RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU997032A1 (en) * 1981-07-22 1983-02-15 Таганрогский радиотехнический институт им.В.Д.Калмыкова Device for adding in redundancy binary notation
SU1594523A1 (en) * 1986-01-13 1990-09-23 Таганрогский радиотехнический институт им.В.Д.Калмыкова Parallel adder
RU2069009C1 (en) * 1993-12-07 1996-11-10 Научно-исследовательский институт многопроцессорных вычислительных систем при Таганрогском радиотехническом институте им.В.Д.Калмыкова Adding device

Non-Patent Citations (1)

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Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2446443C1 (en) * 2010-07-22 2012-03-27 Лев Петрович Петренко METHOD FOR PERFORMING BOOLEAN SUMMATION OF POSITION ARGUMENTS OF ANALOGUE SIGNALS OF TERMS [ni]f(2n) AND [mi]f(2n) OF PARTIAL PRODUCTS IN PRE-ADDER fΣ[ni]&[mi](2n) OF PARALLEL-SERIAL MULTIPLIER fΣ(Σ) USING DOUBLE BOOLEAN DIFFERENTIATION d/dn+ AND d/dn- OF INTERMEDIATE SUMS AND GENERATION OF RESULTANT SUM [Si]f(2n) IN POSITION FORMAT (RUSSIAN LOGIC)

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