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JPH0658924B2 - 半導体デバイスパッケージ及びその製造方法 - Google Patents

半導体デバイスパッケージ及びその製造方法

Info

Publication number
JPH0658924B2
JPH0658924B2 JP61097803A JP9780386A JPH0658924B2 JP H0658924 B2 JPH0658924 B2 JP H0658924B2 JP 61097803 A JP61097803 A JP 61097803A JP 9780386 A JP9780386 A JP 9780386A JP H0658924 B2 JPH0658924 B2 JP H0658924B2
Authority
JP
Japan
Prior art keywords
electrode
chip
semiconductor device
metal layer
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP61097803A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61251047A (ja
Inventor
カルロ・コネッティ・デ・マルティース
Original Assignee
エツセジ−エツセ ミクロエレツトロニカソチエタ ペル アノニマ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by エツセジ−エツセ ミクロエレツトロニカソチエタ ペル アノニマ filed Critical エツセジ−エツセ ミクロエレツトロニカソチエタ ペル アノニマ
Publication of JPS61251047A publication Critical patent/JPS61251047A/ja
Publication of JPH0658924B2 publication Critical patent/JPH0658924B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10W72/90—
    • H10W76/157—
    • H10W95/00—

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP61097803A 1985-04-26 1986-04-26 半導体デバイスパッケージ及びその製造方法 Expired - Fee Related JPH0658924B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT20504A/85 1985-04-26
IT8520504A IT1215268B (it) 1985-04-26 1985-04-26 Apparecchio e metodo per il confezionamento perfezionato di dispositivi semiconduttori.

Publications (2)

Publication Number Publication Date
JPS61251047A JPS61251047A (ja) 1986-11-08
JPH0658924B2 true JPH0658924B2 (ja) 1994-08-03

Family

ID=11167929

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61097803A Expired - Fee Related JPH0658924B2 (ja) 1985-04-26 1986-04-26 半導体デバイスパッケージ及びその製造方法

Country Status (6)

Country Link
JP (1) JPH0658924B2 (de)
DE (1) DE3614087C2 (de)
FR (1) FR2581247B1 (de)
GB (1) GB2174543B (de)
IT (1) IT1215268B (de)
NL (1) NL193513C (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4959706A (en) * 1988-05-23 1990-09-25 United Technologies Corporation Integrated circuit having an improved bond pad
DE69420841T2 (de) * 1994-07-13 2000-01-05 United Microelectronics Corp., Hsinchu Verfahren zur Eliminierung des Antenneneffekts während der Fabrikation
DE69426293T2 (de) * 1994-07-13 2001-04-05 United Microelectronics Corp., Hsinchu Verfahren zur Reduzierung des Antenneneffekts während der Fabrikation
US6888240B2 (en) 2001-04-30 2005-05-03 Intel Corporation High performance, low cost microelectronic circuit package with interposer
US6894399B2 (en) 2001-04-30 2005-05-17 Intel Corporation Microelectronic device having signal distribution functionality on an interfacial layer thereof
US7071024B2 (en) * 2001-05-21 2006-07-04 Intel Corporation Method for packaging a microelectronic device using on-die bond pad expansion
US7183658B2 (en) 2001-09-05 2007-02-27 Intel Corporation Low cost microelectronic circuit package
EP1424730B1 (de) * 2002-11-29 2008-10-08 Infineon Technologies AG Halbleiterchip mit Anschlusskontaktflächen und Anordnung eines solchen Halbleiterchips auf einem Träger

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3458925A (en) * 1966-01-20 1969-08-05 Ibm Method of forming solder mounds on substrates
FR1569479A (de) * 1967-07-13 1969-05-30
NL169122C (nl) * 1970-02-26 1982-06-01 Toyo Electronics Ind Corp Halfgeleiderelement, omvattende een halfgeleiderplaatje met een door een isolerende laag bedekt hoofdvlak en met elektroden die zich ononderbroken uitstrekken over delen van de isolerende laag en aangrenzende delen van zijvlakken van het halfgeleiderplaatje, alsmede werkwijze voor het bevestigen van het halfgeleiderelement op een van aansluitklemmen voorziene montageplaat.
JPS5420120B2 (de) * 1971-12-23 1979-07-20
CA954635A (en) * 1972-06-06 1974-09-10 Microsystems International Limited Mounting leads and method of fabrication
JPS5091269A (de) * 1973-12-12 1975-07-21
JPS5851425B2 (ja) * 1975-08-22 1983-11-16 株式会社日立製作所 ハンドウタイソウチ
JPS5445574A (en) * 1977-09-17 1979-04-10 Tdk Corp Connection method of integrated circuit

Also Published As

Publication number Publication date
GB2174543A (en) 1986-11-05
FR2581247A1 (fr) 1986-10-31
IT1215268B (it) 1990-01-31
DE3614087C2 (de) 1999-05-06
DE3614087A1 (de) 1986-10-30
IT8520504A0 (it) 1985-04-26
FR2581247B1 (fr) 1991-03-29
NL8601073A (nl) 1986-11-17
JPS61251047A (ja) 1986-11-08
GB2174543B (en) 1988-11-16
GB8609260D0 (en) 1986-05-21
NL193513B (nl) 1999-08-02
NL193513C (nl) 1999-12-03

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees