JP2010034481A - Method of manufacturing semiconductor device, and semiconductor device - Google Patents

Abstract

A semiconductor device manufacturing method capable of performing sufficient heat treatment while suppressing deterioration of the surface state of a SiC wafer, and a semiconductor device having excellent characteristics by being manufactured by the manufacturing method. provide.
A method of manufacturing a MOSFET as a semiconductor device includes a step of preparing a wafer 3 made of silicon carbide, and an activation annealing step of performing activation annealing by heating the wafer 3. In the activation annealing step, the wafer 3 is heated in a state where the SiC substrate 61 is disposed along the main surface of the wafer 3.
[Selection] Figure 10

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more specifically, a semiconductor device manufacturing method including a step of performing heat treatment by heating a wafer having at least one main surface made of silicon carbide, and the method. The present invention relates to a manufactured semiconductor device.

  2. Description of the Related Art In recent years, silicon carbide (SiC) is being adopted as a material for forming semiconductor devices in order to enable semiconductor devices such as transistors and diodes to have higher withstand voltage, lower loss, and use under high temperature environments. . Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon (Si) that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  On the other hand, in general, a method for manufacturing a semiconductor device is implemented by combining a step of manufacturing a wafer including a semiconductor layer and a step of heat-treating the wafer. More specifically, in the method for manufacturing a semiconductor device, for example, the following steps are employed. First, impurities are introduced into a semiconductor wafer by ion implantation to produce a wafer having an ion implantation region. Thereafter, the wafer is subjected to heat treatment (activation annealing) for the purpose of activating the introduced impurities.

  And when silicon carbide is employ | adopted as a material which comprises a semiconductor device, it is necessary to implement this activation annealing at high temperature, for example, 1600 degreeC or more. However, when heat treatment at such a high temperature is performed, silicon may be detached from the surface and a layer having a high carbon concentration (carbon rich layer) may be formed in the surface layer portion. In addition, there may be a phenomenon in which the surface roughness of the wafer becomes large (surface roughness) or a step (step bunching) in which the steps formed by the surface roughness are combined to form a large step. Such deterioration of the surface condition adversely affects the characteristics of a semiconductor device manufactured using the wafer. In other words, when silicon carbide is employed as a material constituting the semiconductor device, there is a problem that the heat treatment of the wafer performed in the manufacturing process deteriorates the surface state of the wafer and adversely affects the characteristics of the semiconductor device.

On the other hand, a method has been proposed in which a cap layer is formed by carbonizing a resist on the surface of a silicon carbide wafer and then the wafer is activated (activation annealing) (see, for example, Patent Document 1). Thereby, the escape of Si from the SiC surface due to the activation treatment is prevented.
JP 2007-281005 A

  However, for example, when activation annealing is performed on a wafer having at least one main surface made of silicon carbide (hereinafter referred to as a SiC wafer), a sufficient activation rate (for example, an activation rate of 90% or more) is achieved. In order to achieve this, it is necessary to heat the SiC wafer to a high temperature of 1700 ° C. or higher. On the other hand, the upper limit of the temperature at which SiC sublimation can be suppressed by the cap layer formed by carbonizing the resist is 1700 ° C. That is, in the method of manufacturing a semiconductor device including a process such as activation annealing of a SiC wafer, there is a problem that it is difficult to perform sufficient heat treatment while suppressing deterioration of the surface state of the SiC wafer.

  Accordingly, an object of the present invention is to provide a semiconductor device manufacturing method capable of performing sufficient heat treatment while suppressing deterioration of the surface state of the SiC wafer, and excellent characteristics by being manufactured by the manufacturing method. It is providing the semiconductor device which has this.

  A method for manufacturing a semiconductor device according to the present invention includes a step of preparing a wafer having at least one main surface made of silicon carbide, and a step of heat-treating the wafer by heating the wafer. In the step of heat-treating the wafer, a sublimation suppressing member including at least one selected from the group consisting of silicon carbide, tantalum carbide, tungsten carbide, and carbon is disposed along the one main surface. In this state, the wafer is heated.

  The present inventor has made various studies on a policy capable of performing heat treatment at a sufficiently high temperature, specifically, a high temperature of 1700 ° C. or higher while suppressing the deterioration of the surface state of the SiC wafer. As a result, in a state where the sublimation suppressing member including at least one selected from the group consisting of silicon carbide, tantalum carbide, tungsten carbide and carbon is disposed along the one main surface of the SiC wafer. It has been found that by heat treating the wafer, heat treatment at a high temperature of 1700 ° C. or higher is possible while suppressing deterioration of the surface state of the SiC wafer. This is because even when SiC is sublimated from a SiC wafer by heating to a temperature of 1700 ° C. or higher, the sublimation suppressing member is disposed along the one main surface, so that SiC in the vicinity of the one main surface can be obtained. This is thought to be due to an increase in the partial pressure of, which suppresses sublimation of SiC. Therefore, according to the method for manufacturing a semiconductor device of the present invention, it is possible to provide a method for manufacturing a semiconductor device capable of performing sufficient heat treatment while suppressing deterioration of the surface state of the SiC wafer.

  The sublimation suppressing member may be arranged so as to cover a part of the one main surface of the SiC wafer, but the surface state of the SiC wafer is arranged so as to cover the entire one main surface. Can be further suppressed. In addition, the sublimation suppressing member may be a single member arranged for the purpose of suppressing sublimation of SiC, or may be a part of a container that holds a SiC wafer or a device that performs heat treatment of the SiC wafer. .

  The semiconductor device manufacturing method may further include a step of performing ion implantation on the wafer after the step of preparing the wafer and before the step of heat-treating the wafer.

  Thereby, activation annealing at a high temperature of the SiC wafer subjected to ion implantation, for example, activation annealing at 1700 ° C. or higher can be performed while suppressing deterioration of the surface state of the SiC wafer.

  Preferably, the method for manufacturing a semiconductor device further includes a step of forming a cap layer on the one main surface after the step of preparing the wafer and before the step of heat-treating the wafer. Yes.

  By performing the heat treatment of the SiC wafer with the cap layer formed on the one main surface, it is possible to further suppress the deterioration of the surface state of the SiC wafer due to the heat treatment. Here, as the cap layer, for example, a cap layer made of carbon formed by carbonizing a resist on the surface of the SiC wafer may be adopted, or a cap layer made of tantalum carbide or tungsten carbide may be adopted. .

  Preferably, in the semiconductor device manufacturing method, in the step of heat-treating the wafer, the wafer is heated to 1700 ° C. or higher and 2000 ° C. or lower.

  As described above, heating at 1700 ° C. or higher is necessary to achieve a sufficient activation rate in the activation annealing of the SiC wafer subjected to ion implantation. On the other hand, even when heated to a temperature exceeding 2000 ° C., the improvement in the activation rate is small and the problem of significant member deterioration also occurs. In the step of heat-treating the wafer, necessary and sufficient heat treatment including activation annealing can be performed by heating the wafer to a temperature range of 1700 ° C. to 2000 ° C.

  In the semiconductor device manufacturing method, preferably, the sublimation suppressing member has a thickness of 0.5 mm to 10 mm.

  When the thickness of the sublimation suppressing member is less than 0.5 mm, the main surface opposite to the side facing the SiC wafer is cooled by the influence of gas flow in the heat treatment furnace, for example, so as to face the SiC wafer. The temperature drop of the main surface on the side increases. As a result, the temperature difference between the main surface of the SiC wafer and the main surface of the sublimation suppressing member facing each other increases, and there is a risk that SiC sublimation from the SiC wafer tends to occur. On the other hand, if the thickness of the sublimation suppression member exceeds 10 mm, for example, when the SiC wafer is heated by a heating method using high-frequency heating, the sublimation suppression member is also heated to a high temperature by high-frequency heating, and the sublimation suppression member may be damaged. is there. By setting the thickness of the sublimation suppressing member to 0.5 mm or more and 10 mm or less, it is possible to effectively suppress sublimation of SiC from the SiC wafer while suppressing breakage of the sublimation suppressing member.

  In the method for manufacturing a semiconductor device, the sublimation suppressing member may be placed on the wafer in the step of heat-treating the wafer. Thereby, the temperature difference between the sublimation suppressing member and the wafer becomes small, and SiC sublimation can be effectively suppressed.

  In the method for manufacturing a semiconductor device, in the step of heat-treating the wafer, the sublimation suppressing member may be disposed so as to cover the wafer with an interval. Thereby, the partial pressure of SiC in the vicinity of the one main surface of the SiC wafer can be reliably increased, and sublimation of SiC can be effectively suppressed.

  In the semiconductor device manufacturing method, preferably, the distance between the sublimation suppressing member and the wafer is 0.1 mm or more and less than 5 mm.

  It is difficult to make the distance less than 0.1 mm in consideration of the warpage of the SiC wafer and the accuracy of a jig for arranging the sublimation suppressing member. On the other hand, when the distance is 5 mm or more, the partial pressure of SiC in the vicinity of the one main surface of the SiC wafer does not increase sufficiently, or it takes a long time to increase, and the sublimation of SiC cannot be sufficiently suppressed. . Therefore, the interval is preferably 0.1 mm or more and less than 5 mm.

  The semiconductor device according to the present invention is manufactured by the semiconductor device manufacturing method of the present invention.

  According to the semiconductor device of the present invention, since sufficient heat treatment is performed while suppressing deterioration of the surface state of the SiC wafer, a semiconductor device having excellent characteristics can be provided.

  As is apparent from the above description, according to the semiconductor device manufacturing method and the semiconductor device of the present invention, the semiconductor device can be sufficiently heat-treated while suppressing the deterioration of the surface state of the SiC wafer. By manufacturing the method and the manufacturing method, a semiconductor device having excellent characteristics can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view showing a configuration of a MOSFET (Metal Oxide Field Effect Transistor) as a semiconductor device according to the first embodiment which is an embodiment of the present invention. With reference to FIG. 1, the MOSFET in the first embodiment will be described.

Referring to FIG. 1, MOSFET 1 in the first embodiment is made of silicon carbide (SiC), which is a wide bandgap semiconductor, and has an n ⁺ SiC substrate 11 that is an n-type (first conductivity type) substrate. An n ⁻ SiC layer 12 as a semiconductor layer whose conductivity type is n-type (first conductivity type), and a pair of p-type wells 13 as second conductivity-type regions whose conductivity type is p-type (second conductivity type); , And an n ⁺ source region 14 as a high-concentration first conductivity type region whose conductivity type is n type (first conductivity type). The n ⁺ SiC substrate 11 is made of, for example, hexagonal SiC and includes a high concentration of n-type impurities (impurities whose conductivity type is n-type). The n ⁻ SiC layer 12 is formed on one main surface 11A of the n ⁺ SiC substrate 11 and has an n-type conductivity by including an n-type impurity. The n-type impurity contained in the n ⁻ SiC layer 12 is, for example, N (nitrogen), and is contained at a lower concentration than the n-type impurity contained in the n ⁺ SiC substrate 11.

The pair of p-type wells 13 includes a second main surface 12B that is a main surface opposite to the first main surface 12A that is the main surface on the n ⁺ SiC substrate 11 side in the n ⁻ SiC layer 12. And p-type impurities (impurities whose conductivity type is p-type), so that the conductivity type is p-type (second conductivity type). The p-type impurity contained in the p-type well 13 is, for example, aluminum (Al), boron (B) or the like, and is contained at a lower concentration than the n-type impurity contained in the n ⁺ SiC substrate 11.

N ⁺ source region 14 includes second main surface 12 ^</ b ^> B and is formed inside each of the pair of p-type wells 13 so as to be surrounded by p-type well 13. The n ⁺ source region 14 contains an n-type impurity such as P at a higher concentration than the n-type impurity contained in the n ⁻ SiC layer 12.

  Further, referring to FIG. 1, MOSFET 1 includes a gate oxide film 15 as a gate insulating film, a gate electrode 17, a pair of source contact electrodes 16, an interlayer insulating film 18, a source electrode 19, and a drain electrode 20. And.

A gate oxide film 15 is in contact with second main surface 12B, ⁿ so as to extend from the upper surface of one ^{n +} source region 14 to the top surface of the other ^{n +} source regions 14 - SiC layer 12 It is formed on second main surface 12B and is made of, for example, silicon dioxide (SiO ₂ ).

Gate electrode 17 is arranged in contact with gate oxide film 15 so as to extend from one n ⁺ source region 14 to the other n ⁺ source region 14. The gate electrode 17 is made of a conductor such as polysilicon or Al.

Source contact electrode 16 extends from each of the pair of n ⁺ source regions 14 in a direction away from gate oxide film 15 and is in contact with second main surface 12B. The source contact electrode 16 is made of a material capable of ohmic contact with the n ⁺ source region 14 such as NiSi (nickel silicide).

Interlayer insulating film 18 is formed so as to surround gate electrode 17 on second main surface 12B and to extend from one p-type well 13 to the other p-type well 13. It is made from a silicon dioxide (SiO _2).

Source electrode 19 surrounds interlayer insulating film 18 on second main surface 12B and extends to the upper surfaces of n ⁺ source region 14 and source contact electrode 16. The source electrode 19 is made of a conductor such as Al and is electrically connected to the n ⁺ source region 14 via the source contact electrode 16.

The drain electrode ^20, in n + SiC substrate 11 ⁿ - are formed in contact with the main surface on the side opposite to the side where the SiC layer 12 is formed. The drain electrode 20 is made of a material that can be in ohmic contact with the n ⁺ SiC substrate 11, such as NiSi, and is electrically connected to the n ⁺ SiC substrate 11.

Next, the operation of MOSFET 1 will be described. Referring to FIG. 1, when the voltage of gate electrode 17 is lower than the threshold voltage, that is, in the off state, a reverse bias is applied between p-type well 13 and n ⁻ SiC layer 12 located immediately below gate oxide film 15. It becomes a non-conductive state. On the other hand, when a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode 17, an inversion layer is formed in the channel region 13A in the vicinity of the p-type well 13 in contact with the gate oxide film 15. As a result, n ⁺ source region 14 and n ⁻ SiC layer 12 are electrically connected, and a current flows between source electrode 19 and drain electrode 20.

Here, MOSFET 1 in the first embodiment is manufactured by the method for manufacturing a semiconductor device in the first embodiment, which is one embodiment of the present invention described later. Therefore, sufficient heat treatment is performed while suppressing the deterioration of the surface state of the second main surface 12B of the n ⁻ SiC layer 12. Therefore, MOSFET 1 in the first embodiment is a semiconductor device having excellent characteristics.

More specifically, in MOSFET 1, p-type well 13 and n ⁺ formed by ion implantation are suppressed while deterioration of the surface state at channel region surface 13B, which is an interface between channel region 13A and gate oxide film 15, is suppressed. The activation of impurities in the source region 14 is achieved at a high rate (for example, the activation rate is 90% or more). As a result, the MOSFET 1 is a MOSFET having high carrier mobility in the channel region 13A and capable of reducing on-resistance.

  Next, a method for manufacturing a MOSFET as a semiconductor device in the first embodiment will be described. FIG. 2 is a flowchart showing an outline of the MOSFET manufacturing method according to the first embodiment. 3 to 9 and 11 are schematic cross-sectional views for explaining the method of manufacturing the MOSFET in the first embodiment. FIG. 10 is a schematic diagram for explaining the heat treatment performed in the activation annealing step of the first embodiment.

Referring to FIG. 2, in the MOSFET manufacturing method in the first embodiment, a substrate preparation step is first performed as a step (S10). In this step (S10), a first conductivity type substrate is prepared. Specifically, referring to FIG. 3, an n ⁺ SiC substrate 11 made of, for example, hexagonal SiC and having an n-type conductivity by including an n-type impurity is prepared.

Next, referring to FIG. 2, an n-type layer forming step is performed as a step (S20). In this step (S ^< b> 20), a first conductivity type semiconductor layer is formed on one main surface 11 ^</ b> A of n ⁺ SiC substrate 11. Specifically, referring to FIG. 3, n ⁻ SiC layer 12 is formed on n ⁺ SiC substrate 11 by epitaxial growth. Epitaxial growth can be performed, for example, by using a mixed gas of SiH ₄ (silane) and C ₃ H ₈ (propane) as a source gas. At this time, for example, nitrogen is introduced as an n-type impurity. Thereby, the n ⁻ SiC layer 12 containing an n-type impurity having a lower concentration than the n-type impurity contained in the n ⁺ SiC substrate 11 can be formed. The steps (S10) and (S20) constitute a wafer preparation step for preparing a wafer 3 having at least one main surface made of silicon carbide (see FIGS. 2 and 3).

Next, referring to FIG. 2, a p-type well forming step is performed as a step (S30). In this step (S30), referring to FIG. 4, the n ⁻ SiC layer 12 of the wafer 3 is the main surface opposite to the first main surface 12A that is the main surface on the n ⁺ SiC substrate 11 side. A second conductivity type second conductivity type region is formed so as to include second main surface 12B. Specifically, first, an oxide film 91 made of SiO ₂ is formed on second main surface 12B by, for example, CVD. Then, after a resist is applied onto the oxide film 91, exposure and development are performed, and a resist film 92 having an opening in a region corresponding to the shape of the p-type well 13 as a desired second conductivity type region is formed. Is done.

Then, referring to FIG. 5, oxide film 91 is partially removed by, for example, RIE (Reactive Ion Etching) using resist film 92 as a mask, thereby causing n ⁻ SiC layer 12 to be removed. A mask layer made of oxide film 91 having an opening pattern is formed thereon. Thereafter, after removing the resist film 92 and performing ion implantation into the n ⁻ SiC layer 12 using this mask layer as a mask as shown in FIG. 6, a p-type well 13 is formed in the n ⁻ SiC layer 12. Is formed.

Next, with reference to FIG. 2, an n ⁺ region forming step is performed as a step (S40). In this step (S <b> 40), a high-concentration first conductivity type region containing a first conductivity type impurity having a concentration higher than that of the n ⁻ SiC layer 12 is formed in a region including the second main surface 12 </ b> B in the p-type well 13. It is formed. Specifically, referring to FIG. 6, first, oxide film 91 used as a mask in step (S30) is removed. Referring to FIG. 7, an oxide film 91 made of SiO ₂ is formed on second main surface 12B by, for example, CVD. Further, after a resist is applied on oxide film 91, exposure and development are performed, and a resist film having an opening in a region corresponding to the shape of n ⁺ source region 14 as a desired high-concentration first conductivity type region 92 is formed.

Referring to FIG. 7, oxide film 91 is partially removed by, for example, RIE using resist film 92 as a mask, so that oxide film 91 having an opening pattern on n ⁻ SiC layer 12 is removed. A mask layer is formed. Then, after removing the resist film 92, as shown in FIG. 8, an n-type impurity such as phosphorus (P) is introduced into the n ⁻ SiC layer 12 by ion implantation using the mask layer as a mask. . As a result, an n ⁺ source region 14 as a high concentration first conductivity type region is formed. The above steps (S30) and (S40) constitute an ion implantation step for performing ion implantation on the wafer 3.

  Next, referring to FIG. 2, an annealing cap forming step in which a cap layer is formed is performed as a step (S50). In this step (S50), a cap layer that covers the second main surface 12B is formed on the second main surface 12B that is one main surface of the wafer 3 on which the ion implantation step has been completed. Specifically, referring to FIG. 8, first, oxide film 91 used as a mask in step (S40) is removed. Then, referring to FIG. 9, cap layer 93 covering second main surface 12B is formed on second main surface 12B. The cap layer 93 can be formed by, for example, applying a resist on the second main surface 12B and heating and carbonizing the resist in an argon (Ar) atmosphere. Further, as the cap layer 93, a film made of TaC or WC may be formed by a sputtering method or a CVD method.

  Next, referring to FIG. 2, an activation annealing step in which activation annealing is performed is performed as a step (S60). In this step (S60), activation annealing which is a heat treatment for activating impurities introduced into the wafer 3 by ion implantation in steps (S30) and (S40) is performed by heating the wafer 3. Specifically, the wafer 3 manufactured by performing steps (S10) to (S50) is charged into, for example, a heat treatment furnace and heated to a temperature range of 1700 ° C. or higher and 2000 ° C. or lower.

  Here, a heat treatment furnace for performing the activation annealing will be described. Referring to FIG. 10, heat treatment furnace 5 used in the step (S <b> 60) includes a heating chamber 51 and a high frequency coil 52. The heating chamber 51 is formed with a gas inlet 51 </ b> A that is an opening for introducing atmospheric gas into the heating chamber 51 and a gas outlet 51 </ b> B that is an opening for discharging atmospheric gas in the heating chamber 51. Has been. In the heating chamber 51, a heat insulating member 53 made of a heat insulating material is disposed along the inner wall, and a heating element 54 is disposed on the heat insulating member 53. That is, the heat insulating member 53 is disposed between the inner wall of the heating chamber 51 and the heating element 54. Furthermore, the high frequency coil 52 is disposed so as to surround the outer wall of the heating chamber 51 and the heating element 54.

Next, the procedure for performing the step (S60) using the heat treatment furnace 5 will be described. First, the wafer 3 in which the cap layer 93 is formed on the second main surface 12 </ b> B that is one main surface of the n ⁻ SiC layer 12 in the step (S <b> 50) is placed on the heating element 54 in the heating chamber 51. Is done. Then, SiC substrate 61 as a sublimation suppressing member made of SiC is placed on wafer 3. That is, SiC substrate 61 is placed on cap layer 93. On the other hand, argon (Ar) as an atmospheric gas is introduced into the heating chamber 51 from the gas inlet 51A, and the atmospheric gas is discharged from the gas outlet 51B. Thereby, the atmosphere in the heating chamber 51 is adjusted to an inert atmosphere. Instead of the SiC substrate 61, a TaC substrate made of TaC, a WC substrate made of WC, a C substrate made of carbon, or the like may be employed as a sublimation suppressing member.

  Next, by applying a high frequency voltage to the high frequency coil 52, the heating element 54 is induction heated. Then, the wafer 3 is heated by the heated heating element. The heating temperature of the wafer 3 can be 1700 ° C. or more and 2000 ° C. or less. At this time, since the SiC substrate 61 is placed on the second main surface 12B of the wafer 3, even when SiC is sublimated from the wafer 3 by being heated to a temperature of 1700 ° C. or higher, the second The partial pressure of SiC in the vicinity of main surface 12B increases, the temperature difference between wafer 3 and SiC substrate 61 is suppressed, and the sublimation of SiC from wafer 3 is suppressed. As a result, activation annealing is performed at a sufficient temperature while suppressing deterioration of the surface state of the wafer 3. Through the above steps, the step of heat-treating the wafer 3 is completed.

  Here, when the thickness of the SiC substrate 61 is less than 0.5 mm, the main surface opposite to the side facing the wafer 3 is cooled by the influence of the gas flow in the heat treatment furnace 5, thereby The temperature drop of the main surface on the opposite side is increased. As a result, the temperature difference between the second main surface 12B of the wafer 3 and the main surface of the SiC substrate 61 facing each other increases, and there is a risk that SiC sublimation from the wafer 3 is likely to occur. On the other hand, if the thickness of SiC substrate 61 exceeds 10 mm, SiC substrate 61 may be heated to a high temperature by high frequency heating and damaged. Therefore, the thickness of SiC substrate 61 is preferably not less than 0.5 mm and not more than 10 mm.

  Next, referring to FIG. 2, an annealing cap removing step is performed as a step (S70). In this step (S70), referring to FIG. 9, cap layer 93 formed in step (S50) is removed from wafer 3 as shown in FIG.

  Next, referring to FIG. 2, as steps (S80) to (S130), a gate insulating film forming step, a contact electrode forming step, a drain electrode forming step, a gate electrode forming step, an interlayer insulating film forming step, and a source electrode forming are performed. The steps are performed sequentially.

In the gate insulating film forming step performed as the step (S80), the second main surface 12B exposed by removing the cap layer 93 in the step (S70) is thermally oxidized. Thereby, a gate oxide film 15 (see FIG. 1) is formed as a gate insulating film made of silicon dioxide (SiO ₂ ).

In the contact electrode formation step performed as the step (S90), for example, a nickel (Ni) film formed by vapor deposition is heated and silicided. Thereby, as shown in FIG. 1, a pair of source contact electrodes 16 made of NiSi (nickel silicide) and in ohmic contact with the n ⁺ source region 14 are formed.

In the drain electrode formation step performed as the step (S100), for example, a nickel (Ni) film formed by vapor deposition is heated and silicided. Thus, as shown in FIG. ^1, n + SiC substrate 11 and the drain electrode 20 made of ohmic contact can NiSi ^is, in n + SiC substrate 11 ⁿ - mainly opposite to the side on which the SiC layer 12 is formed It is formed so as to contact the surface.

  In the gate electrode formation step performed as the step (S110), the gate electrode 17 (see FIG. 1) made of polysilicon as a conductor is formed in contact with the gate oxide film 15 by, for example, the CVD method.

In the interlayer insulating film forming step performed as the step (S120), the interlayer insulating film 18 (see FIG. 1) made of SiO _{2 as} an insulator is formed on the second main surface 12B by the CVD method, for example. Is formed so as to surround.

In the source electrode forming step performed as the step (S130), the source electrode 19 (see FIG. 1) made of Al as a conductor is formed on the second main surface 12B by using, for example, a vapor deposition method. It surrounds and is formed so as to extend onto the upper surfaces of n ⁺ source region 14 and source contact electrode 16. Through the above steps (S10) to (S130), the MOSFET 1 manufacturing method as the semiconductor device in the first embodiment is completed, and the MOSFET 1 (see FIG. 1) of the first embodiment is completed.

In the method for manufacturing a semiconductor device according to the present embodiment, activation annealing is performed on wafer 3 at a temperature of 1700 ° C. or higher with SiC substrate 61 placed on wafer 3 in step (S60). The Therefore, referring to FIG. 1, the activation of impurities in p-type well 13 and n ⁺ source region 14 formed by ion implantation is achieved at a high rate while suppressing the deterioration of the surface state on channel region surface 13B. ing. As a result, MOSFET 1 having high carrier mobility and reduced on-resistance in channel region 13A can be manufactured.

(Embodiment 2)
Next, a method for manufacturing a semiconductor device according to the second embodiment, which is another embodiment of the present invention, will be described. FIG. 12 is a schematic diagram for explaining the heat treatment performed in the activation annealing step of the second embodiment. The method of manufacturing a MOSFET as a semiconductor device in the second embodiment is basically performed in the same manner as in the first embodiment. However, referring to FIG. 2, the second embodiment is different from the first embodiment in the activation annealing step performed as step (S60).

  That is, in step (S60) of the second embodiment, referring to FIG. 12, first, wafer 3 on which cap layer 93 is formed in step (S50) is placed on heating element 54 in heating chamber 51. Placed. Further, a cover member 65 is placed on the heating element 54 so as to cover the wafer 3. The cover member 65 has a flat plate shape, and is composed of an SiC plate 62 as a sublimation suppressing member made of SiC, and a leg portion 63 that is connected to the SiC plate 62 and extends in a direction intersecting the main surface of the SiC plate 62. Including. The length of the leg portion 63 is larger than the thickness of the wafer 3. The cover member 65 is disposed so as to cover the wafer 3 at intervals by being supported by the leg portions 63 with respect to the heating element 54. At this time, the SiC plate 62 is disposed along the second main surface 12B so that the main surface thereof faces the second main surface 12B of the wafer 3. Further, the material of the leg portion 63 is not particularly limited, but may be made of SiC similarly to the SiC plate 62 or may be formed integrally with the SiC plate 62. More specifically, the cover member 65 may be a sintered body made of integral SiC.

  Here, the distance between the SiC plate 62 and the wafer 3 (the distance between the surface of the SiC plate 62 facing the wafer 3 and the cap layer 93 formed on the second main surface 12B of the wafer 3) is less than 0.1 mm. This is difficult considering the warpage of the wafer 3 and the accuracy of a jig for arranging the cover member 65. On the other hand, when the distance is 5 mm or more, the partial pressure of SiC in the vicinity of the second main surface 12B of the wafer 3 does not increase sufficiently, or it takes a long time to increase, and the sublimation of SiC is sufficiently suppressed. Can not. Therefore, the interval is preferably 0.1 mm or more and less than 5 mm.

  That is, referring to FIG. 12, in the step (S60) of the second embodiment, SiC plate 62 as a sublimation suppressing member is arranged so as to cover wafer 3 at an interval. Thereby, the partial pressure of SiC in the vicinity of the second main surface 12B of the wafer 3 can be reliably increased, and the sublimation of SiC can be effectively suppressed.

  In the first and second embodiments, the case where the step (S50) of forming the cap layer 93 on the second main surface 12B of the wafer 3 has been described. However, the semiconductor device of the present invention is not limited to this. The manufacturing method is not limited to this, and the step of forming the cap layer (S50) and the step of removing the cap layer (S70) may be omitted. In the above embodiment, the semiconductor device manufacturing method and the semiconductor device of the present invention have been described by taking MOSFET as an example, but the semiconductor device that can be manufactured by the semiconductor device manufacturing method of the present invention is not limited to this. Semiconductor devices that can be manufactured by the method of manufacturing a semiconductor device according to the present invention include, in addition to MOSFETs, for example, JFET (Junction Field Effect Transistor), Schottky barrier diode, pn diode, IGBT (Insulated Gate Bipolar Transistor). An insulated gate bipolar transistor).

  Embodiment 1 of the present invention will be described below. In the same method for manufacturing a semiconductor device as in the second embodiment, an experiment was conducted to examine a preferable distance between the sublimation suppressing member and the SiC wafer. The experimental procedure is as follows.

  First, a SiC wafer made of SiC was prepared, and a resist layer covering a part of the main surface of the SiC wafer was formed. Thereafter, the main surface of the SiC wafer was etched by RIE using the resist layer as a mask. And the sample wafer which has a mesa (convex part) in the main surface was obtained by removing the said mask. This sample wafer was subjected to the same heat treatment as in step (S60) in the second embodiment. The temperature of the heat treatment was 1800 ° C. and the time was 30 minutes. The above process is performed for the case where the distance between the SiC plate 62 (sublimation suppression member) and the wafer 3 (SiC wafer) is 1 mm and 5 mm, and the surface state of the sample wafer after the heat treatment is finished is SEM (Scanning Electron Microscope). A scanning electron microscope).

  Next, experimental results will be described. FIG. 13 is an SEM photograph of the sample wafer when the distance between the sublimation suppressing member and the SiC wafer is 1 mm. FIG. 14 is an SEM photograph of the sample wafer when the distance between the sublimation suppressing member and the SiC wafer is 5 mm.

  Referring to FIG. 13, when the distance between the sublimation suppressing member and the SiC wafer is 1 mm, the edge of mesa 71 formed before the heat treatment is clearly maintained, and the surface of the SiC wafer resulting from the heat treatment at a high temperature. It is confirmed that the deterioration of the state is effectively suppressed. On the other hand, referring to FIG. 14, even when the distance between the sublimation suppressing member and the SiC wafer is 5 mm, the shape of the mesa 71 formed before the heat treatment is substantially maintained, and the conventional sublimation suppressing member is not used. It can be said that the deterioration of the surface state of the SiC wafer is suppressed as compared with the heat treatment. However, as compared with the case of FIG. 13, the edge of the mesa 71 starts to be deformed, and it is considered that the effect of suppressing the deterioration of the surface condition is lowered when the distance between the sublimation suppressing member and the SiC wafer is 5 mm or more. From the above experimental results, in order to effectively suppress the deterioration of the surface state of the SiC wafer due to the heat treatment at a high temperature, it is confirmed that the interval between the sublimation suppressing member and the SiC wafer is preferably 5 mm or less. It was.

  The embodiments and examples disclosed herein are illustrative in all respects and should not be construed as being restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  A method for manufacturing a semiconductor device and a semiconductor device according to the present invention include a method for manufacturing a semiconductor device including a step of performing heat treatment by heating a wafer having at least one main surface made of silicon carbide, and a semiconductor device manufactured by the method. It can be applied particularly advantageously.

3 is a schematic cross-sectional view showing the configuration of a MOSFET in the first embodiment. FIG. 3 is a flowchart showing an outline of a method for manufacturing a MOSFET in the first embodiment. 5 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. FIG. 3 is a schematic diagram for explaining a heat treatment performed in the activation annealing step of the first embodiment. 5 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. FIG. 6 is a schematic diagram for explaining a heat treatment performed in an activation annealing step of a second embodiment. It is a SEM photograph of a sample wafer in case a gap between a sublimation suppression member and a SiC wafer is 1 mm. It is a SEM photograph of a sample wafer in case a gap between a sublimation suppression member and a SiC wafer is 5 mm.

Explanation of symbols

1 MOSFET, 3 wafer, 5 heat treatment furnace, 11 n ⁺ SiC substrate, 11A one main surface, 12 n ⁻ SiC layer, 12A first main surface, 12B second main surface, 13 p-type well, 13A channel region , 13B channel region surface, 14 n ⁺ source region, 15 gate oxide film, 16 source contact electrode, 17 gate electrode, 18 interlayer insulating film, 19 source electrode, 20 drain electrode, 51 heating chamber, 51A gas inlet, 51B gas Discharge port, 52 high frequency coil, 53 heat insulating member, 54 heating element, 61 SiC substrate, 62 SiC plate, 63 leg, 65 cover member, 71 mesa, 91 oxide film, 92 resist film, 93 cap layer.

Claims (9)

Preparing a wafer having at least one main surface made of silicon carbide;
A step of heat-treating the wafer by heating the wafer,
In the step of heat-treating the wafer, a sublimation suppressing member including at least one selected from the group consisting of silicon carbide, tantalum carbide, tungsten carbide, and carbon is disposed along the one main surface. A method of manufacturing a semiconductor device, wherein the wafer is heated in a state.   The method of manufacturing a semiconductor device according to claim 1, further comprising a step of performing ion implantation on the wafer after the step of preparing the wafer and before the step of heat-treating the wafer. .   3. The method according to claim 1, further comprising a step of forming a cap layer on the one main surface after the step of preparing the wafer and before the step of heat-treating the wafer. Semiconductor device manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein in the step of heat-treating the wafer, the wafer is heated to 1700 ° C. or more and 2000 ° C. or less.   The method for manufacturing a semiconductor device according to claim 1, wherein the sublimation suppressing member has a thickness of 0.5 mm to 10 mm.   The method for manufacturing a semiconductor device according to claim 1, wherein, in the step of heat-treating the wafer, the sublimation suppressing member is placed on the wafer.   6. The method of manufacturing a semiconductor device according to claim 1, wherein, in the step of heat-treating the wafer, the sublimation suppressing member is disposed so as to cover the wafer at an interval.   The method for manufacturing a semiconductor device according to claim 7, wherein the distance is 0.1 mm or more and less than 5 mm.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.