JP2008034464A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain the desired impurity concentration and distribution thereof with simplified processes, and further to improve electrical characteristics of the device. <P>SOLUTION: A MESFET having the desired impurity concentration and distribution thereof can be obtained unlike the related art without use of an epitaxial layer through activation of an ion-implanted impurity by executing a thermal process, to a silicon carbide substrate 1, with inductive heating within the atmosphere including at least carbon and silicon after ion implantation to an n-type channel layer 2, and through deposition of a silicon carbide layer 4 formed of silicon carbide with impurity concentration lower than that of the n-type channel layer 2 on the surface of the n-type channel layer 2 to which the ion is implanted. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device such as a silicon carbide MESFET, and more particularly to a method for improving the device characteristics while simplifying the manufacturing process.

  Silicon carbide (silicon carbide, SiC) has a forbidden body width that is about 3 times that of silicon, about 10 times the dielectric breakdown electric field, and about 3 times larger in thermal conductivity. Expected as a material. Furthermore, since silicon carbide can form a silicon oxide film by thermal oxidation and can control n-type and p-type conductivity by impurity doping, various structures realized in conventional silicon devices can be obtained. It has a feature that is significantly different from other compound semiconductor materials, such that a device having the above can be manufactured.

  As semiconductor devices using such silicon carbide, high breakdown voltage high-speed switching pn diodes, Schottky diodes, high breakdown voltage low on-resistance metal-oxide-semiconductor junction field effect transistors (MOSFETs), gates, etc. Insulated bipolar transistors (IGBTs), junction field effect transistors (JFETs), high power high frequency MESFETs, electrostatic induction transistors (SITs), and the like have been developed. Among these, high-power high-frequency MESFETs are attracting attention as high-power transmitters for mobile base stations and individual amplifiers for radar due to the rapid spread of mobile communications.

  For production of MESFET using silicon carbide, an epitaxial wafer in which a conductive layer is formed by homoepitaxial growth on silicon carbide is used. For example, a typical manufacturing method of MESFET using such silicon carbide is disclosed in Patent Document 1 and the like.

  That is, in Patent Document 1, a silicon carbide substrate on which an n-type channel layer and an n + high-concentration layer doped with an impurity at a higher concentration are epitaxially grown is used to electrically isolate mesa from adjacent transistors. Etching, forming a source electrode and a drain electrode, removing the n + high concentration layer between the source electrode and the drain electrode by recess etching, and forming a Schottky junction on the n-type channel layer A manufacturing method comprising a process of making a MESFET is disclosed.

  Further, in the same document, as another method, an ohmic electrode is formed by forming an n-type channel layer by epitaxial growth on a silicon carbide substrate, and forming an n-type high-concentration layer by ion implantation in both the source electrode and drain electrode regions. A step of forming, a step of forming a Schottky electrode on the surface of the n-type channel layer between the source electrode and the drain electrode, and a step of forming a MESFET by performing mesa etching to electrically isolate the adjacent FET. A manufacturing method is disclosed.

  In addition, as a method of manufacturing a MESFET without using an epitaxial substrate, phosphorus is ion-implanted into a channel layer formed on a semi-insulating substrate, while nitrogen is ion-implanted into a source / drain to manufacture a MESFET. Is disclosed in Non-Patent Document 1 and the like.

  Further, in the production of MESFETs using ion implantation, it is known that the surface of silicon carbide is roughened by heat treatment for impurity activation after ion implantation (see, for example, Non-Patent Document 2). In the production of a double diffusion type MOS (DMOS) FET, the on-resistance increases due to the rough surface of the silicon carbide (see, for example, Non-Patent Document 3). For this reason, in the development of silicon carbide elements using an ion implantation process, annealing techniques that prevent surface roughness are being actively studied.

JP-A-5-175239 (page 4-8, FIGS. 1-7) J.B. Tucker et al., “Nitrogen and phosphorous implanted MESFETs in semi-insulating 4H-SiC”, Diamond and Related Materials 11, 2002, p392-395. S. Blanque et al., “Room Temperature Implantaion and Activation Kinetics of Nitrogen and Phosphorous in 4H-SiC Crystal”, Material Science Forum Vols. 457-460, 2004, p893-896 M.A. Capano et al., "Surface Roughening in Ion Implanted 4H-Silicon Carbied", Journal of Electronics Materials, Vol.28, No.3, 1999, p214-218

  By the way, in the MESFET using the epitaxial film as described above, the temperature during epitaxial growth is as high as about 1500 ° C., so it becomes difficult to control the temperature in the furnace and to make the gas flow uniform. It is difficult to control the impurity concentration and thickness of the layer. In particular, since the MESFET channel layer uses a relatively thin epitaxial layer of about several hundred nanometers in silicon carbide devices, in the case of silicon carbide formed at a high temperature, it is possible to control the impurity concentration and thickness. It has become difficult. As a result, the impurity concentration of the epitaxial layer and the thickness thereof vary, and there is a problem that the threshold control of the MESFET cannot be performed.

  Further, in epitaxial growth, it is difficult to control the flow rate of the gas while changing the impurity concentration while growing a thin epitaxial layer used for the channel layer of MESFET, so that only a channel layer having a constant impurity concentration can be formed. Therefore, in order to change the electrical characteristics of the MESFET, there has been no other way but to optimize the impurity concentration and thickness of the epitaxial layer. Furthermore, in the manufacturing process of the DMOSFET, there has been a problem that the on-resistance increases due to surface roughness.

  The present invention has been made in view of the above-mentioned circumstances, and without using an epitaxial device, as a design parameter of the channel layer, in addition to the thickness of the impurity, a concentration gradient in the depth direction of the impurity concentration is formed. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can introduce three design parameters and can further improve electrical characteristics.

Another object of the present invention is to provide a method of manufacturing a semiconductor device that can sufficiently activate impurities and prevent the surface of the silicon carbide from being roughened by heat treatment after ion implantation.
Another object of the present invention is to provide a method for manufacturing a semiconductor device using a highly safe heat treatment without using a reactive gas.

In order to achieve the above object of the present invention, a method for manufacturing a semiconductor device according to the present invention includes:
A method for manufacturing a semiconductor device, wherein a semiconductor element having a semiconductor layer as an active region is formed on a substrate having a semiconductor layer made of silicon carbide,
Ion implantation of impurities into the semiconductor layer;
After the ion implantation, by performing a heat treatment on the substrate in an atmosphere gas containing at least carbon and silicon, the ion-implanted impurities are activated, and the surface of the semiconductor layer subjected to the ion implantation is activated. Depositing a semiconductor layer of silicon carbide;
Forming an ohmic junction or Schottky junction electrode on the semiconductor layer.
In such a configuration, in the step of performing the heat treatment after the ion implantation,
A substrate in which impurities are ion-implanted into a semiconductor layer is placed in a heating container coated with silicon carbide, and the semiconductor layer into which the substrate is ion-implanted is coated with silicon carbide in the heating container. The semiconductor which is stored so as to face the surface and heated so that the portion of the heating container facing the surface of the semiconductor layer reaches a higher temperature than the surface of the semiconductor layer on which the ion implantation has been performed. The space between the layer and the heating container was filled with an atmospheric gas containing a silicon carbide sublimation gas on the surface of the heating container, the impurities implanted by the ion implantation were activated, and the ions were implanted It is preferable to deposit a semiconductor layer made of silicon carbide on the surface of the semiconductor layer.
Further, in the step of performing the heat treatment after the ion implantation, the portion of the heating container that faces the surface of the semiconductor layer becomes higher in the heating container than the surface of the semiconductor layer into which the ions are implanted. It is more preferable to perform the heat treatment while maintaining a proper temperature gradient.

According to the present invention, roughening of the substrate surface can be prevented in the heat treatment for activating the ion-implanted impurities. In addition, since the channel layer of the MESFET can be formed by ion implantation, the impurity concentration, the distribution in the depth direction, and the like can be made in accordance with desired electrical characteristics, and the degree of freedom in device design is increased. In addition to being able to perform the heat treatment for activating the impurities, unlike the conventional case, the substrate surface can be prevented from being rough, and therefore, the gate leakage current is small and good MESFET characteristics can be realized. It has the effect of being able to do it.
In addition, when the present invention is applied to a DMOSFET manufacturing process, impurities can be activated while the surface is flat, and an increase in ion resistance as in the prior art can be suppressed.
In addition, since the method for manufacturing a semiconductor device according to the present invention does not use a reactive gas, high safety in heat treatment can be ensured.

Embodiments of the present invention will be described below.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.

Hereinafter, the manufacturing process of the silicon carbide MESFET will be described with reference to FIG.
First, selective implantation using an ion implantation mask is performed on the high resistance silicon carbide substrate 1 (see FIG. 1A) to form an n-type channel layer 2 (see FIG. 1B). Here, it is generally well known that the impurity concentration distribution in the solid when ion implantation is performed follows a Gaussian distribution.

Next, nitrogen is ion-implanted into the source and drain regions 3a and 3b in order to reduce the contact resistivity (see FIG. 1C).
Next, by activating the ion-implanted nitrogen as an impurity and performing a heat treatment that replaces the lattice position, the surface of the high resistance silicon carbide substrate 1, that is, the surface on the side where the n-type channel layer 2 is formed, A silicon carbide layer 4 having an impurity concentration lower than that of the n-type channel layer 2 is formed (see FIG. 1D).

Here, this heat treatment is performed by an annealing apparatus as described below.
That is, as shown in FIG. 2A, the annealing apparatus S includes, for example, a quartz reaction tube 11 formed in a hollow cylindrical shape, and an RF coil 13 provided around the quartz reaction tube 11. The carbon crucible 9 disposed in the quartz reaction tube 11 and carbon that is provided between the carbon crucible 9 and the quartz reaction tube 11 and prevents the heat from radiating to the outside of the quartz reaction tube 11 is used. The heat insulating material 10 is configured as a main component. The annealing apparatus S is of a well-known induction heating type, except for the carbon crucible 9 described later.

In this annealing apparatus S, the quartz reaction tube 11 is water-cooled although not shown.
The carbon crucible 9 as a heating container includes a main body portion 9a in which the silicon carbide substrate 1 is accommodated and a lid body portion 9b for covering the opening portion of the main body portion 9a. In particular, the carbon crucible 9 is coated with high-purity silicon carbide. It has been made.
When the silicon carbide substrate 1 is stored in the carbon crucible 9, it is stored and arranged so that a gap 12 of about 0.05 to 0.1 mm is generated between the silicon carbide substrate 1 and the lid portion 9b. Is preferred.

  Further, the positional relationship between the RF coil 13 and the carbon crucible 9 is such that the temperature TU on the lid body portion 9b side of the carbon crucible 9 and the temperature TB on the bottom side of the main body portion 9a have a relationship of TB <TU. It is preferable to arrange so as to generate a temperature gradient (see FIG. 2B). The RF coil 13 is connected to a high frequency power source (not shown) and applied with a high frequency voltage.

Thus, the silicon carbide substrate 1 (see FIG. 1 (c)) in which the previous ion implantation has been performed on the carbon crucible 9 of the annealing apparatus having the above-described configuration is performed between the silicon carbide substrate 1 and the lid portion 9b. By storing and arranging the gap 12 as described above between them and applying a predetermined voltage to the RF coil 13, heat treatment by induction heating is performed. In such heat treatment, the atmosphere around the silicon carbide substrate 1 is filled with a gas containing carbon and silicon. That is, the carbon crucible 9 is heated by induction heating, and silicon carbide covering the carbon crucible 9 is sublimated, so that the sublimation gas is filled. At this time, a temperature gradient is maintained in the carbon crucible 9.
The silicon carbide substrate 1 is heated by radiant heat from the carbon crucible 9, and as a result, a silicon carbide layer having an impurity concentration (nitrogen concentration) of about 1E16 cm ⁻³ and a thickness of about 20 nm is formed on the surface of the silicon carbide substrate 1. 4 is formed (see FIG. 1D).

Next, a nitride film is deposited on the silicon carbide layer 4 and etching is performed so that the nitride film 5 remains only in the active region of the MESFET (see FIG. 1E).
Next, a region not covered with the nitride film 5 is oxidized using a diffusion furnace (not shown) until the silicon carbide layer 4 becomes an oxide film, and then immersed in a buffered hydrofluoric acid solution to form a silicon carbide layer. The oxide film 4 and the nitride film 5 are removed. As a result, the silicon carbide layer 4 remains only in the active region of the MESFET (see FIG. 1 (f)).

Next, in order to form the source electrode 6a and the drain electrode 6b, nickel ohmic electrodes that are in ohmic contact with the source region 3a and the drain region 3b are formed (FIG. 1G).
Finally, the MESFET is completed by forming the Schottky gate electrode 7 on the silicon carbide layer 4 (see FIG. 1H).

By the way, it is generally well known that when silicon carbide is heated at a high temperature, silicon atoms are evaporated from the substrate surface, rearrangement of atoms occurs, and the surface becomes rough. For example, it has already been reported that surface roughness occurs when a silicon carbide substrate subjected to ion implantation is heated at 1600 degrees (see, for example, Materials Science Forum, Vols. 457-460, 2004, p893-896).
However, when the silicon carbide substrate 1 subjected to ion implantation is heated using an induction heating device and the carbon crucible 9 covered with high-purity silicon carbide, as in the above-described embodiment of the present invention, Unlike the above, heating is possible in the range of 1300 ° C. to 1700 ° C. without roughening the surface. This is considered to be due to the fact that the silicon carbide layer 4 having a low impurity concentration is formed on the surface of the silicon carbide during the high temperature treatment from the result of elemental analysis.

  Moreover, from the result of measuring the distribution of nitrogen impurity concentration in the silicon carbide layer 4 using a secondary ion mass spectrometer (SIMS), the silicon carbide layer 4 has a silicon and carbon content that is completely different from the silicon carbide of the substrate. In the same manner, it has been confirmed that the nitrogen impurity concentration is lower than that of the ion-implanted silicon carbide substrate 1.

FIG. 3 shows the result of secondary ion mass spectrometry when impurities are ion-implanted into silicon carbide. FIG. 3A shows the result of secondary ion mass spectrometry of the impurity distribution immediately after ion implantation. FIG. 3B shows the results of secondary ion mass spectrometry after heat treatment at 1700 ° C. for 30 minutes.
In FIG. 3A, the horizontal axis represents the depth from the substrate surface, and the vertical axis represents the nitrogen impurity concentration. 3B, the horizontal axis indicates the depth from the substrate surface, the vertical axis on the left side of the figure indicates the nitrogen impurity concentration, and the vertical axis on the right side of the figure indicates the number of recombination per second. Represents.
According to these figures, even when heat treatment at 1700 ° C. is performed, no impurity re-diffusion occurs, and it can be confirmed that a silicon carbide layer having the same composition as the bulk substrate is formed on the surface. Yes.

FIG. 4 shows an example of the impurity distribution in the channel layer of the MESFET according to the embodiment of the present invention manufactured as described above, and this figure will be described below.
First, in FIG. 4, the simulation result of the impurity concentration when the ion implantation conditions for forming the channel layer are an acceleration voltage of 75 keV and a nitrogen dose of 9E12 cm ⁻² is shown by a solid characteristic line a. An example of impurity distribution in the depth direction of a conventional epitaxial layer having an impurity concentration of 3E17 cm ⁻² is represented by a two-dot chain characteristic line b.

According to the characteristic line a, as described above, by performing ion implantation in the embodiment of the present invention, the impurity concentration increases from the surface of the silicon carbide substrate toward the inside thereof, and a certain depth (for example, this In the example, it can be confirmed that a channel layer having an impurity distribution in which the impurity concentration becomes a peak of 1E18 cm ⁻³ at a depth of 150 nm and the impurity concentration decreases further toward the inside can be confirmed.

FIG. 5 shows a change characteristic of the drain current with respect to the gate voltage of the MESFET according to the embodiment of the present invention manufactured as described above, which will be described below.
In FIG. 5, the change characteristic of the drain current with respect to the gate voltage of the MESFET in the embodiment of the present invention is shown by a solid characteristic line a, and also with respect to the gate voltage of the silicon carbide MESFET formed using the conventional epitaxial layer. An example of a change characteristic of the drain current is indicated by a two-dot chain line characteristic line b.

According to the figure, in the MESFET manufactured by ion implantation as described in the embodiment of the present invention even though the saturation drain current is similar, the MESFET in which the channel layer is formed by the conventional epitaxial layer. It can be confirmed that the threshold voltage can be reduced and the mutual conductance can be increased as compared with FIG.
As described above, it is generally well known that a MESFET having a large mutual conductance has a small on-resistance and an excellent high-frequency characteristic, and the MESFET according to the embodiment of the present invention has such a feature. It has become.

  Next, a manufacturing process of the DMOSFET will be described. As shown in FIG. 6, an n-active layer 10 made of an n-silicon carbide layer is formed on a low resistance silicon carbide substrate 1a by epitaxial growth. The thickness of the n − active layer 10 is appropriately set depending on the design withstand voltage of the device. For example, if the withstand voltage is 1.2 KV, the thickness is about 10 μm.

  Thereafter, a p-type well layer 11 and an n + silicon carbide layer 12 are formed by ion implantation. Then, heat treatment is performed by the above-described method to activate the ion-implanted ion species. At this time, a silicon carbide layer corresponding to the aforementioned silicon carbide layer 4 is formed on the surface.

  Next, the gate oxide film 13 is formed by thermal oxidation. A source electrode 6a and a drain electrode 6b are formed, and a gate electrode 14 is formed on the gate oxide film 13 to complete a DMOSFET.

  Since the silicon carbide layer formed on the low-resistance silicon carbide substrate 1a is very thin, it becomes an oxide film by thermal oxidation when forming the gate oxide film 13, and does not affect the device characteristics. .

Thus, since the silicon carbide layer 4 in the embodiment of the present invention has an impurity concentration smaller than that of the ion implantation layer and a flat surface, when used in a MESFET, the leakage current of the Schottky gate is small. When it is used for a DMOSFET, the on-resistance is reduced.
In addition, since the silicon carbide MESFET manufactured by the method for manufacturing a semiconductor device according to the embodiment of the present invention does not require an epitaxial layer, not only the epitaxial device used for the growth becomes unnecessary, but also as described above. The annealing apparatus S is a heating apparatus that uses general induction heating, and the carbon crucible 9 is only coated with silicon carbide, so that the apparatus cost is lower than that of the crystal growth apparatus. In addition, since the semiconductor device manufacturing method according to the embodiment of the present invention does not use reactive gas, heat treatment with high safety can be performed.

It is explanatory drawing of the manufacturing process of silicon carbide MESFET based on the manufacturing method of the semiconductor device in embodiment of this invention. FIG. 2A is a schematic diagram for explaining a configuration of an annealing apparatus used in a manufacturing process of a silicon carbide MESFET based on a manufacturing method of a semiconductor device in an embodiment of the present invention, and FIG. 2A is an embodiment of the present invention. FIG. 2B is a schematic diagram schematically showing a temperature gradient in the carbon crucible used in the annealing apparatus shown in FIG. 2A. is there. FIG. 3A is a characteristic diagram showing the results of secondary ion mass spectrometry when impurities are ion-implanted into silicon carbide, and FIG. 3A shows the depth immediately after the impurities are ion-implanted into silicon carbide in the embodiment of the present invention. FIG. 3B is a characteristic diagram showing the impurity concentration with respect to the depth and the frequency of recombination after a predetermined heat treatment is performed after ion implantation. It is a characteristic diagram which shows an example of the impurity distribution of the channel layer of MESFET in embodiment of this invention with the example of the impurity distribution in the conventional epitaxial substrate. It is a characteristic diagram which shows the change characteristic of the drain current with respect to the gate voltage of MESFET in embodiment of this invention with the change characteristic of the drain current with respect to the gate voltage of the silicon carbide MESFET formed using the conventional epitaxial layer. It is explanatory drawing of the manufacturing process of the silicon carbide DMOSFET based on the manufacturing method of the semiconductor device in embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon carbide substrate 4 ... Silicon carbide layer 5 ... Nitride film 6a ... Source electrode 6b ... Drain electrode 7 ... Schottky gate electrode 9 ... Carbon crucible

Claims (3)

A method for manufacturing a semiconductor device, wherein a semiconductor element having a semiconductor layer as an active region is formed on a substrate having a semiconductor layer made of silicon carbide,
Ion implantation of impurities into the semiconductor layer;
After the ion implantation, by performing a heat treatment on the substrate in an atmosphere gas containing at least carbon and silicon, the ion-implanted impurities are activated, and the surface of the semiconductor layer subjected to the ion implantation is activated. Depositing a semiconductor layer of silicon carbide;
Forming an ohmic or Schottky junction electrode in the semiconductor layer;
A method for manufacturing a semiconductor device, comprising: In the step of performing the heat treatment after the ion implantation,
A substrate in which impurities are ion-implanted into a semiconductor layer is placed in a heating container coated with silicon carbide, and the semiconductor layer into which the substrate is ion-implanted is coated with silicon carbide in the heating container. The semiconductor which is stored so as to face the surface and heated so that the portion of the heating container facing the surface of the semiconductor layer reaches a higher temperature than the surface of the semiconductor layer on which the ion implantation has been performed. The space between the layer and the heating container was filled with an atmospheric gas containing a silicon carbide sublimation gas on the surface of the heating container, the impurities implanted by the ion implantation were activated, and the ions were implanted 2. The method of manufacturing a semiconductor device according to claim 1, wherein a semiconductor layer made of silicon carbide is deposited on the surface of the semiconductor layer.   In the step of performing the heat treatment after the ion implantation, a temperature at which a portion of the heating container facing the surface of the semiconductor layer becomes higher in the heating container than the surface of the semiconductor layer implanted with ions. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the heat treatment is performed while maintaining the gradient.

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