JP2009182240A - Semiconductor device manufacturing method and semiconductor device - Google Patents

Abstract

[PROBLEMS] To achieve sufficient reliability while achieving improvement in characteristics, particularly improvement in carrier mobility, by achieving both improvement of the surface state of an SiC layer that can be deteriorated by step bunching and suppression of residual impurity concentration. A semiconductor device manufacturing method and a semiconductor device that can be secured are provided.
A method of manufacturing a MOSFET as a semiconductor device includes a step (S10) of preparing a {0001} plane 4H-SiC substrate having an off angle of 4 ° or less, and a C / Si ratio of 1.2 on a SiC substrate. Under the conditions described above, the step of epitaxially growing the SiC layer (S30), the step of forming facets on the main surface of the SiC layer (S40), and the step of forming the channel region so as to include the main surface ( In steps (S50) to (S60) of forming the channel region, the channel region is formed so that the facet becomes the channel region.
[Selection] Figure 3

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more specifically, a semiconductor device manufacturing method and a semiconductor device using a {0001} plane SiC substrate made of hexagonal silicon carbide and having an off angle of 4 ° or less. About.

  2. Description of the Related Art In recent years, silicon carbide (SiC) is being adopted as a material constituting a semiconductor device in order to enable a semiconductor device such as a transistor to have a high breakdown voltage, low loss, and use in a high temperature environment. Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon (Si) that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  In the method for manufacturing a semiconductor device employing silicon carbide as a material, an SiC substrate having at least one principal surface made of silicon carbide is prepared, and an SiC layer made of silicon carbide is formed on the SiC substrate by epitaxial growth. Process is often included. Further, for the purpose of forming a high-quality SiC layer by this epitaxial growth, the main surface of the SiC substrate may be formed to be slightly inclined (with an off angle) with respect to a predetermined crystal plane. . Specifically, for example, when a SiC layer is formed by epitaxial growth on a {0001} plane SiC substrate made of hexagonal silicon carbide, the main surface of the substrate has an off angle with respect to the {0001} plane. It is formed. At this time, the off-angle is often set to about 8 °, for example.

On the other hand, along with the recent demand for cost reduction of products using semiconductor devices, the cost reduction of semiconductor devices is also required. In order to cope with this, studies have been made to improve the yield of the SiC substrate by reducing the off-angle of the SiC substrate. In this case, the off-angle of the {0001} plane SiC substrate is, for example, 4 ° (see, for example, Non-Patent Document 1).
Keiji Wada et al. , “Epitaxial growth of 4H-SiC on 4 ° off-axis (0001) and (000-1) substrates by hot-wall chemical vapor deposition, Journal of Cryst. 370-374

  However, when the off angle is reduced to about 4 °, the steps formed by the growth of the SiC crystal constituting the SiC layer are integrated on the surface of the SiC layer formed by epitaxial growth on the SiC substrate, and the unevenness becomes severe. The phenomenon (step bunching) is likely to occur. When this step bunching occurs, the density of energy levels at the surface of the SiC layer (when another layer is formed on the SiC layer, the interface with the other layer) increases, for example, at the surface (interface). Carrier mobility is reduced. As a result, the characteristics of the semiconductor device deteriorate. Further, when the off angle is further reduced to 4 ° or less, the step bunching tends to occur more easily.

  On the other hand, when the SiC layer is formed by vapor phase growth using a source gas containing Si (silicon) and a source gas containing C (carbon), C atoms relative to the number of Si atoms in the supplied source gas By reducing the ratio of numbers (hereinafter referred to as C / Si), the occurrence of step bunching can be suppressed. However, when C / Si is reduced, there arises a problem that the concentration of impurities other than the impurities introduced intentionally (residual impurity concentration) increases in the SiC layer. In a semiconductor device employing silicon carbide as a material, a desired operation is possible by forming a region in which the conductivity type and concentration of impurities are controlled in the SiC layer. Therefore, when the residual impurity concentration increases, the reliability of the manufactured semiconductor device may be reduced. In particular, when the residual impurity concentration in the region responsible for the breakdown voltage of the semiconductor device increases, the breakdown voltage of the semiconductor device may decrease. That is, when a SiC substrate having an off angle reduced to 4 ° or less is employed, there arises a problem that it is difficult to achieve both suppression of step bunching and suppression of residual impurity concentration.

  Therefore, the object of the present invention is to achieve both improvement in the characteristics of the SiC layer, which can be deteriorated by step bunching, and suppression of residual impurity concentration, thereby improving characteristics, in particular, improving carrier mobility. It is an object of the present invention to provide a manufacturing method of a semiconductor device and a semiconductor device capable of ensuring sufficient reliability.

  A method of manufacturing a semiconductor device according to the present invention includes a step of preparing a {0001} plane SiC substrate made of hexagonal silicon carbide and having an off angle of 4 ° or less, and C / Si of 1. A step of epitaxially growing a SiC layer made of silicon carbide under a condition of 2 or more, and a second main surface that is a main surface opposite to the first main surface that is the main surface of the SiC layer on the SiC substrate side The step of forming a facet on the second main surface by heating the SiC layer while supplying silicon to the surface, and the step of forming the channel region so as to include the second main surface I have. Then, in the step of forming the channel region, the channel region is formed so that the facet becomes the channel region.

The present inventor has conducted detailed studies on measures for ensuring sufficient reliability of a semiconductor device while suppressing deterioration of the characteristics of the semiconductor device, particularly a decrease in carrier mobility. As a result, the following findings were obtained. That is, by epitaxially growing the SiC layer under the condition that C / Si is 1.2 or more, the residual impurity concentration in the SiC layer is within a range necessary for ensuring sufficient reliability of the semiconductor device, specifically 1 × It can be suppressed to 10 ¹⁵ cm ⁻³ or less, or to 5 × 10 ¹⁴ cm ⁻³ or less, which is a more preferable range. On the other hand, when a SiC layer is formed on a {0001} plane SiC substrate with an off angle of 4 ° or less under the above-described conditions, a SiC layer that can be deteriorated by step bunching is formed by forming facets on the surface. The surface condition can be improved. By forming the channel region so that the facet becomes the channel region, sufficient carrier (electron or hole) mobility (channel mobility) can be ensured in the channel region.

  In the method for manufacturing a semiconductor device of the present invention, an SiC layer is epitaxially grown on a {0001} plane SiC substrate having an off angle of 4 ° or less under a condition that C / Si is 1.2 or more, and then the SiC layer is formed. After forming a facet on the second main surface, a channel region is formed so that the facet becomes a channel region. Therefore, according to the method for manufacturing a semiconductor device of the present invention, by improving both the surface state of the SiC layer that can be deteriorated by step bunching and suppressing the residual impurity concentration, the characteristics of the semiconductor device are improved, particularly the channel movement. It is possible to manufacture a semiconductor device capable of ensuring sufficient reliability while achieving an improvement in degree.

  In addition, in the step of epitaxially growing the SiC layer, if the C / Si exceeds 4, the surface state of the SiC layer that can be deteriorated by step bunching should be sufficiently improved even when the step of forming a facet is performed after that. You may not be able to. Therefore, C / Si is preferably 4 or less. The “off angle is 4 ° or less” includes a case where the off angle is 0, that is, a case where there is no off angle. However, in order to easily suppress the occurrence of step bunching, the off angle is preferably 0.5 ° or more. Further, the {0001} plane SiC substrate having an off angle of 4 ° or less means that the angle formed between the main surface on which the SiC layer is to be formed and the {0001} plane of the crystal constituting the SiC substrate is 4 ° or less. An SiC substrate is referred to and described from another point of view. An SiC formed by a straight line (normal line) perpendicular to the main surface on which the SiC layer is to be formed with respect to the <0001> direction is 4 ° or less. A substrate.

  Preferably, the method for manufacturing a semiconductor device further includes a step of forming a groove on the second main surface after the step of epitaxially growing the SiC layer and before the step of forming the facet. .

  In the step of forming a facet, the facet is formed while affecting each other between adjacent facets. Therefore, a small facet may be formed or the size and orientation of the formed facet may vary. On the other hand, by forming the groove before forming the facet, the facet formed at a position adjacent to the groove grows without being affected by other facets on the side facing the groove. Therefore, a large facet can be formed uniformly. As a result, the characteristics of the semiconductor device can be further improved.

  Preferably, in the method of manufacturing a semiconductor device, an angle formed between the off orientation of the SiC substrate and the <1-100> direction is 10 ° or less. Thereby, it becomes easy to form a large facet with a uniform orientation, and the characteristics of the semiconductor device can be further improved. Here, in order to easily form a large facet with uniform orientation, it is ideal that the off orientation of the SiC substrate is <1-100>. However, if the angle between the off orientation of the SiC substrate and the <1-100> direction is 10 ° or less, a practically sufficient effect is obtained, and if the angle is 5 ° or less, a higher effect is obtained.

  Preferably in the method for manufacturing a semiconductor device, the C / Si ratio in the step of epitaxially growing the SiC layer is 1.5 or more. Thereby, the residual impurity concentration can be further suppressed, and the reliability of the semiconductor device is further improved.

  Preferably in the method for manufacturing a semiconductor device, the C / Si ratio in the step of epitaxially growing the SiC layer is 2 or more. Thereby, the residual impurity concentration can be further suppressed, and the reliability of the semiconductor device is further improved.

  The semiconductor device according to the present invention is manufactured by the semiconductor device manufacturing method of the present invention.

  By being manufactured by the semiconductor device manufacturing method of the present invention, the semiconductor device of the present invention provides a semiconductor device capable of ensuring sufficient reliability while achieving improved characteristics. be able to.

  As is clear from the above description, according to the semiconductor device manufacturing method and the semiconductor device of the present invention, by improving the surface state of the SiC layer that can be deteriorated by step bunching and suppressing the residual impurity concentration, A semiconductor device manufacturing method and a semiconductor device capable of ensuring sufficient reliability of a semiconductor device while achieving improvement in characteristics of the semiconductor device, particularly improvement in carrier mobility, can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view showing a configuration of a MOSFET (Metal Oxide Field Effect Transistor) as a semiconductor device according to the first embodiment which is an embodiment of the present invention. FIG. 2 is an enlarged schematic partial cross-sectional view showing the vicinity of the region α in FIG. With reference to FIGS. 1 and 2, the MOSFET in the first embodiment will be described.

Referring to FIG. 1, MOSFET 1 in the first embodiment is made of silicon carbide (SiC), and is made of n ⁺ SiC substrate 10, which is an n-type (first conductivity type) substrate, SiC, and conductive The n-type (first conductivity type) buffer layer 11 is made of SiC, and the n ⁻ SiC layer 12 as a semiconductor layer is n-type (first conductivity type), and the conductivity type is p-type (first type). A pair of p-type wells 13 as a second conductivity type region of 2 conductivity type, an n ⁺ source region 14 as a high-concentration first conductivity type region of n type conductivity (first conductivity type), and a conductivity type Is provided with a p ⁺ region 18 as a high concentration second conductivity type region of p type (second conductivity type). The n ⁺ SiC substrate 10 is made of hexagonal SiC (4H—SiC) and contains high-concentration n-type impurities (impurities whose conductivity type is n-type). Further, one main surface 10A of the n ⁺ SiC substrate 10 has an off orientation of <1-100> and an off angle of 4 ° with respect to the (0001) Si surface.

Buffer layer 11 is formed on one main surface 10A of n ⁺ SiC substrate 10 and has an n-type conductivity by including an n-type impurity. The n-type impurity contained in the buffer layer 11 is N (nitrogen), for example, and is contained at a lower concentration than the n-type impurity contained in the n ⁺ SiC substrate 10. The n ⁻ SiC layer 12 is formed on the main surface of the buffer layer 11 opposite to the n ⁺ SiC substrate 10 side, and has an n-type conductivity by including an n-type impurity. The n-type impurity contained in the n ⁻ SiC layer 12 is N (nitrogen), for example, and is contained at a lower concentration than the n-type impurity contained in the buffer layer 11.

The pair of p-type wells 13 includes a second main surface 12B which is a main surface opposite to the first main surface 12A which is the main surface on the n ⁺ SiC substrate 10 side in the n ⁻ SiC layer 12. And p-type impurities (impurities whose conductivity type is p-type), so that the conductivity type is p-type (second conductivity type). The p-type impurity contained in the p-type well 13 is, for example, aluminum (Al), boron (B), or the like, and is contained at a lower concentration than the n-type impurity contained in the n ⁺ SiC substrate 10.

N ⁺ source region 14 includes second main surface 12 ^</ b ^> B and is formed inside each of the pair of p-type wells 13 so as to be surrounded by p-type well 13. The n ⁺ source region 14 contains an n-type impurity such as phosphorus (P) at a higher concentration than the n-type impurity contained in the n ⁻ SiC layer 12. p ⁺ region 18, when viewed from n ⁺ source region 14 formed in the interior of one of the p-type well 13 of the pair of p-type well 13, n ⁺ source formed within the other p-type well 13 On the side opposite to the region 14, the second main surface 12 </ b> B is formed. The p ⁺ region 18 contains a p-type impurity, such as Al or B, at a higher concentration than the p-type impurity contained in the p-type well 13.

  Further, referring to FIG. 1, MOSFET 1 includes a gate oxide film 15 as a gate insulating film, a gate electrode 17, a pair of source contact electrodes 16, a source electrode 19, and a drain electrode 20.

A gate oxide film 15 is in contact with second main surface 12B, ⁿ so as to extend from the upper surface of one ^{n +} source region 14 to the top surface of the other ^{n +} source regions 14 - SiC layer 12 It is formed on second main surface 12B and is made of, for example, silicon dioxide (SiO ₂ ).

Gate electrode 17 is arranged in contact with gate oxide film 15 so as to extend from one n ⁺ source region 14 to the other n ⁺ source region 14. The gate electrode 17 is made of a conductor such as polysilicon or Al.

Source contact electrode 16 extends from each of the pair of n ⁺ source regions 14 to p ⁺ region 18 in a direction away from gate oxide film 15 and is in contact with second main surface 12B. ing. The source contact electrode 16 is made of a material capable of ohmic contact with the n ⁺ source region 14 such as NiSi (nickel silicide).

The source electrode 19 is formed in contact with the source contact electrode 16 and is made of a conductor such as Al. The source electrode 19 is electrically connected to the n ⁺ source region 14 via the source contact electrode 16.

The drain electrode 20 is formed in contact with the other main surface 10B which is the main surface opposite to the one main surface 10A which is the main surface on the side where the n ⁻ SiC layer 12 is formed in the n ⁺ SiC substrate 10. Has been. The drain electrode 20 is made of a material that can be in ohmic contact with the n ⁺ SiC substrate 10 such as NiSi, and is electrically connected to the n ⁺ SiC substrate 10.

  Further, referring to FIGS. 1 and 2, channel region 13 </ b> A that is in the vicinity of contact with gate oxide film 15 of p-type well 13 and in which an inversion layer is to be formed during the operation of MOSFET 1 described later. A facet 121 is formed on the surface. The facet 121 includes a first surface 121A that is a {0001} surface and a second surface 121B that is a surface that intersects the first surface 121A. In the present embodiment, facet 121 is formed over the entire area of second main surface 12B.

Next, the operation of MOSFET 1 will be described. Referring to FIGS. 1 and 2, when the voltage of gate electrode 17 is 0 V, that is, in the off state, a reverse bias is applied between p-type well 13 and n ⁻ SiC layer 12 located immediately below gate oxide film 15. Thus, a non-conduction state is established. On the other hand, when a positive voltage is applied to the gate electrode 17, an inversion layer is formed in the channel region 13 </ b> A near the gate oxide film 15 of the p-type well 13. As a result, n ⁺ source region 14 and n ⁻ SiC layer 12 are electrically connected, and a current flows between source electrode 19 and drain electrode 20.

  Here, MOSFET 1 in the first embodiment is manufactured by the method for manufacturing a semiconductor device in the first embodiment, which is one embodiment of the present invention described later. As a result, it is a semiconductor device (MOSFET) capable of ensuring sufficient reliability while achieving improved characteristics.

  Next, a method for manufacturing a MOSFET as a semiconductor device according to the first embodiment, which is an embodiment of a method for manufacturing a semiconductor device according to the present invention, will be described. FIG. 3 is a flowchart showing an outline of a method of manufacturing a MOSFET in the first embodiment. 4 to 10 are schematic cross-sectional views for explaining the MOSFET manufacturing method in the first embodiment. 6 and 8 are enlarged views showing the vicinity of the region β in FIG. 5 and the vicinity of the region γ in FIG.

Referring to FIG. 3, in the MOSFET manufacturing method in the first embodiment, a substrate preparation step is first performed as a step (S10). In this step (S10), a first conductivity type SiC substrate is prepared. Specifically, referring to FIG. 4, an n ⁺ SiC substrate 10 made of, for example, hexagonal SiC and having an n-type conductivity by including an n-type impurity is prepared. One main surface 10A of the n ⁺ SiC substrate 10 has an off orientation of <1-100> and an off angle of 4 ° with respect to the (0001) Si surface.

Next, with reference to FIG. 3, a buffer layer formation process is implemented as process (S20). In this step (S ^< b> 20), a first conductivity type buffer layer is formed on n ⁺ SiC substrate 10. Specifically, referring to FIG. 4, buffer layer 11 is formed on one main surface 10 ^</ b ^{> A} of n ⁺ SiC substrate 10 by epitaxial growth. Epitaxial growth can be performed, for example, by using a mixed gas of SiH ₄ (silane) and C ₃ H ₈ (propane) as a source gas. At this time, for example, nitrogen is introduced as an n-type impurity. Thereby, the buffer layer 11 containing the n-type impurity having a lower concentration than the n-type impurity contained in the n ⁺ SiC substrate 10 can be formed.

Next, with reference to FIG. 3, an n-type layer forming step is performed as a step (S30). In this step (S <b> 30), a first conductivity type semiconductor layer is formed on the buffer layer 11. Specifically, referring to FIG. 4, n ⁻ SiC layer 12 is formed on buffer layer 11 by epitaxial growth. Epitaxial growth can be performed in the same manner as in the above step (S20). Thereby, the n ⁻ SiC layer 12 containing an n-type impurity having a lower concentration than the n-type impurity contained in the buffer layer 11 can be formed. Here, in the step (S30), C / Si, which is the ratio of C atoms to the number of Si atoms contained in SiH ₄ and C ₃ H ₈ used as the source gas, is 1.2 or more. Thus, the residual impurity concentration in the n ⁻ SiC layer 12 is within a range necessary for ensuring sufficient reliability of the MOSFET 1, specifically, 1 × 10 ¹⁵ cm ⁻³ or less, or more preferably 5 × 10 ¹⁴ cm. ^-3 or less.

Next, referring to FIG. 3, a facet forming step is performed as a step (S40). In this step (S40), silicon (Si) is applied to the second main surface 12B which is the main surface opposite to the first main surface 12A of the n ⁻ SiC layer 12 on the n ⁺ SiC substrate 10 side. By heating the n ⁻ SiC layer 12 while supplying, facets are formed on the second major surface 12B. Specifically, referring to FIG. 5, first, Si film 31 made of Si is formed on second main surface 12B. The formation of the Si film 31 can be performed, for example, by a vapor deposition method. Next, the n ⁻ SiC layer 12 on which the Si film 31 is formed is heated to a predetermined temperature. Thereby, the n ⁻ SiC layer 12 is heated while Si is supplied from the Si film 31 to the second main surface 12B. Thereby, as shown in FIG. 6, the facet 121 is formed in the 2nd main surface 12B. Here, the heating temperature is preferably 1450 ° C. or higher, more preferably 1600 ° C. or higher, from the viewpoint of promoting the formation of facets. On the other hand, from the viewpoint of suppressing SiC sublimation, the heating temperature is preferably 2000 ° C. or lower, and more preferably 1800 ° C. or lower.

Next, referring to FIG. 3, a p-type well formation step is performed as a step (S50). In this step (S50), referring to FIG. 5 and FIG. 6, after Si film 31 formed in step (S40) is removed by, for example, wet etching, n ^- SiC is referred to with reference to FIG. In the layer 12, the second conductivity type of the second conductivity type is included so as to include the second main surface 12B which is the main surface opposite to the first main surface 12A which is the main surface on the n ⁺ SiC substrate 10 side. A region is formed. Specifically, first, an oxide film made of SiO ₂ is formed on second main surface 12B by, for example, CVD. Then, after a resist is applied on the oxide film, exposure and development are performed to form a resist film having an opening in a region corresponding to the shape of the p-type well 13 as a desired second conductivity type region. . Then, by using the resist film as a mask, the oxide film is partially removed by, for example, RIE (Reactive Ion Etching), so that the oxide film having an opening pattern on the n ⁻ SiC layer 12 is removed. A mask layer is formed. Thereafter, after removing the resist film, ion implantation is performed on the n ⁻ SiC layer 12 using the mask layer as a mask, whereby the p-type well 13 is formed in the n ⁻ SiC layer 12.

Next, with reference to FIG. 3, an n ⁺ region forming step is performed as a step (S60). In this step (S60), a high-concentration first conductivity type region containing a first conductivity type impurity having a concentration higher than that of the n ⁻ SiC layer 12 is formed in a region including the second main surface 12B in the p-type well 13. It is formed. Specifically, referring to FIG. 7, first, the oxide film used as a mask in step (S50) is removed, and then the desired n ⁺ source region is obtained in the same procedure as in step (S50). A mask layer having an opening in a region corresponding to the shape of 14 is formed. Then, using the mask layer as a mask, an n-type impurity such as phosphorus (P) is introduced into the n ⁻ SiC layer 12 by ion implantation, whereby the n ⁺ source region 14 is formed.

Here, referring to FIGS. 7 and 8, p-type well 13 and n ⁺ source region 14 are formed in steps (S50) and (S60) so that facet 121 becomes channel region 13A. The channel region 13A is formed so as to include the second main surface 12B. That is, the channel region 13A is formed to include the facet 121. Thus, sufficient carrier (electron or hole) mobility (channel mobility) can be ensured in the channel region 13A.

Next, referring to FIG. 3, a p ⁺ region forming step is performed as a step (S70). In this step (S70), referring to FIG. 7, when viewed from the n ⁺ source region 14 formed inside one p-type well 13 of the pair of p-type wells 13, A high-concentration second conductivity type region (p ⁺ region 18) is formed on the side opposite to the n ⁺ source region 14 formed inside so as to include the second main surface 12B. Specifically, referring to FIG. 7, a mask layer having an opening in a region corresponding to the shape of desired p ⁺ region 18 is formed in the same procedure as in steps (S50) and (S60). P ⁺ region 18 is formed by introducing p-type impurities such as Al and B into the n ⁻ SiC layer 12 by ion implantation.

Next, referring to FIG. 3, an activation annealing step is performed as a step (S80). In this step (S80), activation annealing, which is a heat treatment for activating the impurities introduced by the ion implantation, is performed by heating the n ^- SiC layer 12 subjected to the ion implantation.

Next, with reference to FIG. 3, a gate insulating film formation process is implemented as process (S90). In this step (S90), referring to FIG. 9, the steps of steps (S10) to (S80) are performed, and n ⁺ SiC substrate 10 on which n ⁻ SiC layer 12 including a desired ion implantation layer is formed is heated. Oxidized. Thereby, a thermal oxide film 15A to be a gate oxide film 15 (see FIG. 1) made of silicon dioxide (SiO ₂ ) is formed on the second main surface 12B.

Next, referring to FIG. 3, a drain electrode formation step and an ohmic electrode formation step are performed as steps (S100) and (S110). In the step (S100), for example, a nickel (Ni) film formed by vapor deposition is heated and silicided. Thus, as shown in FIG. ^10, n + SiC substrate 10 and the drain electrode 20 made of ohmic contact can NiSi ^is, in n + SiC substrate 10 ⁿ - mainly opposite to the side on which the SiC layer 12 is formed It is formed so as to contact the surface. Further, in the step (S110), similarly to the step (S100), for example, a Ni film formed by vapor deposition is heated to be silicided to be made of NiSi (nickel silicide), and the n ⁺ source region 14 and A pair of source contact electrodes 16 in ohmic contact extends from each of the pair of n ⁺ source regions 14 to the p ⁺ region 18 in a direction away from the gate oxide film 15, so as to extend from the second main surface 12 B. Formed in contact with. Here, the steps (S100) and (S110) can be performed simultaneously by forming a Ni film in a desired region by, for example, a vapor deposition method and heating it to silicide it.

Next, with reference to FIG. 3, a gate electrode formation process is implemented as process (S120). In this step (S120), for example, Al is a conductor, a gate electrode 17 made of polysilicon (see FIG. 1), extends from the top one ^{n +} source region 14 to above the other ^{n +} source regions 14 In addition, the gate oxide film 15 is formed in contact with the gate oxide film 15.

  Next, with reference to FIG. 3, a source electrode formation process is implemented as process (S130). In this step (S130), the source electrode 19 (see FIG. 1) made of Al as a conductor is formed on the upper surface of the source contact electrode 16, for example, by vapor deposition. Through the above steps (S10) to (S130), the MOSFET 1 manufacturing method as the semiconductor device in the first embodiment is completed, and the MOSFET 1 (see FIG. 1) of the first embodiment is completed.

In the MOSFET manufacturing method according to the first embodiment, a process (on the hexagonal n ⁺ SiC substrate 10 having an off angle of 4 ° or less (4 ° in the present embodiment) and an off orientation of <1-100> ( In S30), after epitaxially growing the n ⁻ SiC layer 12 under the condition that C / Si is 1.2 or more, the facet 121 is formed on the second main surface 12B of the n ⁻ SiC layer 12, The channel region 13A is formed so that the facet 121 becomes the channel region 13A. Therefore, according to the method for manufacturing MOSFET 1 in the present embodiment, the improvement of the characteristics, particularly the channel, can be achieved by satisfying both the improvement of the surface state of n ⁻ SiC layer 12 that can be deteriorated by step bunching and the suppression of the residual impurity concentration. MOSFET 1 capable of ensuring sufficient reliability while achieving improvement in mobility can be manufactured.

(Embodiment 2)
Next, a method for manufacturing a semiconductor device according to the second embodiment, which is another embodiment of the present invention, will be described. FIG. 11 is a schematic cross-sectional view for illustrating the method for manufacturing the MOSFET in the second embodiment. FIG. 11 corresponds to an enlarged view of the vicinity of the region γ in FIG. The method of manufacturing a MOSFET as a semiconductor device in the second embodiment is basically performed in the same manner as in the first embodiment. However, referring to FIG. 3, Embodiment 2 differs from Embodiment 1 in Step (S50) and Step (S60).

That is, in the MOSFET manufacturing method in the second embodiment, the p-type well 13 and the n ⁺ source region 14 are formed in the step (S50) and the step (S60), whereby the second main surface 12B in the channel region 13A. Are included in a single facet 121, channel region 13A is formed. Thereby, the unevenness of the second main surface in the channel region 13A is suppressed, and the channel mobility is further improved.

(Embodiment 3)
Next, a method for manufacturing a semiconductor device according to the third embodiment which is still another embodiment of the present invention will be described. FIG. 12 is a flowchart showing an outline of a MOSFET manufacturing method according to the third embodiment. 13 to 15 are schematic cross-sectional views for explaining the method of manufacturing the MOSFET in the third embodiment. 13, FIG. 14, and FIG. 15 correspond to enlarged views of the vicinity of the region δ in FIG. 4, the vicinity of the region β in FIG. 5, and the vicinity of the region γ in FIG. The method of manufacturing a MOSFET as a semiconductor device in the third embodiment is basically performed in the same manner as in the first embodiment. However, referring to FIG. 12 and FIG. 3, Embodiment 3 is implemented in that the groove forming step is performed as step (S140) after step (S30) and before step (S40). This is different from Form 1.

That is, in the method for manufacturing a MOSFET in the third embodiment, the steps (S10) to (S30) are performed as in the first embodiment, and then the step (S140) is performed. In this step (S140), a groove is formed in a region including second main surface 12B. Specifically, referring to FIGS. 4 and 13, groove 32 is formed in a region including second main surface 12 </ b> B of n ⁻ SiC layer 12 formed by performing steps (S <b> 10) to (S <b> 30). It is formed. The groove 32 can be formed by RIE, for example. Here, a plurality of grooves 32 are parallel to each other at equal intervals in a direction perpendicular to the <1-100> direction that is the off orientation of n ⁺ SiC substrate 10 (the direction from the back to the front in FIG. 13). Formed.

Next, referring to FIG. 12, step (S40) is performed in the same manner as in the first embodiment. At this time, since the groove 32 is formed in the step (S140), the facet 121 to be formed can grow without being affected by the other facet 121 on the side facing the groove 32. Therefore, as shown in FIG. 14, large facets 121 are uniformly formed in the step (S40). Then, in step (S50) and step (S60), as in the case of the second embodiment, p-type well 13 and n ⁺ source region 14 are formed, so that the second main surface in channel region 13A is formed. The channel region 13A is formed so that 12B is included in the single facet 121 (see FIG. 15). Here, in the present embodiment, since the large facets 121 are uniformly formed in the step (S40), the second main surface 12B in the channel region 13A is included in the single facet 121. Thus, it is easy to form the channel region 13A. And channel mobility is further improved by forming channel region 13A using a large facet.

  Embodiment 1 of the present invention will be described below. A TEG (Test Element Group) is manufactured using a process similar to the method for manufacturing a semiconductor device of the present invention, and an experiment for evaluating MOS channel mobility and an experiment for actually manufacturing a MOSFET and measuring on-resistance are performed. It was. The experimental procedure is as follows.

First, steps (S10) to (S40) were performed in the same process as in the first embodiment. Here, in step (S10), a 4H—SiC substrate (n ⁺ SiC substrate 10) having an off angle of 4 ° and an off orientation of <1-100> with respect to the (0001) Si plane was prepared. In the step (S30), the n ⁻ SiC layer 12 was formed by epitaxial growth under the condition of C / Si of 1.2. In the step (S40), after the Si film 31 is formed, a heat treatment is performed for 30 minutes at 1700 ° C. in an argon gas atmosphere, whereby the facet 121 is formed.

Next, a TEG for evaluating the MOS channel mobility was fabricated using the substrate with an epitaxial layer (epi substrate) fabricated as described above. A vertical MOSFET (channel length: 2 μm) was fabricated using the same epi substrate. ^Here, n - the thickness of the SiC layer 12 is 10 [mu] ^m, n - Concentration of n-type impurities in SiC layer 12 was set to 5 × ¹⁰ 15 ^{cm -3} (Example).

  On the other hand, for comparison, the step (S40) which is the step of forming facets in the above procedure is omitted, and an epitaxial substrate is similarly produced, and the same TEG and vertical MOSFET are produced using this (Comparative example) ). Then, the MOS channel mobility and the characteristic on-resistance were measured using the TEGs and vertical MOSFETs of the above examples and comparative examples.

Next, the results of the experiment will be described. The channel mobility in the above example was 100 cm ² / V · s and the characteristic on resistance was 5 mΩ · cm ² , whereas the channel mobility in the comparative example was 20 cm ² / V · s and the characteristic on resistance was 15 mΩ · cm ^2. cm ² . From this, it was confirmed that according to the method for manufacturing a semiconductor device of the present invention, a semiconductor device capable of realizing high channel mobility and low on-resistance can be manufactured.

  Embodiment 2 of the present invention will be described below. When the SiC layer was formed on the 4H—SiC substrate by epitaxial growth, an experiment was conducted to investigate the relationship between C / Si and the residual impurity concentration in the SiC layer. The experimental procedure is as follows.

  First, a 4H—SiC substrate having an off angle of 4 ° and an off orientation of <1-100> with respect to the (0001) Si plane was prepared. Then, the SiC layer was epitaxially grown on the main surface of the substrate under various C / Si without intentionally introducing impurities, and the residual impurity concentration in the SiC layer was measured.

  Next, the results of the experiment will be described. FIG. 16 is a diagram showing experimental results in Example 2. In FIG. 16, the horizontal axis indicates C / Si, and the vertical axis indicates the residual impurity concentration that is a value obtained by subtracting the concentration of p-type impurities from the concentration of n-type impurities. The broken lines in the figure indicate the upper and lower limit values of the allowable range of the residual impurity concentration when the reliability of the semiconductor device, particularly the breakdown voltage is taken into consideration.

  Referring to FIG. 16, when C / Si is 1.2 or more, the residual impurity concentration is drastically reduced and falls within the allowable range of the residual impurity concentration. When C / Si is 1.5 or more, the residual impurity concentration is further reduced, and when C / Si is 2.0 or more, it is a lower value. Therefore, in consideration of the reliability of the semiconductor device, particularly the breakdown voltage, the value of C / Si when epitaxially growing the SiC layer needs to be 1.2 or more, and C / Si is 1.5 or more. It was confirmed that it was preferably 2.0 or more.

  In the above-described embodiments and examples, the vertical MOSFET is taken as an example of a semiconductor device to which the semiconductor device manufacturing method of the present invention can be applied. However, the semiconductor device manufacturing method of the present invention can be applied. The semiconductor device is not limited to this. As a semiconductor device to which the semiconductor device manufacturing method of the present invention can be applied, in addition to a vertical MOSFET, for example, an IGBT (Insulated Gate Bipolar Transistor), a MESFET (Metal Semiconductor Field Effect Transistor), a metal semiconductor field effect transistor ) And the like.

  In addition, when describing a crystal plane and a crystal direction, when describing a negative numerical value, it is common to indicate a bar on the numerical value, but the claims, description, abstract, drawings of the present application In FIG. 4, for convenience, “− (minus)” is added before the numerical value.

  The embodiments and examples disclosed herein are illustrative in all respects and should not be construed as being restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  INDUSTRIAL APPLICABILITY The semiconductor device manufacturing method and semiconductor device of the present invention are particularly advantageously applied to a semiconductor device manufacturing method and a semiconductor device using a {0001} plane SiC substrate made of hexagonal silicon carbide and having an off angle of 4 ° or less. Can be done.

1 is a schematic cross-sectional view showing a configuration of a MOSFET as a semiconductor device in a first embodiment. FIG. 2 is a schematic partial cross-sectional view showing an area α in FIG. 1 in an enlarged manner. 3 is a flowchart showing an outline of a method for manufacturing a MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 6 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the first embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the second embodiment. 10 is a flowchart showing an outline of a method of manufacturing a MOSFET in a third embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the third embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the third embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET in the third embodiment. It is a figure which shows the experimental result in Example 2. FIG.

Explanation of symbols

1 MOSFET, 10 n ⁺ SiC substrate, 10A one main surface, 10B the other main surface, 11 buffer layer, 12 n ⁻ SiC layer, 12A first main surface, 12B second main surface, 13 p-type well, 13A channel region, 14 n ⁺ source region, 15 gate oxide film, 15A thermal oxide film, 16 source contact electrode, 17 gate electrode, 18 p ⁺ region, 19 source electrode, 20 drain electrode, 31 Si film, 32 groove, 121 Facet, 121A first side, 121B second side.

Claims (6)

A step of preparing a {0001} plane SiC substrate made of hexagonal silicon carbide and having an off angle of 4 ° or less;
Epitaxially growing a SiC layer made of silicon carbide on the SiC substrate under a condition that C / Si is 1.2 or more;
By heating the SiC layer while supplying silicon to the second main surface which is the main surface opposite to the first main surface which is the main surface on the SiC substrate side of the SiC layer. Forming facets on the second main surface;
Forming a channel region so as to include the second main surface,
The method of manufacturing a semiconductor device, wherein in the step of forming the channel region, the channel region is formed so that the facet becomes the channel region.   2. The semiconductor device according to claim 1, further comprising a step of forming a groove in the second main surface after the step of epitaxially growing the SiC layer and before the step of forming the facet. Manufacturing method.   3. The method of manufacturing a semiconductor device according to claim 1, wherein an angle between the off orientation of the SiC substrate and the <1-100> direction is 10 ° or less.   The method for manufacturing a semiconductor device according to claim 1, wherein C / Si in the step of epitaxially growing the SiC layer is 1.5 or more.   The method for manufacturing a semiconductor device according to claim 1, wherein C / Si in the step of epitaxially growing the SiC layer is 2 or more.   A semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 1.

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