JP2015095511A - Silicon carbide semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device with improved withstand voltage characteristics.SOLUTION: A MOSFET1 comprises: a silicon carbide layer 11 provided with a trench TR which is opened on the side of one main surface 11A and has a sidewall surface SW forming an obtuse angle with respect to the one main surface 11A; and an insulating film 20 extending from the inside of the trench TR to the one main surface 11A. The sidewall surface SW includes a channel region CH. The thickness of an upper portion of the trench TR, which is the shortest distance from an upper end portion UT to a surface of the insulating film 20, is greater than the thickness of the insulating film 20 on the channel region CH.

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same, and more specifically to a silicon carbide semiconductor device with improved breakdown voltage characteristics and a method for manufacturing the same.

  In recent years, in order to enable a semiconductor device to have a high breakdown voltage and low loss, silicon carbide has been adopted as a material constituting the semiconductor device. Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material constituting a semiconductor device. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  An example of a semiconductor device using silicon carbide as a material is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). A MOSFET is a semiconductor device that controls whether or not an inversion layer is formed in a channel region with a predetermined threshold voltage as a boundary, thereby conducting and interrupting current. For example, in Japanese translations of PCT publication No. 2000-509559 (hereinafter referred to as Patent Document 1), a gate trench is formed in an epitaxial layer made of silicon carbide, and an insulator layer is formed so as to be in contact with the side wall and bottom of the gate trench. MOSFETs have been proposed.

JP 2000-509559 A

  The MOSFET proposed in Patent Document 1 has a problem that the insulating layer covering the upper end of the gate trench tends to be thin, and as a result, the breakdown voltage characteristic of the MOSFET is lowered.

  The present invention has been made in view of the above problems, and an object thereof is to provide a silicon carbide semiconductor device with improved breakdown voltage characteristics and a method for manufacturing the same.

  A silicon carbide semiconductor device according to the present invention includes a silicon carbide layer in which a trench having a wall surface opened to one main surface and having an obtuse angle with respect to the one main surface is formed. And an insulating film extending to the main surface. The wall surface includes a channel region. The thickness of the upper end of the insulating film, which is the shortest distance from the upper end of the trench to the surface of the insulating film, is larger than the thickness of the insulating film on the channel region.

  A method for manufacturing a silicon carbide semiconductor device according to the present invention includes a step of forming a silicon carbide layer including one main surface, and an opening is formed on the one main surface side to form an obtuse angle with respect to the one main surface. And forming a trench having a wall surface including a channel region in the silicon carbide layer and forming an insulating film extending from the inside of the trench to the one main surface. In the step of forming the insulating film, the insulating film is formed so that the thickness of the upper end of the insulating film, which is the shortest distance from the upper end of the trench to the surface of the insulating film, is larger than the thickness of the insulating film on the channel region. The

  According to the silicon carbide semiconductor device and the manufacturing method thereof according to the present invention, it is possible to provide a silicon carbide semiconductor device with improved breakdown voltage characteristics and a manufacturing method thereof.

1 is a cross sectional view schematically showing a structure of a silicon carbide semiconductor device according to Embodiment 1. FIG. 1 is an enlarged schematic sectional view showing a structure of a silicon carbide semiconductor device according to Embodiment 1. FIG. 3 is a flowchart schematically showing a method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 6 is a schematic diagram for illustrating steps (S10) and (S20) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is the schematic for demonstrating the process (S30) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is the schematic for demonstrating the process (S40) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. It is the schematic for demonstrating the process (S50) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. FIG. 10 is another schematic diagram for illustrating a step (S50) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. FIG. 8 is still another schematic diagram for illustrating a step (S50) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is the schematic for demonstrating the process (S60) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. FIG. 7 is a schematic diagram for illustrating steps (S70) and (S80) in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment. It is the schematic for demonstrating the process (S90) in the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1. FIG. 5 is a flowchart schematically showing a method for manufacturing a silicon carbide semiconductor device according to a second embodiment. FIG. 10 is a schematic diagram for illustrating a step (S150) in the method for manufacturing a silicon carbide semiconductor device according to the second embodiment. FIG. 10 is a schematic diagram for illustrating a step (S160) in the method for manufacturing a silicon carbide semiconductor device according to the second embodiment. FIG. 12 is another schematic diagram for illustrating a step (S160) in the method for manufacturing the silicon carbide semiconductor device according to the second embodiment.

[Description of Embodiment of Present Invention]
First, the contents of the embodiments of the present invention will be listed and described.

  (1) The silicon carbide semiconductor device (MOSFET 1) according to the present embodiment has a trench (TR) having a wall surface (SW) that opens to one main surface (11A) and forms an obtuse angle with respect to the one main surface. And a dielectric film (20) extending from the inside of the trench to the one main surface. The wall surface includes a channel region (CH). The thickness (T2) of the upper end of the insulating film, which is the shortest distance from the upper end (UT) of the trench to the surface of the insulating film, is larger than the thickness (T1) of the insulating film on the channel region.

  In the MOSFET 1, the upper end thickness T2 of the insulating film 20 which is the shortest distance from the upper end UT of the trench TR to the surface of the insulating film 20 (the insulating film 20 in the direction along the main surface 11A from the upper end UT of the trench TR). The thickness T2) is larger than the thickness T1 of the insulating film 20 on the channel region CH. As a result, the upper end portion UT of the trench TR where electric field concentration is likely to occur can be covered with the insulating film 20 having a sufficient thickness while maintaining the thickness of the insulating film 20 on the channel region CH. Therefore, according to the MOSFET 1, the breakdown voltage characteristic can be further improved.

  (2) In the silicon carbide semiconductor device (MOSFET 1), the silicon carbide layer (11) includes one main surface (11A) and a source region (14) constituting a part of the wall surface (SW), and the source region And a body region (13) having a channel region (CH) and constituting a part of the wall surface. The insulating film (20) extends from the bottom (bottom surface BW) of the trench (TR) along the wall surface to the boundary between the source region and the body region, and then reaches the upper end (UT) of the trench. Is formed to be large.

  Thereby, the upper end thickness T2 of the insulating film 20 in the upper end UT of the trench TR can be increased while maintaining the thickness of the insulating film 20 on the channel region CH. As a result, the breakdown voltage characteristics can be improved while maintaining the characteristics of the MOSFET 1.

  (3) In the silicon carbide semiconductor device (MOSFET 1), the insulating film (20) is formed of a multilayer film on one main surface (11A) side from the boundary between the source region (14) and the body region (13). Has been.

  Thereby, it becomes easy to increase the thickness of the insulating film 20 at the upper end portion of the trench TR while maintaining the thickness of the insulating film 20 on the channel region CH.

  (4) In the silicon carbide semiconductor device (MOSFET 1), the multilayer film is formed on the silicon carbide layer (11), and includes a lower insulating film (gate oxide film 22) made of silicon dioxide, aluminum nitride, aluminum oxide, It is made of one material selected from the group consisting of silicon dioxide and silicon nitride, and includes an upper insulating film (protective insulating film 21) formed on the lower insulating film.

  As described above, the upper insulating film and the lower insulating film constituting the multilayer film can be made of various insulating materials.

  (5) In the silicon carbide semiconductor device (MOSFET 1), the upper end thickness (T2) of the insulating film 20 is 1.5 times or more the thickness (T1) of the insulating film on the channel region (CH).

  Thereby, the upper end portion UT of the trench TR can be more reliably covered with the insulating film 20. As a result, the breakdown voltage characteristics of the MOSFET 1 can be further improved.

  (6) In the silicon carbide semiconductor device (MOSFET 1), the upper end thickness (T2) of the insulating film 20 is 75 nm or more.

  Thereby, the upper end portion UT of the trench TR can be more reliably covered with the insulating film 20. As a result, the breakdown voltage characteristics of the MOSFET 1 can be further improved.

  (7) In the silicon carbide semiconductor device (MOSFET 1), the thickness (T3) of the insulating film (20) on one main surface (11A) is larger than the upper end thickness (T2) of the insulating film (20). ing.

  Thereby, main surface 11A of silicon carbide layer 11 can be reliably protected by insulating film 20.

  (8) In the silicon carbide semiconductor device (MOSFET 1), the wall surface (SW) of the trench (TR) has an off angle of 50 ° to 70 ° with respect to the {0001} plane of silicon carbide.

  Thereby, the mobility of carriers along the side wall surface SW in the channel region CH can be further improved.

  (9) A method for manufacturing a silicon carbide semiconductor device according to the present embodiment includes a step of forming a silicon carbide layer (11) including one main surface (11A), the one main surface side, and the one side Forming a trench (TR) in the silicon carbide layer having an obtuse angle with respect to the main surface and having a wall surface (SW) including the channel region (CH) on the one main surface from the inside of the trench (TR) Forming an insulating film (20) extending up to. In the step of forming the insulating film, the thickness of the upper end portion (T2) of the insulating film, which is the shortest distance from the upper end portion (UT) of the trench to the surface of the insulating film, is larger than the thickness (T1) of the insulating film on the channel region. An insulating film is formed to be large.

  In the method for manufacturing the silicon carbide semiconductor device, the upper end thickness T2 of the insulating film 20 (the thickness T2 of the insulating film 20 in the direction along the main surface 11A from the upper end UT of the trench TR) is the insulating film on the channel region CH. The insulating film 20 is formed so as to be larger than the thickness T <b> 1 of 20. As a result, the upper end portion UT of the trench TR where electric field concentration is likely to occur can be covered with the insulating film 20 having a sufficient thickness while maintaining the thickness of the insulating film 20 on the channel region CH. Therefore, according to the method for manufacturing the silicon carbide semiconductor device, MOSFET 1 with improved breakdown voltage characteristics can be manufactured.

  (10) In the method for manufacturing the silicon carbide semiconductor device, the step of forming the insulating film (20) includes vapor phase deposition of an upper insulating film (protective insulating film 21) covering the upper end portion (UT) of the trench (TR). After the upper insulating film is formed, an insulating film is formed together with the upper insulating film, and a lower insulating film (gate oxide film 22) covering the upper end of the trench and the wall surface (SW) is formed by thermal oxidation. And a process of performing.

  Thereby, the thickness of the gate oxide film 22 can be controlled more precisely than in the case where the protective insulating film 21 is formed after the gate oxide film 22 is formed. Further, by covering the upper end portion UT of the trench TR with both the protective insulating film 21 and the gate oxide film 22, the upper end portion UT of the trench TR can be more reliably protected by the insulating film 20.

  (11) In the method for manufacturing the silicon carbide semiconductor device, the step of forming the insulating film (20) includes the step of forming a lower insulating film (gate oxide film 22) covering the upper end (UT) and the wall surface (SW) of the trench (TR). After the lower insulating film is formed, the insulating film is formed together with the lower insulating film, and the upper insulating film (protective insulating film 21) covering the upper end portion (UT) of the trench is vapor-deposited. Forming by a method.

  Thereby, when the protective insulating film 21 is formed, the interface between the sidewall surface SW of the trench TR and the gate oxide film 22 can be prevented from being damaged. Further, by covering the upper end portion UT of the trench TR with both the protective insulating film 21 and the gate oxide film 22, the upper end portion UT of the trench TR can be more reliably protected by the insulating film 20.

[Details of the embodiment of the present invention]
Next, specific examples of embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the present specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number.

(Embodiment 1)
First, the structure of the silicon carbide semiconductor device according to the first embodiment which is an embodiment of the present invention will be described. Referring to FIG. 1, MOSFET 1 which is a silicon carbide semiconductor device according to the present embodiment includes a silicon carbide (SiC) substrate 10, a silicon carbide (SiC) layer 11, an insulating film 20, a gate electrode 30, and a source. The electrode 40, the interlayer insulating film 50, the source wiring 60, and the drain electrode 70 are mainly provided.

  SiC layer 11 includes a drift region 12, a body region 13, a source region 14, and a contact region 15. SiC layer 11 has a trench TR that opens to one main surface 11A side. Trench TR has side wall surface SW that forms an obtuse angle (more than 90 ° and less than 180 °) with respect to main surface 11A, and bottom surface BW (bottom) that is connected to and is parallel to main surface 11A. ing. Side wall surface SW has an off angle of 50 ° or more and 70 ° or less with respect to the {0001} plane of silicon carbide, and more specifically is a {0-33-8} plane.

  Trench TR is formed to reach drift region 12 through source region 14 and body region 13. More specifically, trench TR is formed such that side wall surface SW is constituted by source region 14, body region 13 and drift region 12, and bottom surface BW is located in drift region 12. Side wall surface SW includes a channel region CH that is a region where an inversion layer is formed in body region 13 during operation of MOSFET 1.

SiC substrate 10 has a main surface 10A and a main surface 10B opposite to main surface 10A, and has an n-type conductivity by containing an n-type impurity such as nitrogen (N), for example. . Drift region 12 includes side wall surface SW and bottom surface BW of trench TR, and is formed on main surface 10 </ b> A of SiC substrate 10. Drift region 12 has an n-type conductivity by containing an n-type impurity such as nitrogen (N). The n-type impurity concentration in drift region 12 is, for example, about 4 × 10 ¹⁵ cm ⁻³ , which is lower than the n-type impurity concentration in SiC substrate 10.

  Body region 13 forms part of sidewall surface SW of trench TR, and is formed on the side opposite to SiC substrate 10 as viewed from drift region 12. Body region 13 is formed to be in contact with drift region 12, source region 14 and contact region 15, and has channel region CH on the side wall surface SW side. Body region 13 has a p-type conductivity by including a p-type impurity such as Al (aluminum) or B (boron).

  Source region 14 includes main surface 11A, and is formed to constitute a part of side wall surface SW of trench TR. Source region 14 is formed in contact with body region 13 and contact region 15. Source region 14 has an n-type conductivity by including an n-type impurity such as P (phosphorus). The n-type impurity concentration in the source region 14 is higher than the n-type impurity concentration in the drift region 12.

  Contact region 15 includes main surface 11 </ b> A and is formed in contact with body region 13 and source region 14. Contact region 15 has a p-type conductivity by including a p-type impurity such as Al (aluminum) or B (boron). The p-type impurity concentration in contact region 15 is higher than the p-type impurity concentration in body region 13.

  Next, the structure of the insulating film 20 will be described with reference to FIGS. FIG. 2 is an enlarged view of a region surrounded by a broken-line square shown in FIG. Referring to FIGS. 1 and 2, insulating film 20 is formed to extend from the inside of trench TR to main surface 11A. More specifically, the insulating film 20 is formed so as to extend from the bottom surface BW of the trench TR to the upper end portion UT of the trench TR along the side wall surface SW and then to reach the main surface 11A. After extending to the boundary between the source region 14 and the body region 13 on the SW, the thickness is increased before reaching the upper end portion UT of the trench TR.

The insulating film 20 includes a gate oxide film 22 (lower insulating film) and a protective insulating film 21 (upper insulating film). Gate oxide film 22 is formed on a part of main surface 11A of SiC layer 11 and on side wall surface SW and bottom surface BW of trench TR. Gate oxide film 22 is formed by thermally oxidizing the surface layer portion of SiC layer 11 and is made of silicon dioxide (SiO ₂ ). Protective insulating film 21 is formed on gate oxide film 22 so as to cover gate oxide film 22 and upper end portion UT of trench TR and part of main surface 11A. The protective insulating film 21 is formed, for example, by a vapor deposition method such as a CVD (Chemical Vapor Deposition) method, and includes aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), and silicon nitride. It is made of one material selected from the group consisting of (SiN). Insulating film 20 includes a region composed of a multilayer film of gate oxide film 22 and protective insulating film 21 on the main surface 11A side from the boundary portion between source region 14 and body region 13, and bottom surface BW from the boundary portion. On the side, it is composed of a single layer film of the gate oxide film 22. With the above configuration, the insulating film 20 extends from the bottom surface BW of the trench TR to the boundary between the source region 14 and the body region 13 along the side wall surface SW, and then increases in thickness before reaching the upper end portion UT. It is formed so as to reach the main surface 11A. Note that the insulating film 20 is not limited to the one including the region formed of the multilayer film as described above, and the whole may be a single layer film.

  Referring to FIG. 2, upper end thickness T2 of insulating film 20 that is the shortest distance from upper end UT of trench TR to the surface of insulating film 20 (thickness in the direction along main surface 11A from upper end UT of trench TR). T2) is larger than the thickness T1 on the channel region CH. The upper end thickness T2 of the insulating film 20 is 75 nm or more, preferably 80 nm or more. The thickness T1 of the insulating film 20 is, for example, 50 nm. The upper end thickness T2 of the insulating film 20 is 1.5 times or more, preferably 1.6 times or more of the thickness T1. The thickness T3 of the insulating film 20 on the main surface 11A is larger than the upper end thickness T2.

  Referring to FIG. 1, gate electrode 30 is formed in contact with insulating film 20 (on gate oxide film 22 and protective insulating film 21). The gate electrode 30 is made of a conductor such as polysilicon (p-Si) or molybdenum (Mo) to which impurities are added, and is formed in the trench TR.

The interlayer insulating film 50 is formed so as to surround the gate electrode 30 together with the insulating film 20 (the gate oxide film 22 and the protective insulating film 21). The gate electrode 30 is electrically connected to the source electrode 40 and the source wiring 60. Insulated. Interlayer insulating film 50 is made of, for example, silicon dioxide (SiO ₂ ).

Source electrode 40 is formed in contact with main surface 11A (on source region 14 and contact region 15). The source electrode 40 is made of a material capable of making ohmic contact with the source region 14, for example, Ni _x Si _y (nickel silicide), Ti _x Si _y (titanium silicide), Al _x Si _y (aluminum silicide), and Ti _x Al. _{It is made of y} Si _z (titanium aluminum silicide) or the like and is electrically connected to the source region 14 (x, y, z> 0).

  Drain electrode 70 is formed on main surface 10 </ b> B of SiC substrate 10. Drain electrode 70 is made of a material that can make ohmic contact with SiC substrate 10, for example, the same material as source electrode 40, and is electrically connected to SiC substrate 10.

  The source wiring 60 is formed in contact with the source electrode 40. The source wiring 60 is made of a conductor such as aluminum (Al) and is electrically connected to the source region 14 via the source electrode 40.

  Next, the operation of MOSFET 1 will be described. Referring to FIG. 1, in a state where the voltage applied to gate electrode 30 is less than the threshold voltage, that is, in the off state, even if a voltage is applied between source electrode 40 and drain electrode 70, body region 13 drifts. The pn junction formed with the region 12 is reverse-biased and becomes non-conductive. On the other hand, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 30, carriers accumulate in the channel region CH and an inversion layer is formed. As a result, the source region 14 and the drift region 12 are electrically connected, and a current flows between the source electrode 40 and the drain electrode 70. As described above, the MOSFET 1 operates.

  As described above, in MOSFET 1 according to the present embodiment, upper end thickness T2 of insulating film 20 (thickness T2 of insulating film 20 in the direction along main surface 11A from upper end UT of trench TR) is above channel region CH. The thickness of the insulating film 20 is larger than the thickness T1. As a result, the upper end portion UT of the trench TR where electric field concentration is likely to occur can be covered with the insulating film 20 having a sufficient thickness while maintaining the thickness of the insulating film 20 on the channel region CH. Therefore, according to the MOSFET 1, the breakdown voltage characteristic can be further improved.

  Next, a method for manufacturing the silicon carbide semiconductor device according to this embodiment will be described. In the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, MOSFET 1 that is the silicon carbide semiconductor device according to the present embodiment is manufactured. Referring to FIG. 3, a silicon carbide substrate preparation step is first performed as a step (S10). In this step (S10), referring to FIG. 4, SiC substrate 10 is prepared by cutting an ingot (not shown) made of, for example, 4H—SiC and performing a polishing process or the like.

  Next, an epitaxial growth step is performed as a step (S20). In this step (S20), referring to FIG. 4, SiC layer 11 is formed on main surface 10A of SiC substrate 10 by epitaxial growth. The thickness of SiC layer 11 is 11 μm, for example.

  Next, an ion implantation step is performed as a step (S30). In this step (S30), referring to FIG. 5, for example, aluminum (Al) ions are implanted into SiC layer 11 from the main surface 11A side, so that the conductivity type is p-type in SiC layer 11. Body region 13 is formed. The thickness of body region 13 (the aluminum ion implantation depth) is, for example, not less than 0.7 μm and not more than 0.8 μm. Next, for example, phosphorus (P) ions are implanted into the body region 13 at a depth shallower than that of the aluminum ions, so that the source region 14 of n type conductivity is formed in the body region 13. . Next, for example, aluminum (Al) ions are implanted into the source region 14 at a depth equivalent to that of the phosphorus ions, thereby forming a contact region 15 having a p-type conductivity in the source region 14. A region where none of body region 13, source region 14, and contact region 15 is formed in SiC layer 11 becomes drift region 12. Moreover, the introduced impurity is activated by heating SiC substrate 10 after the completion of the ion implantation.

Next, a trench formation step is performed as a step (S40). In this step (S40), referring to FIG. 6, first, a mask (not shown) made of silicon dioxide (SiO ₂ ) having an opening on main surface 11A of SiC layer 11 is formed. Then, dry etching such as RIE (Reactive Ion Etching) using the mask, thermal etching using a halogen-based gas such as chlorine (Cl ₂ ), or etching combining them is performed. Thereby, trench TR having an opening on the main surface 11A side, an obtuse angle with respect to main surface 11A, and having side wall surface SW and bottom surface BW including channel region CH is formed in SiC layer 11. The thickness (channel length) along the sidewall surface SW of the channel region CH is, for example, not less than 0.5 μm and not more than 0.6 μm. Moreover, the depth of trench TR (distance between main surface 11A and bottom surface BW in the thickness direction of SiC layer 11) is, for example, not less than 1.0 μm and not more than 1.8 μm.

Next, a protective insulating film forming step is performed as a step (S50). In this step (S50), referring to FIG. 7, first, silicon dioxide (SiO ₂ ) is formed on SiC layer 11 (on main surface 11A and side wall surface SW and bottom surface BW) by a vapor deposition method such as a CVD method. A protective insulating film 21 (upper insulating film) is formed.

  Next, referring to FIG. 8, a resist film 80 patterned by photolithography is formed on protective insulating film 21. Next, a region mainly located in the trench TR of the protective insulating film 21 is etched. Thereby, a part of the protective insulating film 21 is removed while leaving a region covering the upper end portion UT of the trench TR. Thereafter, the resist film 80 is removed (FIG. 9). In this manner, the protective insulating film 21 extending from the sidewall surface SW of the trench TR to the main surface 11A and covering the upper end portion UT of the trench TR is formed.

Next, a gate oxide film forming step is performed as a step (S60). In this step (S60), referring to FIG. 10, SiC substrate 10 on which protective insulating film 21 is formed is heated, for example, in an atmosphere containing oxygen (O ₂ ). Thereby, the surface layer portion of SiC layer 11 is thermally oxidized, and gate oxide film 22 (lower insulating film) is formed on main surface 11A of SiC layer 11 and side wall surface SW and bottom surface BW of trench TR. The gate oxide film 22 is formed so as to be located below the protective insulating film 21 and constitutes the insulating film 20 together with the protective insulating film 21.

  By performing the step (S50) and the step (S60), the insulating film 20 is formed which includes the protective insulating film 21 and the gate oxide film 22 and extends from the inside of the trench TR to the main surface 11A. The insulating film 20 has an upper end thickness T2 (thickness T2 in the direction along the main surface 11A from the upper end UT of the trench TR) that is the shortest distance from the upper end UT of the trench TR to the surface of the insulating film 20. It is formed to be larger than the thickness T1 on CH (FIG. 2).

  Next, a gate electrode forming step is performed as a step (S70). In this step (S70), referring to FIG. 11, gate electrode 30 is formed in contact with insulating film 20 (protective insulating film 21 and gate oxide film 22) by, for example, LP (Low Pressure) -CVD. The

Next, an interlayer insulating film forming step is performed as a step (S80). In this step (S80), referring to FIG. 11, interlayer insulating film 50 made of silicon dioxide (SiO ₂ ) is formed to cover gate electrode 30 and insulating film 20, for example, by P (Plasma) -CVD. .

  Next, an ohmic electrode forming step is performed as a step (S90). In this step (S90), referring to FIG. 12, first, interlayer insulating film 50 and insulating film 20 (protective insulating film 21 and gate oxide film 22) are removed in the region where source electrode 40 is to be formed, and source region 14 A region where the contact region 15 is exposed is formed. Then, a metal film made of nickel (Ni), for example, is formed in the region. On the other hand, a metal film made of, for example, Ni is formed on main surface 10B of SiC substrate 10. Then, by heating SiC substrate 10 and siliciding at least a part of the metal film, source electrode 40 and drain electrode 70 are formed.

  Next, a source wiring formation step is performed as a step (S100). In this step (S100), referring to FIG. 1, source wiring 60 made of a conductor such as aluminum (Al) is formed on source electrode 40 by, for example, vapor deposition. The MOSFET 1 is manufactured by performing the steps (S10) to (S100), and the method for manufacturing the silicon carbide semiconductor device according to the present embodiment is completed.

  As described above, in the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, the upper end thickness T2 of the insulating film 20 which is the shortest distance from the upper end UT of the trench TR to the surface of the insulating film 20 is the channel region CH. The insulating film 20 is formed so as to be larger than the thickness T1 of the upper insulating film 20. As a result, the upper end portion UT of the trench TR where electric field concentration is likely to occur can be covered with the insulating film 20 having a sufficient thickness while maintaining the thickness of the insulating film 20 on the channel region CH. Therefore, according to the method for manufacturing the silicon carbide semiconductor device, MOSFET 1 with improved breakdown voltage characteristics can be manufactured.

  In the method for manufacturing the silicon carbide semiconductor device, after the protective insulating film 21 covering the upper end portion UT of the trench TR is formed by the vapor deposition method in the step (S50), the protective insulating film 21 together with the protective insulating film 21 is formed in the step (S60). A gate oxide film 22 constituting the insulating film 20 is formed by thermal oxidation. As a result, the thickness of the gate oxide film 22 can be controlled more precisely than when the protective insulating film 21 is formed after the gate oxide film 22 is formed.

(Embodiment 2)
Next, a second embodiment which is another embodiment of the present invention will be described. The method for manufacturing the silicon carbide semiconductor device according to the present embodiment is basically performed in the same manner as in the first embodiment and has the same effects. However, the method for manufacturing the silicon carbide semiconductor device according to the present embodiment differs from that in Embodiment 1 in the step of forming the insulating film.

  Referring to FIG. 13, first, steps (S110) to (S140) are performed similarly to steps (S10) to (S40) (FIG. 3) in the first embodiment. Thereby, as shown in FIG. 6, SiC layer 11 is formed on main surface 10A, and SiC substrate 10 in which trench TR is formed in SiC layer 11 is obtained.

Next, a gate oxide film forming step is performed as a step (S150). In this step (S150), referring to FIG. 14, SiC substrate 10 is heated in an atmosphere containing, for example, oxygen (O ₂ ). Thereby, as shown in FIG. 14, gate oxide film 22 made of silicon dioxide (SiO ₂ ) is formed so as to cover main surface 11A of SiC layer 11 and sidewall surface SW and bottom surface BW of trench TR.

Next, a protective insulating film forming step is performed as a step (S160). In this step (S160), referring to FIG. 15, first, protective insulating film 21 made of silicon dioxide (SiO ₂ ) is formed on gate oxide film 22 by a vapor deposition method such as a CVD method. Next, referring to FIG. 16, a resist film (not shown) patterned by photolithography is formed on protective insulating film 21, and then protective insulating film 21 is partially etched. As a result, as in the case of the step (S50) of the first embodiment, the portion mainly covering the trench TR is removed while the portion covering the upper end portion UT of the trench TR of the protective insulating film 21 remains. Then, after the etching of the protective insulating film 21 is completed, the resist film is removed. Thus, the insulating film 20 composed of the protective insulating film 21 and the gate oxide film 22 is formed.

  Next, steps (S170) to (S200) are performed in the same manner as steps (S70) to (S100) (FIG. 3) in the case of the first embodiment. Thereby, MOSFET 1 shown in FIG. 1 is manufactured, and the method for manufacturing the silicon carbide semiconductor device according to the present embodiment is completed.

  As described above, in the method for manufacturing the silicon carbide semiconductor device according to the present embodiment, after the gate oxide film 22 covering the sidewall surface SW of the trench TR is formed by thermal oxidation in the step (S150), the upper end portion of the trench TR. A protective insulating film 21 covering the UT is formed by vapor deposition. Thereby, it is possible to prevent the interface between the sidewall surface SW of the trench TR and the gate oxide film 22 from being damaged when the protective insulating film 21 is etched.

In the present embodiment, the case where the protective insulating film 21 is made of silicon dioxide (SiO ₂ ) as in the case of the gate oxide film 22 has been described, but the present invention is not limited to this. The protective insulating film 21 may be made of, for example, aluminum nitride (AlN), aluminum oxide (Al ₂ O ₃ ), silicon dioxide (SiO ₂ ), silicon nitride (SiN), or the like. When the protective insulating film 21 is made of a material different from that of the gate oxide film 22 as described above, the gate oxide film 22 can function to stop etching when the protective insulating film 21 is etched.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  INDUSTRIAL APPLICABILITY The silicon carbide semiconductor device and the manufacturing method thereof according to the present invention can be particularly advantageously applied to a silicon carbide semiconductor device and a manufacturing method thereof that require improvement in breakdown voltage characteristics.

1 MOSFET
DESCRIPTION OF SYMBOLS 10 Silicon carbide (SiC) substrate 10A, 10B, 11A Main surface 11 Silicon carbide (SiC) layer 12 Drift region 13 Body region 14 Source region 15 Contact region 20 Insulating film 21 Protective insulating film 22 Gate oxide film 30 Gate electrode 40 Source electrode 50 Interlayer insulating film 60 Source wiring 70 Drain electrode 80 Resist film TR Trench UT Upper end portion CH Channel region SW Side wall surface BW Bottom surface T1, T3 thickness T2 Upper end thickness

Claims (11)

A silicon carbide layer in which a trench having a wall surface that opens on one main surface side and forms an obtuse angle with respect to the one main surface;
An insulating film extending from the inside of the trench to the one main surface,
The wall includes a channel region;
The silicon carbide semiconductor device, wherein the thickness of the upper end portion of the insulating film, which is the shortest distance from the upper end portion of the trench to the surface of the insulating film, is larger than the thickness of the insulating film on the channel region. The silicon carbide layer is
A source region including the one main surface and constituting a part of the wall surface;
A body region that contacts the source region and constitutes part of the wall surface and has the channel region;
The insulating film is formed so as to increase in thickness before reaching the upper end after extending from the bottom of the trench to the boundary between the source region and the body region along the wall surface. The silicon carbide semiconductor device according to claim 1.   The silicon carbide semiconductor device according to claim 2, wherein said insulating film is formed of a multilayer film on the one main surface side with respect to said boundary portion. The multilayer film is
A lower insulating film formed on the silicon carbide layer and made of silicon dioxide;
4. The silicon carbide semiconductor according to claim 3, comprising an upper insulating film formed of one material selected from the group consisting of aluminum nitride, aluminum oxide, silicon dioxide, and silicon nitride, and formed on the lower insulating film. apparatus.   5. The silicon carbide semiconductor device according to claim 1, wherein an upper end thickness of said insulating film is 1.5 times or more a thickness of said insulating film on said channel region.   The silicon carbide semiconductor device according to any one of claims 1 to 5, wherein an upper end thickness of the insulating film is 75 nm or more.   The thickness of the said insulating film on said one main surface is a silicon carbide semiconductor device of any one of Claims 1-6 larger than the upper end part thickness of the said insulating film.   8. The silicon carbide semiconductor device according to claim 1, wherein said wall surface has an off angle of not less than 50 ° and not more than 70 ° with respect to a {0001} plane of silicon carbide. Forming a silicon carbide layer including one main surface;
Forming a trench in the silicon carbide layer that is open on the one main surface side and has an obtuse angle with respect to the one main surface and having a wall surface including a channel region;
Forming an insulating film extending from the inside of the trench to the one main surface,
In the step of forming the insulating film, the thickness of the upper end portion of the insulating film, which is the shortest distance from the upper end portion of the trench to the surface of the insulating film, is larger than the thickness of the insulating film on the channel region. A method for manufacturing a silicon carbide semiconductor device, wherein the insulating film is formed on The step of forming the insulating film includes
Forming an upper insulating film covering the upper end portion by vapor deposition;
The method comprising: forming the insulating film together with the upper insulating film after the upper insulating film is formed, and forming a lower insulating film covering the upper end portion and the wall surface by thermal oxidation. A method for manufacturing a silicon carbide semiconductor device. The step of forming the insulating film includes
Forming a lower insulating film covering the upper end portion and the wall surface by thermal oxidation;
The carbonization according to claim 9, further comprising: forming the insulating film together with the lower insulating film after forming the lower insulating film, and forming an upper insulating film covering the upper end portion by vapor deposition. A method for manufacturing a silicon semiconductor device.

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