JP2008034581A - Submount - Google Patents

Abstract

Provided is a submount that reduces a thermal load on an optical semiconductor element and has a low possibility of causing a positional shift in the optical semiconductor element due to melting of a brazing material of the submount during solder mounting.
An insulating substrate is made of Au, Ag, Al, or Cu, and a main conductor layer formed on the insulating substrate is made of Pd, Ni, Pt, Ru, W, Mo, or TiW. The barrier layer 13 formed on the surface of the body layer 12, the first Au—Sn alloy layer 14 formed on the barrier layer 13, and the Ni layer formed on the surface of the first Au—Sn alloy layer 14 15.
[Selection] Figure 1

Description

  The present invention relates to a submount on which a semiconductor laser and a light emitting diode are mounted.

Generally, an optical semiconductor element (semiconductor laser, light emitting diode, etc.) is mounted on a package made of metal or the like via a submount made of aluminum nitride or the like. The submount is usually formed with a brazing material for mounting the optical semiconductor element. As this brazing material, an AuSn eutectic brazing material (composition ratio Au: Sn = 80: 20 theoretical melting point 278 ° C.) usually made of Au and Sn is used. The However, since the thermal load on the optical semiconductor element damages the characteristics of the optical semiconductor element and hinders long-term reliability, a brazing material that can lower the assembly temperature is required. In order to overcome this problem, for example, there are brazing materials described in Patent Documents 1 to 3 below.
JP 2002-252316 A JP 2002-368020 A JP-T-2005-109484

  According to the submount as described in Patent Document 1, since the brazing material in which the weight percentage ratio of Au to Sn is Au: Sn = 5: 95 to 15:85 is formed, the melting temperature is When the packaged optical semiconductor device is solder-mounted on a printed circuit board or the like (at the time of so-called secondary mounting), the submount brazing material is also melted, and the optical semiconductor element may be displaced. There was a problem of having sex. This is a problem caused by the fact that the solder mounting temperature has risen to about 220 ° C. since it is mounted using a Pb-free solder material in recent years.

  On the other hand, Patent Document 2 and Patent Document 3 propose a brazing material containing Ag. However, Ag is likely to cause migration, and is known to grow a needle-like structure called a whisker. This whisker has a problem that an optical semiconductor device may be short-circuited.

  The present invention has been devised in view of the problems of the prior art, and its purpose is to reduce the thermal load on the optical semiconductor element and to melt the brazing material of the submount during solder mounting into the optical semiconductor element. It is an object of the present invention to provide a submount that is unlikely to cause misalignment.

  The present invention comprises an insulating substrate, Au, Ag, Al or Cu, a main conductor layer formed on the insulating substrate, Pd, Ni, Pt, Ru, W, Mo or TiW, and the main conductor A barrier layer formed on the surface of the layer; a first Au—Sn alloy layer formed on the barrier layer; and a Ni layer formed on the surface of the first Au—Sn alloy layer. Yes.

  The present invention includes a first Au—Sn alloy layer formed on the barrier layer and a Ni layer formed on the surface of the first Au—Sn alloy layer, thereby providing heat to the optical semiconductor element. The load can be reduced, and the possibility that the optical semiconductor element is displaced due to the heat treatment when mounted on a printed circuit board or the like can be reduced.

  The submount of the present invention will be described in detail with reference to the drawings.

  (First Embodiment) FIG. 1 is a cross-sectional view showing the structure of a submount according to the first embodiment of the present invention. The submount of the present invention includes an insulating substrate 11, a main conductor layer 12 formed on the insulating substrate 11, a barrier layer 13 formed on the surface of the main conductor layer 12, and an Au formed on the barrier layer 13. A Sn alloy layer (first Au—Sn alloy layer) 14 and a Ni layer 15 formed on the surface of the Au—Sn alloy layer are provided.

  The insulating substrate 11 is made of an aluminum nitride sintered body, a silicon carbide sintered body, diamond or silicon. Other examples of the material of the insulating substrate 11 include an aluminum oxide sintered body, a glass ceramic sintered body, a silicon nitride sintered body, quartz, sapphire, or cubic boron nitride. In order to efficiently conduct the heat generated when the optical semiconductor element (light emitting diode; LED, laser diode; LD) mounted on the submount of the present invention is driven, the thermal conductivity is 40 W / m · K or more. Therefore, the insulating base 11 is preferably made of an aluminum nitride sintered body, a silicon carbide sintered body, diamond or silicon.

In the submount of the present embodiment, an adhesion metal layer 16 is formed on the surface of the insulating substrate 11. Here, in the submount of the present embodiment, the adhesion metal layer is a layer provided to improve the bonding strength of the metal layer (and the metal layer formed on the upper layer) to the insulating substrate 11. That means. In the present embodiment, the adhesion metal layer 15 is made of Ti, Cr, Ta, Nb, Ni—Cr alloy or Ta ₂ N. In the submount shown in FIG. 1, the adhesion metal layer 15 is desirably formed with a thickness of 0.01 μm to 0.2 μm from the viewpoint of improving the bonding strength and reducing the peeling. If the thickness of the adhesion metal layer 15 is less than 0.01 μm, it tends to be difficult to firmly bond, and if the thickness exceeds 0.2 μm, peeling tends to occur due to internal stress during film formation. is there.

  In the submount of the present embodiment, a barrier layer 16 is formed on the surface of the adhesion metal layer 15. Here, in the submount of the present embodiment, the barrier layer refers to a layer provided so that no diffusion occurs between the upper and lower layers by heat treatment or the like. In the present embodiment, the barrier layer 16 is made of Pt, Pd, Rh, Ru, Ni, Ni—Cr alloy or Ti—W alloy. In the submount shown in FIG. 1, the barrier layer 16 is preferably formed with a thickness of 0.05 to 1 μm from the viewpoint of the function of preventing diffusion and the reduction of peeling. When the thickness is less than 0.05 μm, the barrier layer 16 tends to hardly function as a diffusion preventing layer due to defects such as pinholes. When the thickness exceeds 1 μm, peeling is likely to occur due to internal stress during film formation. Tend to be.

  In the submount of the present embodiment, the main conductor layer 12 is formed on the surface of the barrier layer 16. The main conductor layer 4 is made of Au, Ag, Cu, or Al, and is preferably formed with a thickness of 0.1 μm to 5 μm from the viewpoint of reducing resistance and reducing peeling.

  In the submount of the present invention, a barrier layer 13 is formed on the surface of the main conductor layer 12. Here, the barrier layer 13 is a layer that prevents Sn contained in the Au—Sn alloy layer formed in the upper layer from being diffused into the main conductor layer 12 by heat treatment. That means. In the submount of the present invention, the barrier layer 13 is made of Pt, Pd, Rh, Ru, Ni, Ni—Cr alloy or Ti—W alloy. The barrier layer 13 is desirably formed with a thickness of 0.01 μm to 1 μm from the viewpoint of the function of preventing diffusion and the reduction of peeling. When the barrier layer 13 has a thickness of less than 0.01 μm, it may not be possible to prevent Sn contained in the Au—Sn alloy layer 14 formed in the upper layer from diffusing into the main conductor layer 12. When the thickness exceeds 1 μm, peeling tends to occur due to internal stress during film formation.

  In the submount of the present invention, an Au—Sn alloy layer 14 is formed on the surface of the barrier layer 13. The Au—Sn alloy layer 13 is made of Pt, Pd, Rh, Ru, Ni, Ni—Cr alloy or Ti—W alloy. The Au—Sn alloy layer 13 is composed of 60 to 80 wt% Au and 40 to 20 wt% Sn. When Au is less than 60 wt% or exceeds 80 wt%, the melting temperature of the Au—Sn alloy rises, and there is a tendency that the lowering of the melting temperature of the brazing material, which is the object of the present invention, cannot be achieved.

  In the submount of the present invention, a Ni layer 15 is formed on the surface of the barrier layer 13. In a composition ratio with the lower Au—Sn alloy layer 14, it is desirable that Ni is set to a thickness of 2 wt% to 5 wt%. When Ni is less than 2% or exceeds 5%, the melting temperature of the alloy composed of the Au—Sn alloy layer 14 and the Ni layer 15 rises, and the melting temperature of the brazing material layer which is the object of the present invention is reduced. There is a tendency that low temperatures cannot be achieved.

  The submount of the present invention includes an Au—Sn alloy layer 14 formed on the barrier layer 13 and an Ni layer 15 formed on the surface of the Au—Sn alloy layer 14. When the heat treatment for mounting is performed, a ternary brazing material layer is formed by the Au—Sn alloy layer 14 and the Ni layer 15, and the temperature is lower than that in the case of using an AuSn eutectic brazing material (for example, The thermal load on the optical semiconductor element can be reduced, and the possibility of misalignment in the optical semiconductor element due to heat treatment when mounted on a printed circuit board is reduced. be able to.

  (Second Embodiment) A submount according to a second embodiment of the present invention will be described with reference to FIG. FIG. 2 is a cross-sectional view showing the configuration of the submount according to the second embodiment of the present invention. The submount of the present embodiment is the same as the submount of the first embodiment shown in FIG. 1 except for the Au—Sn alloy layer (second Au—Sn alloy layer) 24 formed on the surface of the Ni layer 15. Is further provided. That is, in the submount of the present embodiment, the Ni layer 15 is sandwiched between the first Au—Sn alloy layer 14 and the second Au—Sn alloy layer 24.

  In the submount of the present embodiment, the second Au—Sn alloy layer is made of Pt, Pd, Rh, Ru, Ni, Ni—Cr alloy or Ti—W alloy. The second Au—Sn alloy layer 24 is composed of 60 to 80 wt% Au and 40 to 20 wt% Sn. When Au is less than 60 wt% or exceeds 80 wt%, the melting temperature of the Au—Sn alloy rises, and there is a tendency that the lowering of the melting temperature of the brazing material, which is the object of the present invention, cannot be achieved.

  The submount of the present embodiment further includes the second Au—Sn alloy layer 24 formed on the surface of the Ni layer 15, so that mutual diffusion between the Au—Sn alloy and Ni is likely to occur. The thermal load on the optical semiconductor element can be further reduced, and the possibility that the optical semiconductor element is displaced due to the heat treatment when mounted on a printed board or the like can be further reduced.

It is sectional drawing which shows the structure of the submount of the 1st Embodiment of this invention. It is sectional drawing which shows the structure of the submount of the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Insulating base | substrate 12 ... Main conductor layers 13, 17 ... Barrier layer 14 ... 1st Au-Sn alloy layer 15 ... Ni layer 16 ... Adhesion metal layer

Claims (4)

An insulating substrate;
A main conductor layer made of Au, Ag, Al or Cu and formed on the insulating substrate;
A barrier layer made of Pd, Ni, Pt, Ru, W, Mo or TiW, and formed on the surface of the main conductor layer;
A first Au-Sn alloy layer formed on the barrier layer;
And a Ni layer formed on the surface of the first Au—Sn alloy layer. The substrate according to claim 1, wherein the first Au—Sn alloy layer is made of 60 to 80 wt% Au and 40 to 20 wt% Sn. The substrate according to claim 1, further comprising a second Au—Sn alloy layer formed on a surface of the Ni layer. The substrate according to claim 3, wherein the second Au—Sn alloy layer is made of 60 to 80 wt% Au and 40 to 20 wt% Sn.

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