JP2013168464A - Semiconductor light-emitting element and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element in which peeling of a metal layer is reduced.SOLUTION: A semiconductor light-emitting element 1 comprises: a substrate 2; a semiconductor element structure 3 stacked on a first principal surface of the substrate 2; and a metal layer 4 stacked on a second principal surface of the substrate 2 on the opposite side to the first principal surface. The metal layer 4 includes a first metal layer 5 for bonding the semiconductor light-emitting element 1 to an external component. The first metal layer 5 includes a plurality of AuSn layers 7 provided in a thickness direction, and an intermediate layer 8 which is provided in contact with the AuSn layer 7 and composed of a metallic material harder than AuSn.

Description

  The present invention relates to a semiconductor light emitting device including a metal layer on the back surface of a substrate and a method for manufacturing the same.

  2. Description of the Related Art Conventionally, a structure having an electrode for attaching a wire on the light emitting surface side, that is, a face-up type semiconductor light emitting device, including a substrate and a light emitting layer laminated on the first main surface of the substrate And a metal layer laminated on the second main surface side (back side) of the substrate has been proposed (see, for example, Patent Document 1).

  The outline of the manufacturing method of the semiconductor light emitting device described in Patent Document 1 is as follows. As the wafer substrate, for example, a semiconductor element structure made of a GaN layer or an InGaN layer is stacked on the first main surface of a 2-inch φ sapphire substrate. Next, an Ag film, a Ni film, and an Rh film are stacked on the back side of the sapphire substrate in order from the substrate side. Further, an Au—Sn eutectic alloy film is formed as a bonding layer on the Rh film. And it divides | segments into a semiconductor light emitting element unit. Each semiconductor light-emitting element is bonded to an external member (package or mounting substrate) through a bonding layer by thermocompression bonding or the like, and then the p-side electrode and the n-side electrode are connected to the lead of the light-emitting device. Each is connected to an electrode.

Patent Document 2 describes a multilayer film in which Au and Sn are alternately stacked as a bonding layer formed on substantially the entire back surface of a wafer substrate in a manufacturing process of a semiconductor light emitting device.
Patent Document 3 describes a eutectic material such as AuSn as a bonding layer of a semiconductor light-emitting device having a so-called junction-down structure.
Patent Document 4 describes a laminate composed of a large number of tin layers and gold layers as a solder layer of a semiconductor chip. This laminate fuses into an AuSn alloy during the soldering process.

JP 2008-153362 A JP 2008-060167 A JP 2007-317771 A JP 2006-287226 A

  However, as in the prior art, when a wafer having a metal layer on the entire back surface of the substrate is divided into semiconductor elements, the metal layer may be peeled off. In particular, in the case of a small die size (for example, in the case of 500 μm × 290 μm or less, etc.), the metal layer is easily peeled off.

  This invention is made | formed in view of the problem mentioned above, and makes it a subject to provide the semiconductor light-emitting device which reduced peeling of the metal layer, and its manufacturing method.

  In order to solve the above problems, a semiconductor light emitting device according to the present invention includes a substrate, a semiconductor element structure stacked on the first main surface of the substrate, and a side opposite to the first main surface of the substrate. A metal layer laminated on the second main surface, wherein the metal layer comprises a first metal layer for joining the semiconductor light emitting device to an external member, The first metal layer includes a plurality of AuSn layers provided in a thickness direction, and an intermediate layer provided in contact with the AuSn layer and made of a metal material harder than AuSn.

According to such a configuration, since the semiconductor light emitting device includes the intermediate layer made of a material harder than AuSn between the AuSn layers, the semiconductor light emitting device emits light compared with the case where the metal layer is composed only of soft AuSn. The element can be easily cleaved. Therefore, the semiconductor light emitting device can reduce peeling of the metal layer from the substrate.
According to such a configuration, the semiconductor light emitting device includes the plurality of AuSn layers and the intermediate layer as the first metal layer. Here, when the total thickness of the plurality of AuSn layers in the present invention is set to a thickness similar to the thickness of a metal layer made of one AuSn layer in a conventional semiconductor light emitting device, for example, the thickness of each AuSn layer Is thinner than the conventional one and the intermediate layer provided in contact with the AuSn layer supports the AuSn layer thinner than the conventional one, so that peeling of the metal layer from the substrate can be reduced.

In the semiconductor light emitting device according to the present invention, the first metal layer is preferably configured by alternately stacking the AuSn layer and the intermediate layer.
In the semiconductor light emitting device according to the present invention, the intermediate layer is made of a metal material mainly composed of at least one selected from Ag, Ni, Rh, Al, W, Pt, Ti, Ru, Mo, and Nb. It is preferable.

  In the semiconductor light emitting device according to the present invention, the intermediate layer preferably has a thickness of less than 0.1 μm. According to such a configuration, in the semiconductor light emitting device, since the intermediate layer constituting the first metal layer is thin, peeling of the metal layer from the substrate can be effectively reduced, and the semiconductor light emitting device can be easily cleaved. Can do. In addition, since the AuSn layer can be sufficiently heated and melted by reducing the thickness of the intermediate layer, mounting is facilitated.

  In the semiconductor light emitting device according to the present invention, the total thickness of the AuSn layers is preferably 2.8 to 4.2 μm. According to this configuration, the total value of the film thickness of the AuSn layer is in an appropriate range, and the semiconductor light emitting device can be easily mounted.

  In addition, the semiconductor light emitting device according to the present invention includes a layer having a higher reflectance with respect to light from the semiconductor device structure than the AuSn layer, between the second main surface of the substrate and the first metal layer. It is preferable to provide a second metal layer. According to this configuration, the semiconductor light emitting element can reflect the light emitted from the semiconductor element structure to the second main surface side of the substrate by the second metal layer. Therefore, the semiconductor light emitting device can improve the light extraction efficiency to the first main surface side of the substrate. In addition, when the semiconductor light emitting element is bonded to an external member via the first metal layer by thermocompression bonding or the like, the intermediate layer supports the AuSn layer, so that the AuSn layer is the second metal layer on the element substrate side. It effectively prevents you from getting around. Therefore, it is possible to reduce a decrease in brightness due to AuSn dissolved by heating eroding the second metal layer.

  In order to solve the above problems, a method for manufacturing a semiconductor light emitting device according to the present invention includes a first step of preparing a semiconductor multilayer structure formed on a first main surface of a substrate, and a first step of the substrate. On the second main surface opposite to the main surface, a plurality of AuSn layers provided in the thickness direction, and an intermediate layer provided between and in contact with the AuSn layer and made of a metal material harder than AuSn, A second step of forming a first metal layer, and a third step of dividing the semiconductor multilayer structure and the substrate on which the first metal layer is formed for each of the semiconductor light emitting elements. To do.

  According to such a procedure, the method for manufacturing a semiconductor light emitting device according to the present invention prepares a semiconductor multilayer structure formed on the first main surface of the substrate in the first step, and performs the substrate in the second step. A first metal layer is formed on the second main surface, and the substrate is divided into semiconductor light emitting elements in a third step. In the method for manufacturing a semiconductor light emitting device, in the second step, as the first metal layer, a plurality of AuSn layers and an intermediate layer in contact with the AuSn layers are stacked in the thickness direction. Here, as for the first metal layer, for example, an AuSn layer is laminated with a thinner film thickness than before, an intermediate layer is laminated on the thin AuSn layer so as to be in contact with the thin AuSn layer, and further, a thinner film thickness than before. The AuSn layer is laminated. That is, the first metal layer has a structure in which the intermediate layer is sandwiched between two thin AuSn layers. That is, the first metal layer of the semiconductor light emitting device according to the present invention can be realized by dividing the conventional process of forming one AuSn layer and adding a process of laminating an intermediate layer between the processes. Therefore, the cleaving property can be improved by a method that is easy to make in the process. Thereby, in a 3rd process, when dividing | segmenting a board | substrate for every semiconductor light-emitting element, it becomes easy to cleave. Therefore, when dividing in the third step, peeling of the metal layer from the substrate can be reduced.

  In the method for manufacturing a semiconductor light emitting element according to the present invention, it is preferable that the second step alternately stacks the AuSn layer and the intermediate layer.

  According to such a procedure, in the method for manufacturing a semiconductor light emitting device according to the present invention, in the first metal layer of the semiconductor light emitting device, the individual AuSn layers are laminated thinner than before, and the intermediate layers alternately with the AuSn layers are provided. Laminated. Here, the lamination may start from either the AuSn layer or the intermediate layer. Thereby, in a 3rd process, when dividing | segmenting a board | substrate for every semiconductor light-emitting element, it becomes easy to cleave. Therefore, peeling of the metal layer from the substrate can be reduced.

  In the method for manufacturing a semiconductor light emitting device according to the present invention, the second step mainly includes at least one selected from Ag, Ni, Rh, Al, W, Pt, Ti, Ru, Mo, and Nb. The intermediate layer is preferably formed of a metal material.

  Also, in the method for manufacturing a semiconductor light emitting device according to the present invention, the second metal layer having higher reflectivity with respect to light from the semiconductor device structure than the AuSn layer is provided between the first step and the second step. It is preferable to have the process of forming.

  According to this procedure, in the method for manufacturing a semiconductor light emitting device according to the present invention, the second metal layer for increasing the light reflectance is formed on the second main surface side of the substrate, and then the semiconductor light emitting device is externally mounted. A first metal layer for bonding to the member is formed. Thereby, the semiconductor light emitting element can improve the light extraction efficiency to the first main surface side of the substrate. In addition, when the semiconductor light emitting element is bonded to an external member via the first metal layer by thermocompression bonding or the like, the intermediate layer supports the AuSn layer, so that the AuSn layer is the second metal layer on the element substrate side. It effectively prevents you from getting around. Therefore, it is possible to reduce a decrease in brightness due to AuSn dissolved by heating eroding the second metal layer.

According to the semiconductor light emitting device of the present invention, it becomes easy to cleave and the peeling of the metal layer can be reduced.
According to the method for manufacturing a semiconductor light emitting device of the present invention, it is easy to cleave when dividing, so that peeling of the metal layer can be reduced. Therefore, the yield can be improved.

BRIEF DESCRIPTION OF THE DRAWINGS It is a schematic diagram of the semiconductor light-emitting device concerning embodiment of this invention, Comprising: (a) is a top view, (b) is sectional drawing in the AA arrow. It is a schematic diagram of the light emitting element of a comparative example, Comprising: (a) is a top view, (b) is sectional drawing in the BB arrow. It is sectional drawing which shows typically the manufacturing process of the semiconductor light-emitting device which concerns on embodiment of this invention. It is explanatory drawing of peeling of the metal layer in a light emitting element, Comprising: (a) is a top view, (b) is sectional drawing in CC arrow. (A) is a conceptual diagram schematically showing a wafer laminated with a single layer of AuSn, and (b) is a conceptual diagram schematically showing a wafer laminated with three layers of AuSn. It is sectional drawing which shows typically the test which heats each wafer of FIG. FIG. 5A is a conceptual diagram schematically showing the state after the wafer of FIG. 5A is heated, and FIG. 5B is a conceptual diagram schematically showing the state after the wafer of FIG. 5B is heated. Yes.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for implementing a semiconductor light emitting device according to the present invention will be described in detail with reference to drawings showing some specific examples. Note that the size, positional relationship, and the like of the members shown in each drawing may be exaggerated for clarity of explanation. Further, in the following description, the same name and reference sign indicate the same or the same members in principle, and the detailed description will be omitted as appropriate.

[1. Overview of semiconductor light emitting device configuration]
FIG. 1 shows a semiconductor light emitting device 1 according to an embodiment of the present invention. FIG. 2 shows a light emitting device 100 of a comparative example. An outline of the configuration of the semiconductor light emitting device 1 will be described with reference to FIGS. 1 and 2. As shown in FIGS. 1A and 1B, the semiconductor light emitting device 1 has a structure having a p-side electrode 32 and an n-side electrode 33 for attaching a wire (not shown) on the light emitting surface side, that is, face-up. Of structure. As illustrated, the semiconductor light emitting device 1 includes a substrate 2, a semiconductor element structure 3 stacked on the first main surface of the substrate 2, and a metal layer 4 stacked on the second main surface of the substrate 2. Is mainly provided. As shown in FIG. 1B, the metal layer 4 includes a first metal layer 5 and a second metal layer 6 for joining the semiconductor light emitting element 1 to an external member (not shown). The first metal layer 5 includes a plurality of AuSn layers 7 provided in the thickness direction and an intermediate layer 8 provided between the AuSn layers 7.

  On the other hand, as shown in FIGS. 2A and 2B, the light emitting device 100 of the comparative example is also of a face-up structure, and is laminated on the substrate 2 and the first main surface of the substrate 2. The semiconductor element structure 3 and the metal layer 4 laminated on the second main surface of the substrate 2 are provided. However, the metal layer 4 of the light emitting element 100 includes one AuSn layer 7 that is a first metal layer and a second metal layer 6 as shown in FIG.

Therefore, the semiconductor light emitting device 1 is different from the light emitting device 100 in the structure of the first metal layer.
In the semiconductor light emitting device 1, the intermediate layer 8 constituting the first metal layer 5 is a layer that is provided in contact with the AuSn layer 7 and made of a material harder than AuSn in Mohs hardness. An intermediate layer 8 is interposed between the two AuSn layers 7. Since the semiconductor light emitting element 1 includes the intermediate layer 8 harder than AuSn in the first metal layer 5, the cleaving property is improved as compared with the light emitting element 100. Therefore, the semiconductor light emitting element 1 can reduce peeling of the metal layer 4 from the substrate 2.

  In addition, since the required thickness of the bonding layer is approximately the same for light emitting elements of the same size, in this example, the semiconductor light emitting element 1 has the thickness of each AuSn layer 7 provided on the first metal layer 5. The film thickness is about 1/3 of the thickness of the AuSn layer 7 in the light emitting device 100 of the comparative example. In other words, the total film thickness of the AuSn layer 7 constituting the first metal layer 5 of the semiconductor light emitting element 1 is about the film thickness of the AuSn layer 7 in the light emitting element 100 of the comparative example. Therefore, in the first metal layer 5 of the semiconductor light emitting device 1, the individual AuSn layers 7 are thin and the intermediate layer 8 supports the thin AuSn layer 7, so that the metal layer 4 is peeled off from the substrate 2. It can reduce compared with. In addition, the experimental result compared with the light emitting element 100 about peeling of the metal layer 4 from the board | substrate 2 is mentioned later.

[2. Details of the structure of the semiconductor light emitting device]
Hereinafter, the configuration of the semiconductor light emitting device 1 according to the present embodiment will be described in detail.
(substrate)
As the substrate 2, for example, a known insulating substrate such as sapphire, spinel, SiC, NGO (NdGaO ₃ ) substrate, LiAlO ₂ substrate, LiGaO ₃ substrate, GaN, GaAs or the like can be used. Of these, a sapphire substrate is preferable.

(Semiconductor element structure)
The semiconductor element structure 3 is formed by laminating an n-side semiconductor layer 21, a light emitting layer 22, and a p-side semiconductor layer 23 in order from the substrate 2 side.
One or both of the n-side semiconductor layer 21 and the p-side semiconductor layer 23 may be composed of a plurality of nitride semiconductor layers. The light emitting layer 22 may be a single layer or a multilayer. Therefore, for example, each of the n-side semiconductor layer 21 and the p-side semiconductor layer 23 can be composed of a plurality of layers corresponding to necessary functions such as a contact layer and a clad layer, thereby realizing light emission characteristics according to applications. can do.

  Examples of the contact layer of the n-side semiconductor layer 21 include a Si-doped n-type GaN layer, and examples of the cladding layer of the n-side semiconductor layer 21 include a Si-doped n-type AlGaN layer. Examples of the contact layer of the p-side semiconductor layer 23 include an Mg-doped p-type GaN layer, and examples of the cladding layer of the p-side semiconductor layer 23 include an Mg-doped p-type AlGaN layer. The light emitting layer 22 includes an InGaN layer, a single or multiple quantum well layer of GaN and InGaN, a single or multiple quantum well layer composed of an InGaN barrier layer and an InGaN well layer having a different composition ratio. The n-side semiconductor layer 21 and the p-side semiconductor layer 23 may further include an undoped nitride semiconductor layer.

  On the semiconductor element structure 3, a transparent electrode layer 31, a p-side electrode 32, an n-side electrode 33, and a protective layer 34 are stacked.

<Transparent electrode layer>
The transparent electrode layer 31 is a first layer of the p-side electrode and functions as an ohmic electrode that is in direct contact with the p-side semiconductor layer 23. The transparent electrode layer 31 is a conductive layer that can transmit the light emitted from the semiconductor light emitting element 1, and is formed on almost the entire upper surface of the p-side semiconductor layer 23, and current flowing from the p-side electrode 32 is supplied to the p-side semiconductor layer. Spread evenly across 23. The material of the transparent electrode layer 31 is, for example, an oxide containing at least one element selected from the group consisting of zinc (Zn), indium (In), and tin (Sn). Specifically, mention may be made of ITO, ZnO, and In ₂ O _3, SnO ₂ or the like.

<P-side electrode>
The p-side electrode 32 functions as a pad electrode to which an external connection member such as a wire is bonded, and includes a pad portion 321 and an extended conductive portion 322.
The pad portion 321 has a substantially circular shape as shown in FIG. 1A and is a region to which an external connection member such as a wire is joined. When the external connection member is joined, the protective layer 34 laminated on the upper surface of the pad portion 321 is removed.

  As shown in FIG. 1A, the stretched conductive portion 322 is divided into two forks from the right end portion of the substantially circular pad portion 321 in the drawing, and each of them is parallel to the periphery of the semiconductor light emitting element 1 in the drawing. Stretched from left to right. Thereby, the current can be diffused in the in-plane direction.

  As a material of the p-side electrode 32, a material that can be normally used as an electrode can be used. For example, zinc (Zn), nickel (Ni), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), osmium (Os), iridium (Ir), titanium (Ti), zirconium (Zr) ), Hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), cobalt (Co), iron (Fe), manganese (Mn), molybdenum (Mo), chromium (Cr), tungsten (W ), Lanthanum (La), copper (Cu), silver (Ag), yttrium (Y) and other metals, and alloys such as Ni—Au and Ni—Pt.

<N-side electrode>
Similar to the p-side electrode 32, the n-side electrode 33 functions as a pad electrode to which an external connection member such as a wire is joined, and includes a pad portion 331 and an extended conductive portion 332.
The pad portion 331 is a substantially circular shape as shown in FIG. 1A, and is a region where wires are joined. When the external connection member is joined, the protective layer 34 laminated on the upper surface of the pad portion 331 is removed.

  As shown in FIG. 1A, the stretched conductive portion 332 is stretched from the left end portion of the substantially circular pad portion 331 to the left in the drawing. As shown in FIG. 1A, in a plan view, the pad portion 321 of the p-side electrode 32, the pad portion 331 of the n-side electrode 33, and the extended conductive portion 332 are arranged in a straight line. In addition, as shown in FIG. 1B, the p-side electrode 32 is provided above the n-side electrode 33 in a cross-sectional view. Thereby, the current can be diffused in the in-plane direction between the p-side electrode 32 and the n-side electrode 33.

  Examples of the material for the n-side electrode 33 include materials that can be used as electrodes. Further, for example, it may be composed of two metals laminated in the order of Ti / Al from the n-side semiconductor layer 21 side. Similarly, it may be composed of three or more metals laminated in order such as Ti / Pt / Au, Ti / Al / Pt / Au, W / Pt / Au, and V / Pt / Au.

<Protective layer>
The protective layer 34 covers and protects the p-side electrode 32, the n-side electrode 33, and the upper surface and side surfaces of the semiconductor element structure 3. The protective layer 34 is an insulating film and is particularly preferably made of an oxide film. The protective layer 34 is made of, for example, a Zr oxide film (ZrO ₂ ) or SiO ₂ .
The protective layer 34 is formed by, for example, sputtering, ECR (Electron Cyclotron Resonance) sputtering, CVD (Chemical Vapor Deposition), ECR-CVD, ECR-plasma CVD, vapor deposition, It can be formed by a known method such as an EB method (Electron Beam). Especially, it is preferable to form by ECR sputtering method, ECR-CVD method, ECR-plasma CVD method, etc.

(Metal layer)
As shown in FIG. 1B, the metal layer 4 includes a first metal layer 5 and a second metal layer 6. The first metal layer 5 is provided for bonding the semiconductor light emitting element 1 to an external member.
The second metal layer 6 is laminated between the second main surface (back surface) of the substrate 2 and the first metal layer 5.
In the present embodiment, the second metal layer 6 includes a light reflection layer 11, an adhesion layer 12, a first diffusion prevention layer 13, and a second diffusion prevention layer 14.
Each layer constituting these metal layers 4 can be formed by, for example, vapor deposition, sputtering, ion beam assisted vapor deposition, plating, or the like. Each layer is preferably formed on the entire second main surface of the substrate 2.

(Second metal layer)
<Light reflection layer>
The light reflecting layer 11 is provided in contact with the back surface of the substrate 2 and is a layer for efficiently reflecting the light emitted by the semiconductor element structure 3 and taking it out to the outside. The light reflection layer 11 is preferably a layer having a higher reflectance than the AuSn layer 7 with respect to the emission wavelength of the semiconductor element structure 3. Specifically, it is preferably formed of a layer made of a material such as Ag (silver), Al (aluminum), Rh (rhodium), or a single layer or a laminated structure such as an alloy of these materials.

<Adhesion layer>
The adhesion layer 12 is a layer provided in order to strengthen the adhesion between the light reflection layer 11 and the first diffusion prevention layer 13. Suitable materials for the adhesion layer 12 include, for example, iron group elements (Fe, Co, Ni), tungsten (W), chromium (Cr), molybdenum (Mo), manganese (Mn), and the like.

<First diffusion preventing layer and second diffusion preventing layer>
The first diffusion preventing layer 13 and the second diffusion preventing layer 14 protect the light reflecting layer 11 such as preventing AuSn from diffusing from the first metal layer 5 to the light reflecting layer 11.
As a material of the first diffusion preventing layer 13, for example, a platinum group element (Ru, Rh, Pd, Os, Ir, Pt) and an iron group element (Fe, Co, Ni) that is a similar element are suitable. .
As the material of the second diffusion prevention layer 14, the material of the first diffusion prevention layer 13, or gold (Au), tungsten (W), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V ), Niobium (Nb), tantalum (Ta), manganese (Mn), molybdenum (Mo), chromium (Cr), and the like, or alloys thereof.

  The second metal layer 6 may be composed of the light reflecting layer 11, the adhesion layer 12, and the first diffusion preventing layer 13. In this case, from the substrate side, for example, a structure in which Ag / Ni / Rh is laminated, a structure in which Al / W / Pt is laminated, or the like can be given.

(First metal layer)
The first metal layer 5 includes a plurality of AuSn layers 7 provided in the thickness direction and an intermediate layer 8.
The intermediate layer 8 is a layer that is provided in contact with the AuSn layer 7 and is made of a material harder than AuSn in terms of Mohs hardness.
An intermediate layer 8 is interposed between the two AuSn layers 7. In the present embodiment, the first metal layer 5 is configured by alternately stacking AuSn layers 7 and intermediate layers 8. The film thickness of the intermediate layer 8 is smaller by about one digit than the film thickness of the AuSn layer 7, but is exaggerated in FIG.

  In the example of the first metal layer 5 shown in FIG. 1B, the AuSn layer 7, the intermediate layer 8, the AuSn layer 7, the intermediate layer 8, and the AuSn layer 7 are laminated in this order from the substrate 2 side. That is, among the plurality of layers constituting the first metal layer 5, the uppermost layer and the lowermost layer are the same and are the AuSn layer 7. The number of AuSn layers 7 and the number of intermediate layers 8 are different.

<AuSn layer>
The AuSn layer 7 is preferably a eutectic alloy film containing Au and Sn as main components. AuSn eutectic means an Au content of 80% or more.
The sum of the film thicknesses of the plurality of AuSn layers 7 in the first metal layer 5 is about the same as the numerical range used as the film thickness of AuSn consisting of one layer like the light emitting element 100. The total thickness of the plurality of AuSn layers 7 in the first metal layer 5 is preferably 2.8 to 4.2 μm, and more preferably 3.2 to 3.8 μm. The thickness is particularly preferably about 3.5 μm. The reason for this is to enable mounting. For example, if the total thickness of the AuSn layer 7 is smaller than, for example, 2.8 μm, a semiconductor light emitting element using AuSn eutectic for the first metal layer 5 may not be mounted on the package of the light emitting device. On the other hand, if the usage amount of the AuSn layer 7 is increased more than necessary and the total value of the film thickness of the AuSn layer 7 is larger than 4.2 μm, the heating time assumed for mounting is insufficient for melting. There is a risk that the adhesion will be reduced.

<Intermediate layer>
In the present embodiment, the intermediate layer 8 is made of a material harder than AuSn. That is, the intermediate layer 8 is preferably made of a material having a hardness larger than the hardness (Mohs hardness) of AuSn. Here, as a material harder than AuSn, for example, a metal material mainly composed of at least one selected from the group consisting of Ag, Ni, Rh, Al, W, Pt, Ti, Ru, Mo, and Nb Can be mentioned.
In particular, when Rh is used, it is possible to reduce AuSn from turning around to the substrate side by heating as will be described later. When Ni is used, peeling of the metal layer 4 can be effectively reduced as will be described later.

Of the first metal layer 5, the thickness of the intermediate layer 8 is preferably less than 0.1 μm although it depends on the type of material. Further, when Rh is used for the intermediate layer 8, the film thickness is preferably in the range of 0.01 to 0.05 μm as described later.
When the thickness of the intermediate layer 8 is thinner than 0.1 μm, for example, the mountability to a reflow type package is improved. On the other hand, the lower limit of the film thickness of the intermediate layer 8 is preferably thicker than 0.001 μm. This is because it is extremely difficult to form a film of 0.001 μm or less with high accuracy.

[3. Outline of Manufacturing Method of Semiconductor Light Emitting Element]
The manufacturing method of the semiconductor light emitting element 1 mainly includes a first step, a second step, and a third step. The first step is a step of preparing the semiconductor multilayer structure 3 formed on the first main surface of the substrate 2. For example, a semiconductor is stacked on the first main surface of the wafer substrate (the front side of the substrate 2). Thus, the semiconductor multilayer structure 3 including the light emitting layer is formed. The second step is a step of forming a metal laminated structure (metal layer) 4 including the first metal layer 5 by laminating metal on the second main surface of the wafer substrate (the back side of the substrate 2). The subsequent third step is a step of dividing the wafer substrate into each element 1. The second step includes a first metal layer forming step for forming the first metal layer 5 in the metal laminated structure 4. The method for manufacturing a semiconductor light emitting device according to the embodiment of the present invention is characterized by this first metal layer forming step. In the first metal layer forming step, as the first metal layer 5 on the back side of the substrate, a plurality of AuSn layers 7 provided in the thickness direction and an intermediate layer 8 are stacked.

[4. Details of Manufacturing Method of Semiconductor Light Emitting Element]
Hereinafter, the details of the manufacturing method of the semiconductor light emitting device 1 will be described with reference to FIG.
FIG. 3A shows a cross section of the semiconductor multilayer structure laminated on the wafer substrate in the first step. This first step is a step of forming the semiconductor multilayer structure 40 by stacking GaN semiconductors by epitaxial growth on the first main surface of the sapphire substrate 20 as a round wafer substrate. Here, the semiconductor stacked structure 40 includes an n-side semiconductor layer, a light emitting layer, and a p-side semiconductor layer. In addition, a transparent electrode layer, a p-side electrode, an n-side electrode, and a protective layer are sequentially stacked on the semiconductor stacked structure 40.

  Next, preparatory steps for the second and third steps are performed. First, the back surface (second main surface) of the sapphire substrate 20 is ground and polished to thin the sapphire substrate 20. A cross section of the thinned sapphire substrate 20 is shown in FIG. Next, as shown in FIG. 3C, the laser beam 200 is irradiated inside the sapphire substrate 20 along a cutting line to be cut. At this time, laser irradiation is performed from the back surface (second main surface) side of the sapphire substrate 20 to a position to be a cutting line of the element. At this stage, it is not yet broken into individual pieces.

  FIG. 3D shows a cross section of the metal laminated structure (metal layer) laminated on the back side of the substrate in the second step. The second step is a step of forming a metal laminated structure 50 including a first metal layer by laminating a metal on the second main surface of the sapphire substrate 20. Here, the metal laminated structure 50 is obtained by laminating the second metal layer and the first metal layer in this order. That is, the second step includes a second metal layer forming step and a first metal layer forming step. Specifically, first, in the second metal layer forming step, the second metal layer is laminated on the entire back surface of the sapphire substrate 20 by sputtering. That is, an Ag film, Ni film, Rh film, and Au film are sequentially stacked. Further, in the first metal layer forming step, the first metal layer is laminated on the entire surface from above the second metal layer by sputtering. That is, for example, AuSn layers, intermediate layers, AuSn layers, intermediate layers, and AuSn layers are alternately stacked. Here, a material harder than AuSn is used as the material of the intermediate layer.

  FIG. 3E shows a wafer substrate cross section when the wafer substrate is divided in the third step. The third step is a step of dividing the sapphire substrate 20 on which the semiconductor multilayer structure 40 and the metal multilayer structure 50 are formed for each semiconductor light emitting element 1. More specifically, the sapphire substrate 20 is placed on a sheet (not shown) with the first main surface side (semiconductor multilayer structure 40 side) of the sapphire substrate 20 facing down and the back surface side (metal multilayer structure 50) facing up. The sapphire substrate 20 is sandwiched between the sheet and the film by placing and placing a film (not shown) on the upper surface of the sapphire substrate 20. A metal ring for stepwise feeding of the sheet is connected to the end of the sheet, and the sapphire substrate 20 in this state is on the conveyor 210 of the breaking device that breaks with the blade 240 by pushing the wafer from above. In a stepwise manner along the position of the scribe line that has already been irradiated with the laser. At this time, the sapphire substrate 20 is moved so as to advance to a predetermined dividing point of the scribe line, and is sandwiched from above and below by the fixed lower part 220 and the fixing upper part 230 of the breaking device, and then divided by the blade 240 and sent to the next dividing point. Repeat the operation. Thereby, it becomes an element separated into pieces.

  A light emitting device can be manufactured by mounting one or more semiconductor light emitting elements 1. In this case, the step of fixing the semiconductor light emitting element to an external mounting substrate such as a package includes a heating step of heating the package in order to thermocompress the first metal layer including the AuSn layer. Thereafter, a process of connecting the n-side electrode and the p-side electrode of the semiconductor light emitting element and the inner leads of the mounting substrate with wires, and a process of sealing the semiconductor light emitting element in a package are mainly performed. In addition, a package manufacturing process, a package plating process, a cleaning process, an unnecessary object removing process, a protective element bonding process, and the like are performed as necessary.

  As described above, according to the semiconductor light emitting device of the present embodiment, a plurality of AuSn layers that are thinner than the conventional single AuSn layer are used as the first metal layer constituting the metal layer laminated on the back side of the substrate. Since the intermediate layer is provided between the AuSn layers, it is easy to divide. Therefore, peeling of the metal layer from the substrate can be reduced.

  In addition, according to the method of manufacturing a semiconductor light emitting device of this embodiment, before the substrate is divided for each semiconductor light emitting device, a process of forming a thin AuSn layer as compared with a conventional single layer AuSn layer is performed. Since the step of laminating the intermediate layer in contact with the thin AuSn layer is added, it is easy to divide in the step of dividing the substrate. Therefore, peeling of the metal layer from the substrate can be reduced, and as a result, the yield can be improved.

  As mentioned above, although this embodiment was described, this invention is not limited to these, It can implement variously in the range which does not change the meaning. For example, the first metal layer 5 has been described as having three AuSn layers and two intermediate layers 8 interposed therebetween, but the AuSn layer may be two or more. In the case of two AuSn layers, the thickness of each AuSn layer is increased compared to the case of three layers. If there are three layers, for example, AuSn layer (1100 nm) + intermediate layer + AuSn layer (1100 nm) + intermediate layer + AuSn layer (1300 nm), when two layers are formed, AuSn layer (1700 nm) + intermediate layer + AuSn layer (1800 nm) may be used.

  As a modification of the first metal layer 5, the intermediate layer 8, the AuSn layer 7, the intermediate layer 8, the AuSn layer 7, and the intermediate layer 8 may be laminated in this order from the substrate 2 side. As another modification, the number of AuSn layers 7 and the number of intermediate layers 8 may be the same. The intermediate layer 8 may be interposed between the AuSn layers, and the intermediate layer may not be provided before the AuSn layer is stacked or after the AuSn layer is stacked.

In order to confirm the performance of the semiconductor light emitting device 1 of the present invention, the following experiments 1 to 6 were performed.
Experiment 1 is an experiment in which the rate of occurrence of peeling of the metal layer described later is measured when only the material conditions of the intermediate layer 8 are changed in the semiconductor light emitting device 1 of the present invention.
Experiment 2 is an experiment for searching for a material suitable as the intermediate layer 8 from a viewpoint different from the peeling rate of the metal layer accompanying Experiment 1.
Experiment 3 is an experiment in which the peeling rate of the metal layer is measured when only the film thickness condition of the intermediate layer 8 is changed in the semiconductor light emitting device 1 of the present invention.
Experiment 4 is an experiment for finding a film thickness suitable as the intermediate layer 8 from a viewpoint different from the occurrence rate of peeling of the metal layer accompanying Experiment 3.
Experiment 5 is an experiment for verifying the peeling rate of the metal layer of the semiconductor light emitting element using the specific film thickness and the specific material derived from Experiments 1 to 4 as the intermediate layer 8.
Experiment 6 is an experiment accompanying the experiment 5 to verify the adhesion of the first metal layer.
Hereinafter, the definition of the metal layer peeling occurrence rate and Experiments 1 to 6 will be described in order.

<Rate of metal layer peeling>
2A and 2B show a light emitting device 100 of a comparative example in which the metal layer is not peeled off. On the other hand, FIG. 4A and FIG. 4B show the light emitting device 100 of this comparative example in which the metal layer peeled off.

  Compared with the plan view, the light emitting element 100 shown in plan view in FIG. 4A is different from the light emitting element 100 shown in plan view in FIG. 2A in that the metal layer region 301 is exposed. It is different.

  Further, in comparison with the cross-sectional views, in the light-emitting element 100 shown in the cross-section taken along the line CC in FIG. 4B, the region 301 of the metal layer is exposed and the region 302 of the substrate is exposed. This is different from the light emitting element 100 shown in FIG. 2B as a cross section taken along line BB.

  Here, the peeling of the metal layer means that not all of the metal layer 4 formed on the entire surface of the substrate 2 is peeled off, but a region 302 where the metal layer is not laminated is formed on the back surface of the substrate. Further, the peeling of the metal layer means that the position of the metal layer 4 laminated on the back side of the substrate 2 is as if shifted in the horizontal direction, as shown in FIG. If the metal layer is not peeled off when the wafer is divided, the position of the metal layer 4 laminated on the back surface side of the substrate 2 is flush with the substrate 2 as shown in FIG.

  Conventionally, when mass-producing semiconductor light-emitting elements, when a wafer substrate is divided, a part where the metal layer on the back side of the substrate is peeled is included at a certain ratio. The ratio of the metal layer peeled in a predetermined number of sets (1 lot = 3600) is defined as the metal layer peeling occurrence rate below. Moreover, the element from which the metal layer has been peeled is defined as a defective product having poor cleaving property, and the element from which the metal layer is not peeled is defined as a good product having good cleaving property. (Yield) is represented by 1- (rate of occurrence of peeling of metal layer).

  The method of checking the rate of occurrence of metal layer peeling is to divide the wafer, align the elements, and count the elements on which the metal layer is peeled off (tearing) from the front side (device side). . At this time, for example, when the element is visually observed using a microscope and the metal layer region 301 is exposed as shown in FIG. 4A, the metal layer is peeled off (stripped). Count as you are. Note that the portion where the metal layer region 301 is exposed does not necessarily appear in the left-right direction in FIG. 4A, and the metal layer region 301 may be exposed in the vertical direction.

<Experiment 1>
In the metal layer 4 of the semiconductor light emitting device 1 of the present invention, the second metal layer 6 (light reflecting layer 11, adhesion layer 12, first diffusion preventing layer 13, second diffusion preventing layer 14) is formed from the substrate side by Ag / Ni / Rh / Au was laminated. And in the 1st metal layer 5 which comprises the metal layer 4, the difference in peeling rate of a metal layer when only the material conditions of the intermediate | middle layer 8 were changed was measured. Here, a metal having a higher hardness than AuSn was used as the material of the intermediate layer. If the metal is laminated as the second metal layer 6, it can be easily prepared for the first metal layer 5 to be laminated next to the second metal layer 6 in the manufacturing process. Therefore, Ni used for the adhesion layer 12, Rh used for the first diffusion prevention layer 13, and W that can be used for the adhesion layer 12 were prepared. And the conditions of material and film thickness were changed like the following Examples 1, 2, 3 and Comparative Example 1.

Example 1
The intermediate layer was Ni and the film thickness was 50 nm (500 mm).
Specifically, as the first metal layer 5 of the semiconductor light emitting device 1 according to the embodiment of the present invention, each film thickness in the order of AuSn / Ni / AuSn / Ni / AuSn from the substrate side to the back surface of the sapphire substrate. [Nm] was laminated as 1100/50/1100/50/1300. Here, the AuSn layer provided in three layers has a total thickness of 3500 [nm] (3.5 μm). Thereafter, the sapphire substrate was divided to obtain one lot of semiconductor light emitting devices. This material condition and film thickness condition are defined as Example 1. The hardness of Ni is 4.0. Table 1 shows the peeling rate of the metal layer as a measurement result. The wraparound amount d in Table 1 was obtained in Experiment 2 and will be described later.

(Example 2)
Ni in Example 1 was replaced with Rh to obtain one lot of semiconductor light emitting devices in the same manner. This material condition and film thickness condition are defined as Example 2. The hardness of Rh is 6.0. Table 1 shows the measurement results of the rate of occurrence of peeling of the metal layer.

(Example 3)
Ni in Example 1 was replaced with W to obtain one lot of semiconductor light emitting devices in the same manner. This material condition and film thickness condition are defined as Example 3. The hardness of W is 7.5. Table 1 shows the measurement results of the rate of occurrence of peeling of the metal layer.

(Comparative Example 1)
As the light emitting element 100, the first metal layer 5 was made of AuSn, and the thickness thereof was 3500 [nm] (3.5 μm). Other than that, one lot of semiconductor light emitting devices was obtained in the same manner as in Examples 1 to 3. This material condition and film thickness condition are referred to as Comparative Example 1. The hardness of Au is 2.5, and the hardness of Sn is 1.5. Since the AuSn eutectic has an Au content of 80% or more, the hardness of AuSn is expressed as 2.5 here, but it is actually a value smaller than 2.5. Table 1 shows the measurement results of the rate of occurrence of peeling of the metal layer. Although Comparative Example 1 does not have an intermediate layer, Table 1 shows the hardness of AuSn as 2.5.

  As shown in Table 1, in Examples 1, 2, and 3, the occurrence rate of metal layer peeling was smaller than that in Comparative Example 1. That is, according to the conditions of Examples 1, 2, and 3, it is possible to reduce the peeling of the metal layer from the substrate of the semiconductor light emitting element and increase the ratio of non-defective products having good cleaving properties.

<Experiment 2>
Rh used for the intermediate layer 8 as the condition of Example 2 is the same as the material used for the first diffusion prevention layer 13 constituting the second metal layer 6 of the semiconductor light emitting device 1. For this reason, according to the conditions of Example 2, it is considered that the effect of preventing AuSn from diffusing from the first metal layer 5 to the light reflecting layer 11 is improved. Even under the conditions of Examples 1 and 3, the intermediate layer 8 is expected to have an effect of preventing the diffusion of AuSn. Further, it is considered that a material suitable for the intermediate layer 8 can be searched by examining the correlation between the effect of preventing diffusion of AuSn and the effect of reducing the peeling rate of the metal layer.

  Therefore, the effect of preventing the diffusion of AuSn was confirmed by using a material that was already known from Experiment 1 to reduce the metal layer peeling rate. For this purpose, a simple method was used for the experiment. That is, the semiconductor layer was not laminated on the first main surface of the wafer (sapphire substrate), the metal layer was laminated on the second main surface (back surface), and the wafer was not divided. That is, the semiconductor light emitting device itself was not manufactured, but the metal layer was laminated in the same manner as the method for manufacturing the semiconductor light emitting device 1. Moreover, the metal layer was laminated | stacked similarly to the manufacturing method of the light emitting element 100 of a comparative example. A schematic view of the produced wafer is shown in FIG.

  A cross section of the wafer 400 shown in a plan view on the upper side of FIG. 5A in a DD line is shown on the lower side of FIG. The wafer 400 is formed on the second main surface (back surface) of the sapphire substrate 420, as in Comparative Example 1, with the second metal layer (the light reflecting layer 11, the adhesion layer 12, the first diffusion preventing layer 13, and the second diffusion preventing layer). 14) and a single AuSn layer 7 are laminated. The wafer 400 has a hole 410 at the center where the second metal layer and the AuSn layer are not stacked. Assuming that the first principal surface side of the wafer (lower side in the sectional view of FIG. 5A) is observed with a microscope, the peripheral region corresponding to the light reflecting layer 11 is bright and the central circular region is dark. An image will be observed. The shape observed in such an image is the same shape as the upper plan view of FIG.

  A cross section of the wafer 500 taken along the line E-E shown in plan view on the upper side of FIG. 5B is shown on the lower side of FIG. The wafer 500 is different from the wafer 400 in that it has the three AuSn layers 7 as in the first to third embodiments. The diameter of the hole 510 of the wafer 500 is the same as the diameter of the hole 410 of the wafer 400. If this wafer 500 is also observed with a microscope from the first main surface side (lower side in the sectional view of FIG. 5B), the peripheral region corresponding to the light reflecting layer 11 is bright and the central circular region is dark. The same image will be observed as well. For this wafer 500, three types of wafers were prepared in which the material of the intermediate layer 8 was Ni, Rh, W.

  Each wafer 400, 500 was fabricated by the following process. First, the back side of the sapphire substrate is ground and polished (step S101). Then, patterning was performed on the back side of the thinned sapphire substrates 420 and 520 (step S102). Here, patterning was performed so as to mask almost the center of the entire back side of the substrate. Next, the second metal layer (the light reflection layer 11, the adhesion layer 12, the first diffusion prevention layer 13, and the second diffusion prevention layer 14) is sequentially laminated on the back side of the patterned sapphire substrates 420 and 520 (step S103). ). Next, a single AuSn layer 7 is stacked on the sapphire substrate 420 as a first metal layer (step S104a). On the other hand, the three AuSn layers 7 are stacked on the sapphire substrate 520 as the first metal layer with the intermediate layer 8 interposed (step S104b). Subsequently, the back side of the sapphire substrates 420 and 520 is lifted off (step S105). As a result, the central mask on the back side of the substrate and the first metal layer and the second metal layer laminated on the mask are removed. That is, the holes 410 and 510 were formed in the central part on the back side of the sapphire substrates 420 and 520, with the metal layer not being laminated and the back side of the substrate being exposed.

  The produced wafer (400 or 500, the same applies hereinafter) was heated by the heating means 600 shown in FIG. The heating means 600 includes a hot plate 601 and auxiliary means for assisting heating by the hot plate 601. The auxiliary means includes an aluminum foil 602, an aluminum plate 603, and a SUS plate 604 in order from the bottom.

  The aluminum foil 602 is provided to bring the hot plate 601 and the aluminum plate 603 into close contact. On the aluminum plate 603, the wafer is placed with the back side (the first metal layer and the second metal layer side) facing down. The aluminum plate 603 is provided to facilitate heat transfer from below to the wafer. The SUS plate 604 is provided to bring the wafer into close contact with the aluminum plate 603.

  With the wafer sandwiched between the aluminum plate 603 and the SUS plate 604, the wafer was heated to 300 ° C. with the hot plate 601 and left at 300 ° C. for 5 minutes. After the heating, the SUS plate 604 was removed, the wafer was cooled to room temperature, and AuSn erosion (wraparound) was observed with a microscope from the first main surface side (front side) of the wafer.

  A schematic diagram of the cooled wafer is shown in FIG. A cross section of the wafer 400 taken along the line F-F shown in plan view on the upper side of FIG. 7A is shown on the lower side of FIG. The wafer 400 shown in FIG. 7A has a wider peripheral edge of the hole 410 and a lower bottom surface of the hole 410 than the wafer 400 shown in FIG. Here, the cross-sectional shape shown on the lower side of FIG. 7A is the cross section cut off after heating, although the second metal layer is divided corresponding to the cross-sectional view shown on the lower side of FIG. Then, each layer cannot be identified.

  When observed with a microscope from the first main surface side of this wafer 400 (lower side in the sectional view of FIG. 7A), the peripheral region corresponding to the light reflecting layer 11 is bright, and the smaller one corresponding to the bottom surface of the hole 410 is used. An image was observed in which the concentric region was dark and the annular region surrounded by two concentric circles was slightly dark. The shape of this image is the same as that of the upper plan view of FIG. The reason why the annular region became slightly dark is that AuSn eroded the second metal layer and turned around to the sapphire substrate 420 side and changed its color. When AuSn erodes the second metal layer, the function of the light reflecting layer 11 is impaired. Therefore, when manufactured as a light emitting device, the brightness decreases.

  Then, in order to quantify the degree of AuSn erosion, a wraparound amount d shown in FIG. 5A was defined. This wraparound amount d is surrounded by two concentric circles corresponding to the discolored region, that is, the holes when observed with a microscope from the first main surface side of the wafer provided with holes in the metal layer on the second main surface side. This is the length of the circular region in the radial direction.

  A cross section taken along line GG of the wafer 500 shown in plan view on the upper side of FIG. 7B is shown on the lower side of FIG. In the wafer 500 shown in FIG. 7B, the peripheral edge of the hole 510 is slightly expanded and the bottom surface of the hole 510 is slightly narrower than the wafer 500 shown in FIG. Here, the cross-sectional shape shown on the lower side of FIG. 7B is divided into layers corresponding to the cross-sectional view shown on the lower side of FIG. 5B, but the cross section cut after heating is an actual STM image. According to this, the AuSn layer 7 and the intermediate layer 8 are integrated so that they cannot be distinguished.

  When observed with a microscope from the first main surface side of this wafer 500 (lower side in the sectional view of FIG. 7B), the peripheral region corresponding to the light reflecting layer 11 is bright, and the smaller one corresponding to the bottom surface of the hole 510 is shown. An image in which the region of the concentric circles was dark and the ring region surrounded by the two concentric circles was discolored and slightly darkened was observed. The shape of this image is the same as that of the upper plan view of FIG.

  The wraparound amount d for the wafer 500 is smaller than the wraparound amount d for the wafer 400. The results are shown in Table 1 above. Note that the wraparound amount d is not measured by creating an element in which semiconductors are stacked, but is displayed side by side in correspondence with the example of the first metal layer having the same material, film thickness, and stacked structure. .

  When the intermediate layer 8 is provided in the bonding layer (first metal layer) as in Examples 1, 2, and 3 in Table 1, that is, in the case of the structure of the wafer 500, compared with the structure of the wafer 400, A remarkable effect of greatly preventing the diffusion of AuSn was observed. The effect of preventing the diffusion of AuSn was greatest when the same material (Rh) as that used for the first diffusion prevention layer 13 was used for the intermediate layer 8.

In the case where the intermediate layer 8 is not provided on the first metal layer as in Comparative Example 1, that is, in the case of the structure of the wafer 400, d = 11.53 μm. On the other hand, when Rh was used for the intermediate layer 8, the amount of wraparound d was 4.33 μm. When both are compared, when Rh is used for the intermediate layer 8, the amount of decrease in discoloration (wraparound amount) is 7.2 μm.
Therefore, the improvement rate at this time was 62.4% from 7.2 / 11.53. As a cause of such a small amount of discoloration wrapping, it is considered that there is some reaction such as being drawn to Rh during AuSn dissolution.

<Experiment 3>
Based on the result of Experiment 2, when the material of the intermediate layer 8 is fixed to Rh and only the film thickness condition of the intermediate layer 8 is changed, the difference in the occurrence rate of peeling of the metal layer is the same as in Experiment 1. Measured by the method. At this time, the conditions of the material and the film thickness were changed as in Examples 4 and 5 and Reference Examples below.

Example 4
The film thickness of Rh in Example 2 was replaced with 10 nm (100 mm), and similarly, one lot of semiconductor light emitting devices was obtained. This material condition and film thickness condition are referred to as Example 4. Table 2 shows the measurement results of the metal layer peeling rate.

(Example 5)
The film thickness of Rh in Example 2 was replaced with 30 nm (300 mm), and similarly, one lot of semiconductor light emitting devices was obtained. This material condition and film thickness condition are referred to as Example 5. Table 2 shows the measurement results of the metal layer peeling rate.

(Reference example)
The film thickness of Rh in Example 2 was replaced with 100 nm (1000 mm), and similarly, one lot of semiconductor light emitting devices was obtained. In the case of these material conditions and film thickness conditions, the metal layer peeling occurrence rate was worse than that of Comparative Example 1 in which the first metal layer was composed of a single AuSn layer. However, the wraparound amount d was better than that of Comparative Example 1 and Examples 2, 4, and 5. Table 2 shows the measurement results of the metal layer peeling rate for the reference example.
In addition, in order to contrast the measurement results of Comparative Example 1 and Example 2 shown in Table 1 with Examples 4 and 5 and the like, they are shown together in Table 2.

  As shown in Table 2, in Examples 4 and 5, the occurrence rate of peeling of the metal layer was smaller than that in Comparative Example 1. When Rh was used as the material for the intermediate layer 8, the metal layer peeling tendency tended to decrease as the film thickness decreased. When the Rh film thickness was 100 nm (1000 mm) as in the reference example, the metal layer peeling rate increased. One possible reason for this is that the film thickness of the entire first metal layer is 5% or more larger than that of the comparative example under the conditions of the reference example.

<Experiment 4>
Based on the result of Experiment 3, in order to confirm that even when the film thickness is reduced as in the conditions of Examples 4 and 5, there is the same effect of preventing diffusion of AuSn as in the condition of Example 2. The same method as in Experiment 2 was examined. At this time, with respect to the wafer 500, three kinds of wafers having different film thicknesses were prepared in accordance with the conditions of Examples 4 and 5 and the reference example after setting the material of the intermediate layer 8 to Rh.

  The wraparound amount d for the wafer 500 is smaller than the wraparound amount d for the wafer 400. The results are shown in Table 2. Note that the wraparound amount d was not measured by creating an element in which semiconductors were stacked, but was displayed side by side in correspondence with an example in which the material, film thickness, and stacked structure of the first metal layer were the same.

  As shown in Table 2, when the material of the intermediate layer 8 is Rh, the diffusion preventing effect of AuSn tends to increase slightly as the thickness of the intermediate layer 8 is in the range of 10 to 1000 nm. . As a result, it was confirmed that Examples 4 and 5 also had the same effect of preventing diffusion of AuSn as in Example 2.

<Experiment 5>
As a result of Experiment 1, when the rate of occurrence of peeling of the metal layer was the lowest, the material used for the intermediate layer 8 was Ni. As a result of Experiment 3, the thickness of the intermediate layer 8 when the peeling rate of the metal layer was the lowest was 10 nm. Therefore, it is expected that the best result can be obtained with this combination, so an experiment was conducted to verify this.

(Example 6)
Using the material (Ni) of Example 1, the film thickness was replaced with 10 nm (100 mm), and similarly, one lot of semiconductor light emitting devices was obtained. This material condition and film thickness condition are defined as Example 6. Table 3 shows the measurement results of the metal layer peeling occurrence rate. In addition, in order to contrast the measurement results of Comparative Example 1 and Example 4 shown in Table 2 with Example 6, they are also shown in Table 3.

As shown in Table 3, according to the conditions of Example 6, the metal layer peeling occurrence rate was 8.5%, which was the best result as expected.
Here, it is replaced with a ratio (yield) of good products with good cleaving property per lot. Here, the yield [%] = 100− (the occurrence rate of peeling of the metal layer).
In this case, 77.4% is obtained in Comparative Example 1, 84.3% is obtained in Example 4, and 91.5% is obtained in Example 6. The yield of Example 6 increased by 14.1% from Comparative Example 1. Therefore, the increase rate at this time was 18.2% due to 14.1 / 77.4.

<Experiment 6>
In order to confirm the adhesion of the element formed by providing the intermediate layer 8 as in the conditions of Example 4 and Example 6 described in Table 3, a comparative experiment of die shear strength with Comparative Example 1 described in Table 3 was performed. It was. The destruction mode at the time of die sharing of the semiconductor light emitting device mounted on a predetermined mounting substrate was the interface between the substrate 2 and the second metal layer 6. Here, the second metal layer 6 was laminated on the back surface of the substrate 2 from the substrate side in the order of Ag / Ni / Rh / Au with the respective film thicknesses [nm] being 120/100/200/500.
The die shear strength is a shear strength measured as a load when the semiconductor chip is pushed from the side in the horizontal direction at a normal temperature and a high temperature and peeled off. A known die shear strength tester is used for this measurement. The die shear strength is defined in the JEITA standard (EIAJ ED4703) and the MIL standard (MIL-STD-883C).

  As a result of the experiment, the adhesion force to the mounting substrate of the element prepared by providing the intermediate layer 8 as in the conditions of Example 4 and Example 6 is about 700 gf, and the intermediate layer is applied as in the condition of Comparative Example 1. It was confirmed that it was almost the same as the element prepared without providing. That is, even when a measure for preventing the metal layer from peeling off from the substrate (a measure against tearing) was taken, the adhesion did not change. The reason is that the section cut after heating and mounting the semiconductor light emitting device 1 of the present embodiment is not separated from layer to layer in the AuSn layer 7 and the intermediate layer 8 according to the actual STM image. It is thought that. That is, since the AuSn layer 7 and the intermediate layer 8 are mixed in the first metal layer 5, the strength itself is maintained.

  In addition, in the said experiment, although the metal laminated | stacked as the 2nd metal layer 6 in the manufacturing process was performed as a material of an intermediate | middle layer, the material of an intermediate | middle layer is not limited to this. As the material for the intermediate layer, for example, Cu having a hardness of 3.0, Al having a hardness of 2.75, Ag having a hardness of 2.5, or the like may be used. An alloy may be used in addition to a single metal.

  The semiconductor light emitting device according to the present invention can be used for lighting fixtures, backlights, in-vehicle light emitting devices, displays, optical disc light sources, exposure light sources, and other general consumer light sources.

DESCRIPTION OF SYMBOLS 1 Semiconductor light emitting element 2 Board | substrate 3 Semiconductor element structure 4 Metal layer 5 1st metal layer 6 2nd metal layer 7 AuSn layer 8 Intermediate layer 11 Light reflection layer 12 Adhesion layer 13 1st diffusion prevention layer 14 2nd diffusion prevention layer 20 Sapphire substrate 21 n-side semiconductor layer 22 light-emitting layer 23 p-side semiconductor layer 31 transparent electrode layer 32 p-side electrode 321 pad portion 322 stretched conductive portion 33 n-side electrode 331 pad portion 332 stretched conductive portion 34 protective layer 40 semiconductor multilayer structure 50 Metal laminated structure

Claims (10)

A substrate, a semiconductor element structure stacked on the first main surface of the substrate, and a metal layer stacked on the second main surface opposite to the first main surface of the substrate. A semiconductor light emitting device,
The metal layer includes a first metal layer for bonding the semiconductor light emitting element to an external member,
The first metal layer includes a plurality of AuSn layers provided in a thickness direction, and an intermediate layer provided in contact with the AuSn layer and made of a metal material harder than AuSn. Semiconductor light emitting device.   The semiconductor light emitting device according to claim 1, wherein the first metal layer is configured by alternately stacking the AuSn layer and the intermediate layer.   The intermediate layer is made of a metal material mainly composed of at least one selected from Ag, Ni, Rh, Al, W, Pt, Ti, Ru, Mo, and Nb. 2. The semiconductor light emitting device according to 2.   4. The semiconductor light emitting element according to claim 1, wherein the intermediate layer has a thickness of less than 0.1 μm.   5. The semiconductor light emitting device according to claim 4, wherein the total film thickness of the AuSn layer is 2.8 to 4.2 μm.   A second metal layer including a layer having a higher reflectance with respect to light from the semiconductor element structure than the AuSn layer is provided between the second main surface of the substrate and the first metal layer. The semiconductor light emitting element according to claim 1. A first step of preparing a semiconductor multilayer structure formed on a first main surface of a substrate;
On the second main surface opposite to the first main surface of the substrate, a plurality of AuSn layers provided in the thickness direction and provided between the AuSn layers and made of a metal material harder than AuSn A second step of forming a first metal layer comprising an intermediate layer;
And a third step of dividing the substrate on which the semiconductor multilayer structure and the first metal layer are formed for each of the semiconductor light emitting elements.   8. The method of manufacturing a semiconductor light emitting element according to claim 7, wherein in the second step, the AuSn layer and the intermediate layer are alternately stacked.   The second step is characterized in that the intermediate layer is formed of a metal material mainly composed of at least one selected from Ag, Ni, Rh, Al, W, Pt, Ti, Ru, Mo, and Nb. The manufacturing method of the semiconductor light-emitting device according to claim 7 or 8.   8. The method according to claim 7, further comprising a step of forming a second metal layer having a higher reflectance with respect to light from the semiconductor element structure than the AuSn layer between the first step and the second step. The manufacturing method of the semiconductor light-emitting device as described in any one of Claim 9 thru | or 9.

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