JP2000323430A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a contact hole which comes into good contact with the surface of a semiconductor substrate in a semiconductor device equipped with SAC(Self-Aligned Contact)/BLC(Borderless Contact), to enhance the semiconductor device in degree of integration, to provide a good contact hole even if the semiconductor device is micronized in the direction parallel with the surface of the substrate, and furthermore to restrain a MOS transistor from deteriorating in reliability without making a side wall spacer complicated in structure. SOLUTION: A liner layer 9 of SiN film or the like is not provided between the side of a side wall spacer 6 and an interlayer insulating film 12. Therefore, the liner layer 9 can be formed thick enough, a gate structure can be widened in space, and contact holes 13 and 14 can be enhanced in contact area, so that an excellent contact can be realized. The gate structure is lessened in space, whereby a semiconductor device can be improved in degree of integration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a SAC (Self-alig
The present invention relates to a semiconductor device having n-contact / BLC (border-less contact) and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIGS. 21 to 24 are process sectional views showing a conventional method for manufacturing a semiconductor device. 21 to 24, reference numeral 101 denotes a Si substrate which is a semiconductor substrate, and reference numeral 102 denotes a field insulating film for electrically separating each element. In this case, the field insulating film is formed by using STI (Shallow Trench Isolation) technology. 103 is a gate oxide film of the MOS transistor, and 104 is its gate electrode formed of a conductive film. Reference numeral 105 denotes an offset insulating film formed only on the gate electrode 104, and reference numeral 106 denotes a sidewall spacer. 107 is a diffusion layer forming the source / drain of the MOS transistor, and 108 is salicide [Salicide (Self-
aligned silicide)] is a silicide layer formed only on the source / drain diffusion layer 107 of the MOS transistor by the technique, and 109 is a liner layer formed of a SiN film. Reference numeral 110 denotes an interlayer insulating film formed of a Si oxide film.

[0003] Reference numerals 111 and 112 denote contact holes for connecting the silicide layer 108 and the upper wiring layer 115, and reference numeral 111 denotes a contact hole (SAC) provided in a space interposed between the gate electrodes 104. Reference numeral 112 denotes a contact hole (SAC / BLC) provided in a space between the gate electrode 104 and the field insulating film 102.
BLC of C.

Reference numeral 113 denotes an adhesion layer formed of a conductive film also serving as a barrier metal, and reference numeral 114 denotes a W plug formed by blanket W growth and etch back thereof. Reference numeral 115 denotes a wiring layer formed of a conductive film.

Next, a conventional method for manufacturing a semiconductor device will be described. As shown in FIG. 21, first, a field insulating film 102 is formed on a Si substrate 101. Here, the STI technology is used. Si trench etching and S in the trench
i-oxide film filling and CMP (Chemical Mechanical Polish)
ing: chemical mechanical polishing).

Next, a gate oxide film 103 is formed by thermal oxidation using an electric furnace, and then a low pressure CVD (Chemical Vapor Deposition) is performed.
position) to form a polysilicon film to be a gate electrode, and to form an offset insulating film by a low pressure CVD method.
An iN film is formed. The gate electrode 104 and the offset insulating film 105 are formed by forming a resist pattern of the gate electrode by the reduced projection exposure technique, anisotropic dry etching of the SiN film, and anisotropic dry etching of the polysilicon film.

Next, a SiN film is formed by a low pressure CVD method, and a sidewall spacer 106 is formed by etch back on the entire surface. After forming the diffusion layer 107 by ion implantation, a silicide layer 108 is formed by salicide technology. Thereafter, a liner layer 109 is formed from a SiN film by a low pressure CVD method, and an interlayer insulating film 110 is formed by forming a Si oxide film by a normal pressure CVD method and flattening by CMP.
To form After the liner layer 109 is formed, the distance between the liner layers 109 formed on the side surfaces of the side wall spacers 106 of the two adjacent gate electrodes 104 is D, and the gate electrode 104 closest to the field insulating film 102 is formed. Liner layer 109 formed on the side surface of side wall spacer 106 and field insulating film 1
F is the interval (horizontal distance) from 02.

Next, as shown in FIG. 22, a resist pattern of a contact hole is formed by a reduced projection exposure technique.
The SAC contact hole 111 and the SAC / BLC are formed in the interlayer insulating film 110 by the anisotropic dry etching of the Si oxide film.
Is formed. In this etching, the etching is temporarily stopped at the liner layer 109 under the condition that the etching rate of the Si oxide film is sufficiently higher than that of the SiN film.

Further, as shown in FIG. 23, the liner layer 109 formed of a SiN film and exposed at the bottom of the contact holes 111 and 112 in the step of FIG. After removal, the surface of the silicide layer 108 is exposed, and the contact holes 111 and 112 are completed.

Next, as shown in FIG. 24, an adhesion layer 113 formed by laminating a Ti layer by DC magnetron sputtering and a TiN layer by reactive sputtering is formed in the contact holes 111 and 112. Thereafter, blanket W layers are buried in the contact holes 111 and 112 by plasma CVD, and W plugs 114 are formed by overall etch back. Furthermore, Ti by DC magnetron sputtering
A multi-layer conductive film formed by laminating a layer, a TiN layer formed by reactive sputtering, an Al alloy layer formed by DC magnetron sputtering, and a TiN layer formed by reactive sputtering, forming a resist pattern by a reduced projection exposure technique; The wiring layer 115 is formed by anisotropic dry etching of the film. Thereafter, in order to recover the damage of the MOS transistor, a heat treatment at about 400 ° C. is performed in an atmosphere containing hydrogen.

The above is the outline of the conventional semiconductor device manufacturing method. The purpose of the SAC is to eliminate the alignment margin between the gate electrode 104 and the contact hole 111 and increase the density of the semiconductor device. The BLC aims at eliminating the alignment margin between the field insulating film 102 and the contact hole 112 and increasing the density of the semiconductor device. Processing of contact holes 111 and 112 is performed using Si
The difference in the etching rate between the oxide film and the SiN film is used. That is, the contact hole 111 is formed by first etching for removing the Si oxide film first under the condition that the etching rate of the Si oxide film is sufficiently higher than that of the SiN film, and then performing second etching for removing only the SiN film. And a contact hole 112 is formed. The processing method is described in, for example, JP-A-8-203998 and JP-A-8-203998.
316313, JP-A-9-153546,
JP-A-9-260605, JP-A-9-45908
No., etc. Generally, the condition that the etching rate of the Si oxide film is higher than that of the SiN film can be realized by using a fluorocarbon-based gas mixed with a CO gas.

Further, as for the SAC technology, for example, Japanese Patent Application Laid-Open No. Hei 3-21030 discloses a liner layer 1 made of a SiN film.
JP-A-61-16571 discloses the use of a SiN film for the offset insulating film 105 and a SiN film for the sidewall spacer 106. Generally, the SiN film is formed by using a low pressure CVD method using ammonia and SiH ₄ gas or a plasma CVD method.
In order to simultaneously realize SAC and BLC, it is necessary to form at least the liner layer 109. Generally, in a semiconductor device having SAC and BLC, a structure in which a MOS transistor is covered with a SiN film is used. That is, the offset insulating film 105,
Sidewall spacer 1 is provided on the side wall of gate electrode 104.
In addition, a liner layer 109 is formed on the entire surface under the interlayer insulating film 110.

The liner layer 109 has a contact hole 111.
When the contact hole 112 is formed, the interlayer insulating film 11 is formed.
It functions as an etching stopper film at the time of the first etching for removing 0. After that, a second etching is performed, and the liner layer 109 of the SiN film remaining at the bottom of the contact after the first etching is removed, so that a contact hole 111 and a contact hole 112 are formed. By doing so, the contact hole 1 is formed by over-etching.
11 is the Si substrate 1 immediately below the sidewall spacer 106
01 will not be reached. In addition, contact hole 1
12 breaks through the field insulating film 102 and does not reach the substrate.

Further, when the misalignment is further increased and the contact hole 111 runs over the gate electrode 104, the offset insulating film 105 and the sidewall spacer 106 prevent a short circuit between the adhesion layer 113 and the gate electrode 104. . As described above, the contact hole 111 and the contact hole 112 can be formed without a margin for alignment between the gate electrode 104 and the field insulating film 102.

In FIGS. 23 and 24, A is the distance between the centers of two adjacent gate electrodes 104 (hereinafter referred to as “gate electrode center distance”), and B is the gate electrode 104 closest to the field insulating film 102. Between the center of the field insulating film 102 and the center of the field insulating film 102 (hereinafter referred to as “distance between the field insulating film and the gate electrode center”), and C is the contact hole 11.
1, the width of the silicide layer 108 formed below
Is the width of the silicide layer 108 formed below the contact hole 112, and x is the width of the liner layer 109 facing the contact holes 111 and 112.

In the conventional structure, the width of the contact hole 111 formed in the region between the two adjacent gate electrodes 104 is opened on the silicide layer 108 of C, and the opening width of the contact hole 111 on the surface of the silicide layer 108 (hereinafter referred to as the width). The effective opening width (referred to as “the effective opening width of the contact hole 111”) is the same as D, and D is approximately C-2x. In addition, the gate electrode 10
4 and an opening width of the contact hole 112 on the surface of the silicide layer 108 (hereinafter referred to as an “effective opening width of the contact hole 112”) formed on the silicide layer 108 having a width E formed in a region between the field insulating film 102. ) Is the same width as F, and is approximately Ex.

[0017]

However, in the above-mentioned conventional structure, the liner layer 109 is formed of a SiN film formed by a low pressure CVD method or a plasma CVD method.
It is formed not only vertically but also horizontally with respect to the substrate surface of the substrate 101. That is, the SiN film is also grown on the sidewalls of the sidewall spacers 106 formed on the sidewalls of the gate electrode 104 and the offset insulating film 105. This SiN film is formed in the contact holes 111 and 1 after the contact holes 111 and 112 are opened so that the contact openings are formed under the highly anisotropic etching conditions.
12 remain on the side walls and are not removed. As a result, in the contact hole 111, although the width of the silicide layer 108 is C, the gate electrode 1 after the formation of the liner layer 109 is formed.
Since the space between the holes 04 is D, the contact holes 111 having the space of C cannot be opened, and the effective opening width is almost C-2x. Depending on the processing conditions of the contact hole 111, C-2x and D have substantially the same interval. Further, in the contact hole 112, although the silicide layer 108 has the width of E, the contact hole 112 having the interval of E cannot be opened, and the effective opening width becomes almost Ex, and the contact hole Depending on the processing conditions 111, Ex and F have substantially the same interval. Contact hole 111
In the contact hole 112, a loss of a distance of 2x occurs, and a loss of a distance of x occurs in the contact hole 112.
13 is reduced (in other words, the diffusion layer 10
7 and the contact area between the contact layer 113 and the contact layer 113 are reduced). This decrease in contact area increases contact resistance,
As a result, a contact failure is likely to occur, which causes a decrease in the yield of the semiconductor device.

On the other hand, the contact hole 111 has a contact area due to the opening width of C-2x in which a loss of 2x has occurred, and the contact hole 112 has a contact area due to the opening width of Ex in which a loss of x has occurred. Even when a contact can be formed by the area, the sidewall spacer 106
Width x of liner layer 109 (SiN film) remaining on side wall of
Will hinder the improvement of the degree of integration. That is, in terms of the distance between the center of the gate electrodes, although the distance of A-2x can be achieved, it can only be reduced to A.

Since the liner layer 109 is provided in the gap between the gate electrodes 104 in addition to the sidewall spacers 106, the interlayer insulating film 1 between the adjacent gate electrodes 104 is formed.
There is a problem that the interval D for embedding 10 becomes small and the aspect ratio becomes too large, so that the interlayer insulating film 110 (Si oxide film) cannot be filled therein (see FIG. 25; FIG. 25).
In the above, 116 is a void portion where the interlayer insulating film 110 is not filled. If the interlayer insulating film 110 cannot be filled, not only the contact hole 111 and the contact hole 112 cannot be formed, but also the adhesion layer 113 and the W plug 114 are short-circuited with the adjacent contact hole.

Further, when the distance D between the adjacent gate electrodes 104 for embedding the interlayer insulating film 110 is reduced and the aspect ratio is increased, even if the interlayer insulating film 110 (Si oxide film) can be filled, the liner can be filled. Layer 109 (SiN
The first etching for removing the Si oxide film under the condition that the etching rate of the interlayer insulating film 110 (Si oxide film) is sufficiently higher than that of the film (Si film) is performed with an increase in the aspect ratio.
Since the etching selectivity between the SiN film and the Si oxide film decreases, it becomes very difficult to remove the Si oxide film filled in the gap D at the interval D.

The thickness of the liner layer 109 is determined by the interlayer insulating film 110 (Si oxide film) and the liner layer 109 (SiN film).
The thickness of the interlayer insulating film 110 is determined by the difference in the etching rate of the film and the thickness of the interlayer insulating film 110. The thickness of the interlayer insulating film 110 is proportional to the miniaturization in the horizontal direction with respect to the substrate surface due to restrictions on device characteristics. The liner layer 10
There is a limit to the reduction of the film thickness to nine. That is, the thickness of the liner layer 109 in the direction perpendicular to the substrate surface needs to correspond to the thickness of the interlayer insulating film 110, and a corresponding film grows in the horizontal direction relative to the substrate surface. Resulting in. Therefore, when further miniaturization is further pursued, the gap between the gate electrodes 104 is only formed by the liner layer 109,
That is, it is buried only by the etching stopper film (see FIG. 26). In this case, contact hole 1
11 cannot be opened.
As a result, the thickness of the liner layer 109 is restricted by the increase in the thickness, and the necessary and sufficient thickness determined by the difference between the etching rates of the Si oxide film and the SiN film and the thickness of the interlayer insulating film 110 is reduced by the offset insulating film. 105, the silicide layer 108, and the field insulating film 102.

When the sidewall spacer 106 is formed of a single-layer SiN film as described above, or when the liner layer 109 is formed of a thick film, hydrogen does not pass therethrough, and contains hydrogen after the wiring layer 115 is formed. The characteristics are not restored by the heat treatment in the atmosphere, and problems such as a change in the characteristics of the MOS transistor and a decrease in reliability due to the occurrence of an interface order are caused. In order to prevent this, for example, Japanese Patent No. 268
No. 5034 (registration date; August 15, 1997), as described as an example,
6, a method such as forming a two-layer film of a SiN film and a Si oxide film, and a method of forming the liner layer 109 with a two-layer film of a SiN film and a Si oxide film are used. However, in such a case, particularly, the total thickness of the liner layer 109 is determined by the difference between the etching rates of the Si oxide film and the SiN film and the required thickness of the SiN film determined by the thickness of the interlayer insulating film 110. In addition, since the underlying Si oxide film is added, the film thickness is further increased. Therefore, the gate electrode 10
4 is too small, the aspect ratio becomes too large, and the Si oxide film cannot be filled therein. Also, the gap between the gate electrodes 104 only forms the liner layer 109, that is, only the etching stopper film is formed. There is a problem that the problem of being buried easily occurs, which is disadvantageous for miniaturization.

Further, since the MOS transistor is covered with the thick liner layer 109, it is difficult for hydrogen to pass therethrough. In order to prevent problems such as fluctuations in characteristics of the above and a decrease in reliability due to generation of an interface order, heat treatment at a higher temperature for a long time is required. Also, even if heat treatment is applied for a long time at high temperature,
It may not recover.

Further, in order to prevent problems such as a change in the characteristics of the MOS transistor and a decrease in reliability due to the occurrence of an interface order due to the effect of being covered with the liner layer 109, the side wall spacer 106 is complicated. There is a problem that it needs to be structured.

An object of the present invention is to solve the above-mentioned conventional problems, to form a contact hole (opening) for obtaining a good contact with the surface of a semiconductor substrate, to improve the degree of integration, and to improve the degree of integration. Good contact holes can be formed even when miniaturization in the horizontal direction is performed, and furthermore, problems such as reduction in reliability of MOS transistors do not occur without making sidewall spacers (sidewall insulating films) complicated. And a method of manufacturing the same.

[0026]

According to the present invention, there is provided a semiconductor device comprising:
A field insulating film buried in a groove formed in a semiconductor substrate is provided, and a gate insulating film, a gate electrode, and a first insulating film are sequentially stacked on the semiconductor substrate to form a gate insulating film, a gate electrode, and a first insulating film. A plurality of gate structures with side wall insulating films formed on the side walls are provided, and source / drain diffusion layers are provided on the surface of the semiconductor substrate so as to sandwich the gate electrode, and a second insulating film is formed on the semiconductor substrate and the gate structure. A first opening in which an interlayer insulating film is provided on the second insulating film, and a predetermined portion of the interlayer insulating film and the second insulating film is removed to expose the surface of the semiconductor substrate between the gate structures; (SAC) and a second opening (BLC) where both surfaces of the field insulating film and the semiconductor substrate are exposed,
A semiconductor device in which a wiring layer electrically connected to a surface of a semiconductor substrate via a first opening and a second opening is provided on an interlayer insulating film, wherein the second insulating film has a side wall insulation. It is characterized in that the film thickness between the side surface of the film and the interlayer insulating film is set to a small film thickness through which hydrogen can pass during heat treatment in an atmosphere containing hydrogen. Further, the second insulating film is characterized in that the film thickness between the side surface of the side wall insulating film and the interlayer insulating film is made zero.

According to this structure, almost no or no second insulating film (liner layer) is formed between the side surface of the sidewall insulating film (sidewall spacer) and the interlayer insulating film. Therefore, the thickness of the second insulating film can be increased, and the distance between the gate structures can be kept wide, and an opening (contact hole) having a larger contact area can be formed, and a good contact can be obtained. be able to. In addition, the distance between the gate structure portions is reduced, so that the degree of integration and the size of the semiconductor device can be reduced. Further, even if the substrate surface is miniaturized in the horizontal direction, a good contact opening can be formed. In addition, even if the thickness of the second insulating film is increased, the distance between the gate structures can be kept wide, so that the interlayer insulating film can be easily filled between the gate structures and the opening for forming the opening can be formed. Will also be easier. In addition, during the heat treatment in an atmosphere containing hydrogen, hydrogen does not become impossible to pass through the second insulating film, so that the characteristics can be easily recovered by the heat treatment, and the sidewall insulating film does not have a complicated structure. Problems such as fluctuations in the characteristics of the MOS transistor and a decrease in reliability due to the occurrence of interface order can be prevented.

Preferably, the sidewall insulating film and the interlayer insulating film are silicon oxide films.

Further, the present invention is characterized in that a lower insulating film (first liner layer) is provided in contact with a lower portion of the second insulating film (second liner layer) and in the same region as the second insulating film. I do. By providing the lower insulating film, the influence of the stress of the second insulating film on the surface of the semiconductor substrate can be reduced. This lower insulating film is also preferably a silicon oxide film, like the sidewall insulating film and the interlayer insulating film.

It is preferable that the second insulating film is a silicon nitride film, a silicon oxynitride film, or a metal oxide film because the etching selectivity with respect to the interlayer insulating film can be increased. If a metal oxide film is used, the thickness can be further reduced.

According to the method of manufacturing a semiconductor device of the present invention, a step of forming a groove in a semiconductor substrate and embedding a field insulating film in the groove is performed, and a gate insulating film, a gate electrode and a first insulating film are sequentially laminated on the semiconductor substrate. Forming a plurality of gate structures in which side wall insulating films are formed on side walls of the gate insulating film, the gate electrode, and the first insulating film; and forming source / drain diffusion layers on the surface of the semiconductor substrate with the gate electrode interposed therebetween. Forming a second insulating film on the semiconductor substrate and the gate structure by a method in which growth in the horizontal direction with respect to the surface of the semiconductor substrate is suppressed; and after forming the second insulating film, A step of forming an interlayer insulating film on the entire surface, and selectively etching the interlayer insulating film and the second insulating film to form a first opening (SAC) in which the surface of the semiconductor substrate between the gate structures is exposed. self Forming a second opening (BLC) in which both surfaces of the field insulating film and the semiconductor substrate are exposed at the same time as forming the semiconductor substrate through the first opening and the second opening; Forming a wiring layer electrically connected to the surface of the semiconductor device on the interlayer insulating film.

According to this manufacturing method, little or no second insulating film (liner layer) is formed between the side surface of the sidewall insulating film (sidewall spacer) and the interlayer insulating film. Therefore, the thickness of the second insulating film can be increased, and the distance between the gate structures can be kept wide, and an opening (contact hole) having a larger contact area can be formed, and a good contact can be obtained. be able to. In addition, the distance between the gate structure portions is reduced, so that the degree of integration and the size of the semiconductor device can be reduced. Further, even if the substrate surface is miniaturized in the horizontal direction, a good contact opening can be formed. Further, even if the thickness of the second insulating film is increased, the distance between the gate structures can be kept wide.
The space between the gate structures is easily filled with the interlayer insulating film, and the etching for forming the opening is also facilitated. In addition, during the heat treatment in an atmosphere containing hydrogen, hydrogen does not become impossible to pass through the second insulating film, so that the characteristics can be easily recovered by the heat treatment, and the sidewall insulating film does not have a complicated structure. Problems such as fluctuations in the characteristics of the MOS transistor and a decrease in reliability due to the occurrence of interface order can be prevented.

In the step of forming the second insulating film, it is preferable to form the film by strong anisotropic sputtering by extracting only the component which is perpendicularly incident on the surface of the semiconductor substrate.

The step of forming the first and second openings includes a first etching step of selectively etching the interlayer insulating film and a second etching step of selectively etching the second insulating film. Since the second insulating film serves as a stopper film for etching in the first etching step, the side wall insulating film is not etched in the first etching step.

Preferably, the side wall insulating film and the interlayer insulating film are silicon oxide films.

Further, according to the present invention, before forming the second insulating film, the lower insulating film (the second insulating film) may be formed on the semiconductor substrate and the gate structure by a method in which the growth in the horizontal direction with respect to the semiconductor substrate surface is suppressed. Forming a first insulating film (second liner layer), forming a second insulating film (second liner layer) on the lower insulating film, and forming first and second openings. It is characterized in that the lower insulating film is selectively etched in addition to the insulating film. By forming the lower insulating film, the influence of the stress of the second insulating film on the surface of the semiconductor substrate can be reduced.

In this case, the step of forming the first and second openings includes the first step of selectively etching the interlayer insulating film.
And a second etching step of continuously and selectively etching the second insulating film and the lower insulating film, and the second insulating film becomes a stopper film for the etching in the first etching step. In addition, the side wall insulating film and the lower insulating film are not etched by the first etching step.

The lower insulating film is also preferably a silicon oxide film, like the sidewall insulating film and the interlayer insulating film.

It is preferable that the second insulating film is formed of a silicon nitride film, a silicon oxynitride film, or a metal oxide film because the etching selectivity with respect to the interlayer insulating film can be increased. Further, if a metal oxide film is used, the thickness can be further reduced.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, wherein 1 is a Si substrate as a semiconductor substrate, 2 is a field insulating film, 3 is a gate oxide film (gate insulating film) of a MOS transistor, 4 is a gate electrode of a MOS transistor, 5 is an offset insulating film (first insulating film), 6 is a sidewall spacer (sidewall insulating film), 7 is a diffusion layer constituting a source / drain of the MOS transistor, and 8 is a silicide layer. , 9 is a liner layer (second insulating film), 10 is a liner layer α region, 11 is a liner layer β region, 12 is an interlayer insulating film, and 13 is a contact hole (SA) as an opening.
C) and 14 are contact holes (SAC / BL) which are openings.
C), 15 are an adhesion layer, 16 is a W plug, and 17 is a wiring layer. The gate structure is composed of a gate oxide film 3, a gate electrode 4, an offset insulating film 5, and a sidewall spacer 6.

The field insulating film 2 is for electrically isolating each element, and in the present embodiment, the STI (Shall
The trench formed on the Si substrate 1 is filled with a Si oxide film using an ow Trench Isolation technique. S in this groove
By filling the i-oxide film, both ends of the groove can be electrically separated, and an independent potential can be given.

The gate oxide film 3 of the MOS transistor is
In the present embodiment, it is composed of a Si oxide film. The gate oxide film 3 may be a Si oxide film containing a small amount of N. This improves the reliability when the gate oxide film 3 is made thinner,
This is advantageous for miniaturization.

In the present embodiment, the gate electrode 4 of the MOS transistor is formed of a polysilicon layer containing P as an impurity. The gate electrode 4 may be formed of a polysilicon layer containing B as an impurity depending on the type of MOS transistor to be formed. Further, it may be formed of a two-layer film of a polysilicon layer containing impurities, a silicide layer of W or Ta, or a metal layer of W or Mo. Generally, the former is called a polycide gate electrode, and the latter is called a polymetal gate electrode. In any case, a sufficient impurity is contained in the polysilicon layer so that the depletion layer does not spread in the polysilicon film due to a change in potential.

The offset insulating film 5 is an insulating film formed only on the gate electrode 4, and in this embodiment, is constituted by a Si oxide film. The offset insulating film 5 functions as an etching mask when the gate electrode 4 is processed. Further, when the sidewall spacers 6 are formed, the surface of the gate electrode 4 is prevented from being exposed, and the silicide layer 8 is prevented from being formed on the gate electrode 4. Further, it functions as an ion implantation mask when forming the diffusion layer 7 and prevents the implanted ion species from penetrating through the gate electrode 4 and reaching the Si substrate 1. In addition,
The same effect can be obtained even if the offset insulating film 5 is made of a SiN film. Further, a multilayer structure in which a Si oxide film and a SiN film are arbitrarily combined may be used.

In this embodiment, the side wall spacer 6 is formed of a Si oxide film. The side wall spacers 6 work to make the impurity profile appropriate in order to reduce charges near the drain of the MOS transistor.

The diffusion layer 7 is formed by ion implantation.
It constitutes the source / drain of the MOS transistor. The diffusion layer 7 includes a silicide layer 8 and contact holes 13 and 14.
Is electrically connected to the wiring layer 17 via the adhesion layer 15 and the W plug 16 filled in the substrate. In the present embodiment, an n-type diffusion layer formed by implanting As ions is used.
In this case, a p-type well (not shown) is formed in the Si substrate 1, and an n-type diffusion layer 7 is formed on the surface of the p-type well. The same effect can be obtained even if the diffusion layer 7 is a p-type diffusion layer formed by BF ₂ ion implantation. In this case, an n-type well (not shown) is formed on the Si substrate 1. The p-type diffusion layer 7 is formed on the surface of the n-type well.

The silicide layer 8 is formed only on the source / drain diffusion layer 7 of the MOS transistor by the salicide technique. The silicide layer 8 is glued on the diffusion layer 7 in a self-aligned manner.
5 is provided to reduce the contact resistance with 5. Thereby,
The driving capability can be improved by reducing the parasitic resistance of the MOS transistor. In the present embodiment, it is composed of a Co silicide layer. The effect of the present invention does not change even if the silicide layer 8 is not formed.

The liner layer 9 is formed of a SiN film.
Here, for the sake of explanation, a region above the silicide layer 8 having the diffusion layer 7 as a lower layer and the field insulating film 2, that is, a region where the gate electrode 4, the offset insulating film 5, and the sidewall spacer 6 are formed, is excluded. The liner layer 9 thus formed is referred to as a liner layer α region 10. Diffusion layer 7
Layer 9 formed only on the region excluding the silicide layer 8 and the field insulating film 2 having a lower layer, ie, the region where the gate electrode 4, the offset insulating film 5, and the sidewall spacer 6 are formed. The liner layer β
Region 11 is assumed.

The interlayer insulating film 12 is formed of a Si oxide film. When forming the contact holes 13 and 14, first, the S of the interlayer insulating film 12 is formed by first etching.
An opening is formed by etching the i-oxide film, and an opening is formed by etching the SiN film of the liner layer 9 by the second etching. Note that a detailed method of forming the contact holes 13 and 14 will be described later as a method of forming the contact holes 51 and 52 in the third embodiment.

The liner layer α region 10 has the contact hole 1
3 and the contact hole 14, the interlayer insulating film 12
Serves as an etching stopper film at the time of the first etching for removing a part of. Therefore, the liner layer α region 10
Indicates that the interlayer insulating film 12 (Si oxide film) and the liner layer 9 (S
iN film) and the interlayer insulating film 12
, That is, a film thickness necessary and sufficient to stop the first etching for removing the interlayer insulating film 12 in the liner layer α region 10. Thereafter, in the second etching, the SiN film remaining on the contact bottom after the first etching is removed, and the contact holes 13 and 14 are formed. With this configuration, the contact hole 14 does not break through the field insulating film 2 due to over-etching and does not reach the substrate.

The liner layer β region 11 has a contact hole 1
3 and the contact hole 14, the interlayer insulating film 12
Serves as an etching stopper film at the time of the first etching for removing a part of. Therefore, the liner layer β region 11
Indicates that the interlayer insulating film 12 (Si oxide film) and the liner layer 9 (S
iN film) and the interlayer insulating film 12
, That is, a film thickness necessary and sufficient to stop the first etching for removing the interlayer insulating film 12 in the liner layer β region 11. Thereafter, in the second etching, the SiN film left in the middle portion of the contact side wall after the first etching is removed, and the contact holes 13 and 14 are formed. With such a configuration, the contact hole 13 is formed by over-etching so that the Si substrate 1 immediately below the sidewall spacer 6 is formed.
Will not be reached.

Further, when the misalignment becomes larger and the contact hole 13 runs over the gate electrode 4, the offset insulating film 5 and the side wall spacer 6
Prevents a short circuit between the adhesion layer 15 and the gate electrode 4. As described above, the contact hole 13 and the contact hole 14 are formed without a margin for alignment between the gate electrode 4 and the field insulating film 2.
Is composed.

The interlayer insulating film 12 formed of a Si oxide film is
The silicide layer 8 and the gate electrode 4 are prevented from contacting the wiring layer 17 to prevent the MOS transistor from impairing its function.

The contact holes 13 and 14 are contact holes for connecting the silicide layer 8 and the upper wiring layer 17. That is, the contact holes 13 and 14
Is formed to fill the adhesion layer 15 and the W plug 16 to electrically connect the diffusion layer 7 of the source / drain of the MOS transistor and the wiring layer 17. Contact hole 13
Is a contact hole (SAC) provided in the space between the gate electrodes 4. The opening width (effective opening width) G at the bottom of the contact hole 13 is substantially the same as the width C-2x of the silicide layer 8 formed thereunder. The contact hole 14 is a contact hole (SAC / BL) provided in a space between the gate electrode 4 and the field insulating film 2.
C) is a one-sided SAC BLC. Contact hole 14
The opening width (effective opening width) H on the surface of the silicide layer 8 at the bottom is substantially the same as the width Ex of the silicide layer 8 formed thereunder. In FIG. 1, the dimensions of A, B, C, E, and x in the conventional example (FIG. 23) are shown, and the effective opening widths of the contact holes 13 and 14 are shown in FIG. 112, the distance between the gate electrode centers is A-2x in FIG.
(A in the related art), the distance between the center of the field insulating film and the gate electrode becomes Bx (B in the related art), and each is shorter than that in the conventional example.

The adhesion layer 15 is an adhesion layer formed of a conductive film also serving as a barrier metal.
It is composed of a laminated film of a Ti layer formed by magnetron sputtering and a TiN layer formed by MO-CVD. The adhesion layer 15 is provided to reduce the contact resistance between the silicide layer 8 and the W plug 16. Further, at the time of growing the blanket W by plasma CVD at the time of forming the W plug 16, the blanket W film is prevented from peeling off, and the WF is formed at the time of growing the blanket W.
₆ is provided to prevent the gas from reacting with the silicide layer 8. The adhesion layer 15 may be made of any material as long as the above-described effects can be obtained.

In this embodiment, the W plug 16 fills the inside of the contact holes 13 and 14 by the growth of the blanket W by plasma CVD and the etch back thereof. The W plug 16 includes the silicide layer 8 and the wiring layer 1
7 is provided to reduce the resistance.

In this embodiment, the wiring layer 17 is composed of a Ti layer formed by DC magnetron sputtering, a TiN layer formed by reactive sputtering, and an Al layer formed by DC magnetron sputtering.
A multilayer conductive film composed of an alloy layer and a TiN layer formed by reactive sputtering. The wiring layer 17 is provided for electrically connecting semiconductor devices such as a plurality of MOS transistors formed on the Si substrate 1.

As described above, in the first embodiment of the present invention, the liner layer 9 is formed only on the liner layer α region 10 and the liner layer β region 11 in the direction parallel to the substrate surface of the Si substrate 1. The gate electrode 4 and the offset insulating film 5
Are not formed between the side surfaces of the sidewall spacers 6 formed on the side walls of the first and second layers and the interlayer insulating film 12, and the side surfaces of the sidewall spacers 6 and the interlayer insulating film 12 are in contact with each other. Thereby, in the contact hole 13 (SAC),
When the silicide layer 8 thereunder has a width of C-2x, a contact hole 13 having an effective opening width G substantially equal to the length of C-2x can be opened. Further, the contact hole 14 (SA
In C / BLC), when the silicide layer 8 thereunder has a width of Ex, a contact hole 14 having an effective opening width H of substantially the same length as Ex can be opened. Therefore, the contact area between the silicide layer 8 and the adhesion layer 15 (silicide layer) does not occur, as shown in the conventional example, with no loss of 2 × interval in the contact hole 111 and no loss of x interval in the contact hole 112. If there is no diffusion layer 8, the diffusion layer 7 and the adhesion layer 15
Area in contact with the substrate) does not decrease. Therefore, an increase in contact resistance due to a decrease in the contact area is prevented, and a contact failure is prevented, so that the yield of the semiconductor device does not decrease.

Further, the effective opening widths G and H of the contact holes 13 and 14 are set to be smaller than those of the conventional contact holes 111 and 112.
In FIG. 1, the distance between the gate electrode centers is A
-2x (conventionally A), and the distance between the field insulating film and the gate electrode center becomes Bx (conventionally B), which can be shorter than the conventional example, and can greatly contribute to the improvement of the degree of integration. .

Since the gap (interval G) between adjacent gate electrodes 4 before the formation of the interlayer insulating film 12 is not affected by the thickness of the liner layer 9, the gaps between the liner layer α region 10 and the liner layer β region 11 It is not reduced according to the required film thickness. Thereby, a sharp increase in the aspect ratio of the gap between the gate electrodes 4 can be prevented, and a sufficient space for filling the Si oxide film constituting the interlayer insulating film 12 can be secured. Further, since the gap between the adjacent gate electrodes 4 before the formation of the interlayer insulating film 12 can be kept wide, the interlayer insulating film 12 (Si oxide film) can be compared with the liner layer 9 (SiN film) after the formation of the interlayer insulating film 12. 1) The first etching for removing the Si oxide film under the condition that the etching rate is sufficiently high can be performed more easily.

Further, even if the distance between the gate electrodes 4 is reduced by miniaturization in the horizontal direction with respect to the substrate surface, the gap (G) between the gate electrodes 4 is not affected by the thickness of the liner layer 9. The gap (G) between the gate electrodes 4 does not fill with the liner layer 9. Accordingly, the film thickness of the liner layer α region 10 and the liner layer β region 11 can be determined by the difference between the etching rates of the Si oxide film and the SiN film and the thickness of the interlayer insulating film 12 without being restricted by the increase in the film thickness. The determined necessary and sufficient thickness can be formed on the offset insulating film 5, the silicide layer 8, and the field insulating film 2.

Also, the first etching for opening the contact holes 13 and 14 can be stopped by the liner layer 9, so that the sidewall spacer 6 can be formed of a Si oxide film. In order to prevent problems such as variations in characteristics of the MOS transistor due to being covered with the liner layer 9 and a decrease in reliability due to the occurrence of interface order, a complicated sidewall structure and its realization are realized. No additional steps are required.

The liner layer 9 is not formed on the side wall of the sidewall spacer 6. Thereby,
Since the gate oxide film 3 and the gate electrode 4 of the MOS transistor in which the characteristic variation becomes a problem are not entirely covered with the liner layer 9, hydrogen can pass through and the wiring layer 17 can be formed.
The properties are restored by heat treatment in an atmosphere containing hydrogen after formation,
It is possible to prevent problems such as a change in the characteristics of the MOS transistor and a decrease in reliability due to the occurrence of an interface order.

The liner layer 9 is not limited to the SiN film, but may be any material that can provide a high etching selectivity with respect to the Si oxide film forming the interlayer insulating film 12. For example, a SiON film or a metal oxide film of Co, Al or the like can be used instead. When a metal oxide film such as Co or Al is used, the liner layer 9 can be made thinner.

[Second Embodiment] A second embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment of the present invention, wherein 21 is a Si substrate as a semiconductor substrate, 22 is a field insulating film, 23 is a gate oxide film (gate insulating film) of a MOS transistor, 24 is a gate electrode of a MOS transistor, 25 is an offset insulating film (first insulating film), 26
Is a sidewall spacer (sidewall insulating film), and 27 is an MO
A diffusion layer forming the source / drain of the S transistor;
28 is a silicide layer, 29 is a first liner layer (lower insulating film), 30 is a first liner layer α region, 31 is a first liner layer β region, 32 is a second liner layer (second insulating film),
33 is a second liner layer α region, 34 is a second liner layer β
Region, 35 is an interlayer insulating film, 36 is a contact hole (SAC) as an opening, and 37 is a contact hole (SAC) as an opening.
AC / BLC), 38 is an adhesion layer, 39 is a W plug, 40
Is a wiring layer.

The Si substrate 21, the field insulating film 22, the gate oxide film 23, the gate electrode 24, the offset insulating film 2
5, side wall spacer 26, diffusion layer 27 constituting source / drain, silicide layer 28, interlayer insulating film 3
5, contact hole (SAC) 36, contact hole (SA)
C / BLC) 37, the adhesion layer 38, the W plug 39, and the wiring layer 40 are the Si substrate 1, the field insulating film 2, the gate oxide film 3, the gate electrode 4, the offset insulating film 5, and the Si substrate in the first embodiment, respectively. Sidewall spacer 6,
Same as the diffusion layer 7, the silicide layer 8, the interlayer insulating film 12, the contact hole (SAC) 13, the contact hole (SAC / BLC) 14, the adhesion layer 15, the W plug 16, and the wiring layer 17 constituting the source / drain. , And a detailed description is omitted.

In the second embodiment, a first liner layer 29 is used instead of the liner layer 9 in the first embodiment.
The second embodiment differs from the first embodiment in that a second liner layer 32 is provided, and the other configurations are the same. Hereinafter, differences from the first embodiment will be described in detail.

The first liner layer 29 is formed of a Si oxide film. Here, for the sake of explanation, the upper surface of the silicide layer 28 having the diffusion layer 27 as a lower layer and the field insulating film 22
The first liner layer 29 formed on the first liner layer α except for the region where the offset insulating film 25 and the sidewall spacer 26 are formed.
Region 30 is assumed. In addition, it is formed only on the region excluding the upper surface of the silicide layer 28 having the diffusion layer 27 as the lower layer and the upper surface of the field insulating film 22, that is, the region where the offset insulating film 25 and the sidewall spacer 26 are formed. The first liner layer 29 is a first liner layer β region 31.

The second liner layer 32 is formed of a SiN film. Here, for the sake of explanation, on the silicide layer 28 having the diffusion layer 27 as a lower layer and on the field insulating film 22, that is, except for the region where the offset insulating film 25 and the sidewall spacer 26 are formed, The formed second liner layer 32 is used as a second liner layer α region 33. In addition, it is formed only on the region excluding the upper surface of the silicide layer 28 having the diffusion layer 27 as a lower layer and the upper surface of the field insulating film 22, that is, the region where the offset insulating film 25 and the sidewall spacer 26 are formed. The second liner layer 32 is replaced with the second liner layer β region 3
4 is assumed.

The interlayer insulating film 35 is formed of a Si oxide film. When forming the contact holes 36 and 37, first, the S of the interlayer insulating film 35 is formed by first etching.
An opening is formed by etching the i-oxide film, and the SiN film of the second liner layer 32 and the first
The Si oxide film of the liner layer 29 is opened by etching. A detailed method of forming the contact holes 36 and 37 will be described later as a method of forming the contact holes 86 and 87 in the fourth embodiment.

The first liner layer α region 30 reduces the influence of the stress of the second liner layer α region 33 on the silicide layer 28.

The first liner layer β region 31 has an end (Y portion) on the side wall spacer 26 in an overhang shape, and the second liner layer 32 is formed on the side wall of the side wall spacer 26. Work not to be.

The second liner layer α region 33 functions as an etching stopper film at the time of the first etching for removing the interlayer insulating film 35 when the contact holes 36 and the contact holes 37 are formed. Therefore, the second liner layer α region 3
3 is a film thickness determined by the difference between the etching rates of the interlayer insulating film 35 (Si oxide film) and the second liner layer 32 (SiN film) and the thickness of the interlayer insulating film 35, that is, the second liner layer α. The region 33 has a film thickness necessary and sufficient to stop the first etching for removing the interlayer insulating film 35. Thereafter, in the second etching, the SiN film (second liner layer 32) and the Si oxide film (first liner layer 29) remaining on the contact bottom after the first etching are removed, and the contact holes 36 and 37 are formed. Form.
With such a configuration, the contact hole 37 does not break through the field insulating film 22 due to over-etching and does not reach the substrate.

The second liner layer β region 34 functions as an etching stopper film at the time of the first etching for removing the interlayer insulating film 35 when forming the contact holes 36 and the contact holes 37. Therefore, the second liner layer β region 3
Reference numeral 4 denotes a thickness determined by the difference between the etching rates of the Si oxide film and the SiN film and the thickness of the interlayer insulating film 35, that is, the first etching for removing the interlayer insulating film 35 in the second liner layer β region 34. Is formed with a film thickness necessary and sufficient to stop the process. After that, in the second etching, the SiN film (second liner layer 32) remaining in the middle part of the contact side wall after the first etching is removed, and the contact hole 36 is formed.
And a contact hole 37 are formed. With such a configuration, the contact hole 3 is formed by over-etching.
6 is the Si substrate 21 immediately below the sidewall spacer 26
Will not be reached.

Further, when the misalignment is further increased and the contact hole 36 runs over the gate electrode 24, the offset insulating film 25 and the side wall spacer 2
6 prevents a short circuit between the adhesion layer 38 and the gate electrode 24.
As described above, the contact hole 36 and the contact hole 37 are formed without a margin for alignment between the gate electrode 24 and the field insulating film 22.

As described above, in the second embodiment of the present invention, instead of the liner layer 9 in the first embodiment, the first liner layer 29 (Si oxide film) and the second liner layer 32 ( (For example, a SiN film), and the same effects as in the first embodiment can be obtained.

That is, the first liner layer 29 and the second liner layer 32 are composed of the first liner layer α region 30, the first liner layer β region 31, and the second liner layer It is formed only in the α region 33 and the second liner layer β region 34, and is formed between the side surface of the side wall spacer 26 formed on the side wall of the gate electrode 24 and the offset insulating film 25 and the interlayer insulating film 35. The side surface of the sidewall spacer 26 and the interlayer insulating film 3
5 is in contact. Thereby, the contact hole 36
(SAC), the underlying silicide layer 28 has C-2x
, A contact hole 36 having an effective opening width I substantially equal to the length of C-2x can be opened. Further, in the contact hole 37 (SAC / BLC), when the silicide layer 28 below has a width of Ex, a contact hole 37 having an effective opening width J substantially the same length as Ex can be opened. Therefore, as shown in the conventional example, the loss of the contact hole 111 at the interval of 2x and the loss of the contact hole 112 at the interval of x do not occur.
Area (the contact area between the diffusion layer 27 and the adhesion layer 38 when there is no silicide layer 28) does not decrease. Therefore, it is possible to prevent an increase in the contact resistance due to a decrease in the contact area, and thus prevent a contact failure,
The yield of semiconductor devices does not decrease.

Further, the effective opening widths I and J of the contact holes 36 and 37 are changed to the contact holes 111 and 112 in the conventional example.
In FIG. 2, the distance between the center of the gate electrode is A
-2x (conventionally A), and the distance between the field insulating film and the gate electrode center becomes Bx (conventionally B), which can be shorter than the conventional example, and can greatly contribute to the improvement of the degree of integration. .

Since the gap (interval I) between adjacent gate electrodes 24 before the formation of the interlayer insulating film 35 is not affected by the second liner layer 32, the second liner layer α region 33 and the second liner layer
It is not reduced according to the required film thickness of the liner layer β region 34. Thereby, a sharp increase in the aspect ratio of the gap between the gate electrodes 24 can be prevented, and a sufficient space for filling the Si oxide film constituting the interlayer insulating film 35 can be secured.
Further, since the gap between the adjacent gate electrodes 24 before the formation of the interlayer insulating film 35 can be kept wide, the interlayer insulating film 35 (Si Oxide film) The first etching for removing the Si oxide film under the condition that the etching rate is sufficiently high can be performed more easily.

Further, even if the distance between the gate electrodes 24 is reduced by miniaturization in the horizontal direction with respect to the substrate surface, the gap (I) between the gate electrodes 24 is reduced by the first and second liner layers 29 and 32.
The gap (I) of the gate electrode 24 is not buried by the liner layers 29 and 32 because it is not affected by the film thickness of the gate electrode 24. As a result, the thicknesses of the liner layer α region 33 and the liner layer β region 34 of the second liner layer 29 can be determined without any restriction on the film thickness due to the difference in the etching rate between the Si oxide film and the SiN film and the interlayer thickness. A necessary and sufficient thickness determined by the thickness of the insulating film 12 is set to the offset insulating film 25,
It can be formed on the silicide layer 28 and the field insulating film 22.

Further, the first etching for opening the contact hole 36 and the contact hole 37 can be stopped by the second liner layer 32, so that the sidewall spacer 26 can be formed of a Si oxide film. Due to the effect of being covered with the second liner layer 32, M
In order to prevent problems such as a change in the characteristics of the OS transistor and a decrease in reliability due to the occurrence of an interface order, a complicated sidewall spacer structure and a process for realizing the same are not required.

The second liner layer 32 is not formed on the side wall of the side wall spacer 26. As a result, the gate oxide film 23 and the gate electrode 24 of the MOS transistor in which the characteristic variation becomes a problem become the second liner layer 3
2, the entire surface is not covered with hydrogen, so that hydrogen can pass therethrough, and the characteristics can be recovered by heat treatment in an atmosphere containing hydrogen after the formation of the wiring layer 40, and the reliability of the MOS transistor can be changed due to the characteristic fluctuation and the occurrence of interface order. Problems such as a decrease in image quality can be prevented.

Further, as in the second embodiment, the liner layer is formed of the first liner layer 29 (Si oxide film) and the second liner layer.
The first liner layer 29 can reduce the influence of the stress of the second liner layer 32 on the silicide layer 28 by using a two-layer film with the liner layer 32 (SiN film). When the silicide layer 28 is not formed, the first liner layer 29 is
The effect of stress on the liner layer 32 can be reduced. Even in the case where the liner layer is formed of a two-layer film in this manner, in this embodiment, the liner layer is thickened, the gap between the gate electrodes 24 is reduced, and the aspect ratio is excessively increased. Since the problem that the insulating film 35 (Si oxide film) cannot be filled and the gap between the gate electrodes 24 is formed only by forming the liner layer, that is, the problem that the gap is filled with only the etching stopper film, do not occur. Becomes possible.

The second liner layer 32 is not limited to the SiN film, but may be made of any material that can increase the etching selectivity with respect to the Si oxide film forming the interlayer insulating film 35. For example, a SiON film or a metal oxide film of Co, Al or the like can be used instead. When a metal oxide film such as Co or Al is used, the second liner layer 32 can be made thinner.

[Third Embodiment] A third embodiment of the present invention will be described below with reference to the drawings. 3 to 11 are process cross-sectional views illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Reference numeral 41 denotes a Si substrate (semiconductor substrate); 42, a field insulating film; A gate electrode film, 44 a gate electrode, 45 an offset insulating film (first insulating film), 46 a sidewall spacer (sidewall insulating film),
47 is a diffusion layer, 48 is a silicide layer, 49 is a liner layer (second insulating film), 50 is an interlayer insulating film, 51 is a contact hole (SAC), 52 is a contact hole (SAC / BL).
C) and 53 are adhesion layers, 54 is a W plug, and 55 is a wiring layer.

First, the step of FIG. 3 will be described. In this embodiment, a p-type Si substrate 41 is used, a 10-nm-thick Si oxide film is formed on this Si substrate 41 by thermal oxidation, and a 100-nm-thick film is formed thereon by low-pressure CVD.
Is formed. Further, after forming a resist pattern for forming the field insulating film 42 by the reduced projection exposure technique, the SiN film, the Si oxide film, and the Si substrate 41 are subjected to an etching process by anisotropic dry etching,
A groove having a depth of 300 nm is formed in the i-substrate 41. Furthermore,
After removing and cleaning the resist pattern, the Si substrate 4
The groove formed in 1 is filled with a Si oxide film by using a plasma CVD method, and is polished to a SiN film by a CMP method to flatten the surface. Further, the SiN film is removed by etching using a phosphoric acid solution heated to about 130 ° C. As described above, the field insulating film 42 for electrically separating each element is formed. By the field insulating film 42, both ends of the groove can be electrically separated, and an independent potential can be given.

Further, an n-type MOS transistor is formed later.
In this case, accelerate B ions to form p-type wells.
Energy is 400 keV, injection amount is 1 × 10¹³cm
^-2And for channel stop to improve separation withstand voltage
The acceleration energy of B ions is 180 keV and the implantation amount is 6
× 10¹²cm^-2Threshold control of MOS transistor
For B ions, the acceleration energy is 20 keV, the implantation dose
Is 6 × 10¹²cm^-2Ion implantation is performed to the extent. Also,
When forming a p-type MOS transistor, an n-type MOS transistor is used.
Acceleration energy of 700 ions for P ions for L formation
V, injection amount is 1 × 10 ¹³cm^-2Improves the breakdown voltage
Energy to accelerate P ions for channel stop
Is 250 keV and the injection amount is 6 × 10¹²cm^-2And MOS
Accelerate As ions for controlling the threshold of the transistor.
Energy is 40 keV, injection amount is 6 × 10¹²cm^-2degree
Then, ion implantation is performed. Then, the temperature is increased in a nitrogen atmosphere.
Heat treatment at 1000 ° C for 10 seconds
The implanted impurities are activated.

Subsequently, after removing the Si oxide film remaining on the Si substrate 41 on which the field insulating film 42 has been formed by using a diluted hydrofluoric acid solution, thermal oxidation in a mixed atmosphere of O ₂ and H ₂ is performed. To form a 3 nm thick Si oxide film,
A gate oxide film 43 of the MOS transistor is formed. The gate oxide film 43 is formed of an Si oxide film using RTP technology or N
_It may be formed of an oxynitride film formed in a gas phase containing ₂ O or NO.

Further, on the gate oxide film 43, a reduced pressure CV
D, a polysilicon film having a thickness of 100 nm is formed, and P
The gate electrode film 44a is formed by performing ion implantation and B ion implantation at a predetermined location to form a p-type gate electrode. The gate electrode film 44a may be formed as a two-layer film in which a polysilicon film having a thickness of 50 nm by low-pressure CVD and a WSix film having a thickness of 40 nm by plasma CVD or sputtering are stacked. Further, a polysilicon film having a thickness of 50 nm by low pressure CVD, a WNx film having a thickness of 10 nm by plasma CVD or sputtering, and a
Alternatively, it may be formed of a three-layer film in which a W film is stacked.

Further, in order to form the offset insulating film 45 on the gate electrode film 44a, a Si oxide film having a thickness of 120 nm is formed by low pressure CVD or plasma CVD. In addition,
The offset insulating film 45 is formed by low pressure CVD or plasma CVD.
May be formed using a SiN film. Further, a multilayer structure in which a Si oxide film and a SiN film are arbitrarily combined may be formed.

Further, after forming a resist pattern for forming the gate electrode 44 on the Si oxide film to be the offset insulating film 45 by the reduced projection exposure technique, the Si oxide film is formed by anisotropic dry etching using the resist pattern as a mask. Is etched to form an offset insulating film 45. At this time, the gate electrode film 4 other than the region of the offset insulating film 45 is formed.
The surface of 4a is exposed. Then, the resist pattern is removed and washed. The state at this point is shown in FIG.

Next, in the step of FIG. 4, the gate electrode film 44a is etched by anisotropic dry etching to form a final gate electrode 44 pattern. At this time, the offset insulating film 45 functions as an etching mask. As a result, the film thickness is reduced by about 10 nm.
m.

Next, the step of FIG. 5 will be described. n
In the case of a MOS transistor, in order to reduce the electric charge near the drain, an appropriate A
The acceleration energy of s ions is 30 keV and the implantation amount is 1 ×
In order to suppress the short channel effect of the MOS transistor at 10 ¹⁴ cm ^-2 , BF ₂ ions are implanted at an acceleration energy of 60 keV and a dose of 2 × 10 ¹³ cm ^-2 . Further, in the p-type MOS transistor, in order to reduce the electric charge near the drain, the BF ₂ ions are accelerated by 3 to improve the impurity profile.
0 keV, the implantation amount is 1 × 10 ¹⁴ cm ⁻² , and in order to suppress the short channel effect of the MOS transistor, P ions are accelerated at an acceleration energy of 60 keV and the implantation amount is 3 × 10 ¹⁴
Ion implantation is performed at ¹³ cm ^-2 . The above corresponds to the LDD injection and the pocket injection, which are conventionally well known, and is not shown.

Further, the thickness is reduced to 100 nm by low pressure CVD.
Is formed on the entire surface, and then the entire surface is etched back to form sidewall spacers 46 on the side walls of the gate electrode 44 and the like (the offset insulating film 45, the gate oxide film 43, etc.). At the time of full etch back,
In order not to leave an unnecessary Si oxide film on the Si substrate 41,
Perform some overetching. At this time, the offset insulating film 45 is reduced in thickness by about 10 nm, but the offset insulating film 45 having a thickness of about 100 nm is
4 so that the surface of the gate electrode 44 is not exposed during the above-described overall etch-back. The side wall spacer 46 is formed to reduce the electric charges near the drain of the MOS transistor and to make the impurity profile appropriate. At this time, it is assumed that the distance between the side wall spacers 46 formed on the side walls of two adjacent gate electrodes 44 is K.

Further, a diffusion layer 47 is formed by ion implantation.
I do. The ion implantation for forming the n-type diffusion layer is performed by A
The acceleration energy of s ions is 30 keV and the implantation amount is 2 ×
10 ¹⁵cm^-2Do with. i for forming a p-type diffusion layer
On injection is BF_TwoAcceleration energy for ions is 25 ke
V, injection amount 2 × 10¹⁵cm^-2Or B
Acceleration energy of ions is 5 keV, implantation dose is 2 × 10
¹⁵cm^-2Do with. Thereafter, the temperature is set to 100 in a nitrogen atmosphere.
Perform a heat treatment at 0 ° C. for 10 seconds, and perform ion implantation.
The activated impurities are activated. As described above, the MOS transistor
Diffusion layer 47 forming the source / drain of the transistor is formed.
I do. The state at this point is shown in FIG.

Next, the step of FIG. 6 will be described. In order to remove the natural oxide film on the diffusion layer 47, after wet treatment with diluted hydrofluoric acid, 8 nm of Co and 20 nm of TiN are deposited by DC magnetron sputtering. TiN deposited on the upper layer is provided to prevent Co from being oxidized in a later step. Thereafter, a heat treatment is performed in a N ₂ atmosphere at a temperature of 500 ° C. for a time of 60 seconds,
Co silicide is formed on the diffusion layer 47. Further, cleaning and etching of a mixed solution of sulfuric acid and hydrogen peroxide and cleaning and etching with a mixed solution of ammonia, hydrogen peroxide and water are performed to form the field insulating film 42, the offset insulating film 45, and the sidewall spacers. Co on 46 and TiN remaining on the entire surface are removed. Further, a heat treatment is performed at a temperature of 800 ° C. for 10 seconds in an N ₂ atmosphere,
The resistance of Co silicide is reduced. As described above, the silicide layer 48 is formed only on the diffusion layer 47 in a self-aligned manner. Note that the silicide layer 48 may be Ti silicide formed in a similar procedure. The silicide layer 48
It is provided to reduce the sheet resistance of the source / drain of the MOS transistor and to reduce the contact resistance with the adhesion layer 53 (FIG. 11). Thereby, the parasitic resistance of the MOS transistor is reduced, and the driving capability is improved.

Next, the step of FIG. 7 will be described. A liner layer 49 is formed on the field insulating film 42, on the silicide layer 48, on the offset insulating film 45, and directly above the sidewall spacer 46 (not to be formed on the side wall). The liner layer 49 is ideally formed using a film forming method in which the growth rate in the vertical direction with respect to the Si substrate 41 is high and the growth rate in the horizontal direction is zero. Using a Si target as the liner layer 49, Ar and N ₂
In the reactive sputtering by sputtering in the inside, the SiN film is formed so that the film thickness in the vertical direction becomes 50 nm, but the collimation sputtering method is used to suppress the growth in the horizontal direction and advance the growth in the vertical direction. . By providing a slit plate (collimation) having a specific aspect ratio (about 2) between the Si target and the Si substrate 41, SiN incident on the Si substrate 41 from an oblique direction is provided.
And suppresses horizontal growth. That is, the liner layer 49 is prevented from growing on the side wall of the 46 sidewall spacer. At this time, the interval between two adjacent side wall spacers 46 is
Due to the effect of the liner layer 49 slightly formed on the side wall (side surface) of the above, the interval becomes slightly smaller than K.

The liner layer 49 is not limited to the collimation sputtering method. The line between the Si target and the Si substrate 41 is made wider than usual to prevent the SiN incident on the Si substrate 41 from an oblique direction from reaching. It may be formed using a method such as a distance sputtering method.

The liner layer 49 is provided with a contact hole 5 described later.
1 and the contact hole 52, the interlayer insulating film 50
Is formed in advance to serve as an etching stopper film at the time of the first etching for opening the opening. Therefore, the liner layer 49 has a sufficient vertical thickness in the vertical direction to stop the first etching for removing the interlayer insulating film 50.

The liner layer 49 is not limited to the SiN film, but may be any material that can increase the etching selectivity with respect to the Si oxide film forming the interlayer insulating film 50. For example, a SiON film or a metal oxide film of Co, Al or the like can be used instead. In the case of the SiON film, the SiON film is formed so as to have a vertical thickness of 50 nm by reactive sputtering using an SiO ₂ target by sputtering in Ar and N _2. In order to suppress vertical growth and promote vertical growth, it can be formed using a collimation sputtering method. In the case of a metal oxide film of Co, Al, or the like, A
Each metal film is formed by sputtering in an atmosphere of r, and then subjected to an oxidizing treatment by heat treatment in oxygen or exposure to O ₂ plasma, etc.
It is formed so that it is about. A metal oxide film of Co, Al, or the like can obtain a higher etching selectivity with respect to a Si oxide film than a SiN film or a SiON film.

Next, in the step of FIG.
After formation, the thickness is 1500 nm by plasma CVD.
Is formed on the entire surface. This Si oxide film is formed under such a condition that a gap between two adjacent sidewall spacers 46 can be filled. Thereafter, the interlayer insulating film 50 is formed by performing planarization by CMP to finish the entire film thickness from the surface of the Si substrate 41 to 400 nm. The interlayer insulating film 50 prevents the silicide layer 48 and the gate electrode 44 from coming into contact with the wiring layer 55 (FIG. 11) to prevent the function of the MOS transistor from being impaired.

Next, in the step of FIG.
After the formation, a resist pattern for forming the contact holes 51 and 52 is formed on the interlayer insulating film 50 by a reduced projection exposure technique. Using this resist pattern as a mask, the interlayer insulating film 5 is formed by anisotropic dry etching under the condition that the etching rate of the interlayer insulating film 50 (Si oxide film) is sufficiently higher than that of the liner layer 49 (SiN film).
First etching for removing 0 (Si oxide film) is performed. At this time, as the etching of the contact hole 51 and the contact hole 52 proceeds, the Si of the liner layer 49 is formed on the bottom.
Although the N film is exposed, the etching rate of the SiN film is sufficiently low, so that the etching is temporarily stopped at the SiN film. In addition, since the first etching is performed under the condition of strong anisotropy,
Etching in the direction of the sidewall spacer 46 does not proceed.

After removing and cleaning the resist pattern for forming the contact holes 51 and 52, in the step of FIG. 10, the bottom of the contact holes 51 and 52 is formed by the step of FIG. The exposed liner layer 49 is removed, and second etching for exposing the surface of the silicide layer 48 is performed. The second etching is performed under the condition that the etching rates of the SiN film and the Si oxide film are substantially equal. Under these conditions, when etching proceeds in the lateral direction, no step is formed between the liner layer 49 (SiN film) and the interlayer insulating film 50 (Si oxide film). It is important to select a condition having strong anisotropy in the first etching, but strong anisotropy is not required in the second etching. It is better that the etching in the lateral direction proceeds to the extent that the bottoms of the contact holes 51 and 52 are aligned with the ends of the silicide layer 48. This can increase the contact area. However, it must not extend beyond the end of the silicide layer 48. That is,
A processing condition in which the interval is K and the contact hole 51 can be opened is selected. Therefore, the effective opening width of the contact hole 51 is K, which is almost the same as the width C-2x of the silicide layer 48 thereunder, and the effective opening width L of the contact hole 52 is equal to the width E− of the silicide layer 48 therebelow. It is almost the same as x.

The step of FIG. 11 will be described. A 20 nm-thick Ti layer and MO were deposited by DC magnetron sputtering.
Forming a 20 nm-thick TiN layer by CVD to form the adhesion layer 53; The adhesion layer 53 is provided to reduce the contact resistance between the silicide layer 48 and the W plug 54. Further, at the time of blanket W growth by plasma CVD at the time of forming the W plug 54, the blanket W film is prevented from peeling off, and WF _{6 is formed} at the time of blanket W growth.
It is provided to prevent a gas from reacting with the silicide layer 48. If the above-mentioned Ti layer is formed thicker at the bottoms of the contact holes 51 and 52, the contact resistance becomes more stable.
(Ion metal plasma) formed by using sputtering or the like. After forming the adhesion layer 53, the contact holes 51 and 52
Is filled with a W plug 54, so that the contact hole 51
It is not possible to select a film thickness that allows the opening of the contact hole 52 to be closed by the adhesion layer 53, so it is preferable to use a film forming method that grows more in the vertical direction with respect to the Si substrate 41.

Further, the surface of the Ti layer and the silicide layer 48 is alloyed by performing a heat treatment at a temperature of 600 ° C. and a time of 30 seconds in an N ₂ atmosphere to make the contact more dense and stabilize the contact resistance. At the same time, the deterioration of the TiN layer is promoted, so that the TiN layer is hardly etched by the WF ₆ gas when the blanket W is grown by the plasma CVD. As a result, even in the thinner TiN layer, the WF ₆ gas enters the diffusion layer 47 through the silicide layer 48 and
An increase in reverse current at the pn junction with the i-substrate 41 (well) can be prevented.

Further, the plasma CV
The blanket W is grown and etched back by D to fill the contact holes 51 and 52 with W, thereby forming a W plug 54. The W plug 54 is provided to reduce the resistance between the silicide layer 48 and the wiring layer 55.

Further, a Ti layer with a thickness of 10 nm by DC magnetron sputtering, a TiN layer with a thickness of 20 nm by reactive sputtering, an Al alloy layer with a thickness of 400 nm by DC magnetron sputtering, and a film by reactive sputtering A TiN layer having a thickness of 30 nm is laminated. A resist pattern for forming the wiring layer 55 is formed by the reduction projection exposure technique, and the wiring layer 5 is formed by RIE (Reactiveion etching) using the resist pattern as a mask.
5 is formed. The wiring layer 55 is formed for electrically connecting a plurality of semiconductor devices such as MOS transistors formed on the Si substrate 41. Although the present embodiment has been described using a material mainly containing an aluminum alloy, the wiring layer 55 may be formed using a material mainly containing W.

Then, after removing and cleaning the resist pattern for forming the wiring layer 55, a heat treatment is performed at 400 ° C. for 15 minutes in an atmosphere containing hydrogen, and various dry etchings are performed. And recover the damage done to the MOS transistor.

As described above, a semiconductor device similar to that of the first embodiment can be manufactured. The effect of the present invention does not change even if the silicide layer 48 is not formed.

The manufacturing method in the present embodiment is
Basically, it is a method for manufacturing the semiconductor device described in the first embodiment (FIG. 1). However, as can be seen by comparing FIG. 11 with FIG. 1, in FIG. 11, the liner layer 49 is formed between the side surface of the sidewall spacer 46 and the interlayer insulating film 50 by heat treatment in an atmosphere containing hydrogen. In this case, the liner layer is formed between the side surface of the sidewall spacer 6 and the interlayer insulating film 12 in FIG. 9 are not formed, and the sidewall spacer 6 and the interlayer insulating film 12 are in contact with each other. The configuration of FIG.
In the manufacturing method according to the present embodiment, the liner layer 4
9 shows a case in which the growth in the horizontal direction with respect to the substrate surface is completely suppressed when forming No. 9, which is the best configuration.

As described above, in the third embodiment of the present invention, the liner layer 49 is formed thick only in the direction perpendicular to the substrate surface of the Si substrate 41, and is formed on the side walls of the gate electrode 44 and the offset insulating film 45. Sidewall spacer 4
6 is hardly formed between the side surface 6 and the interlayer insulating film 50. Thereby, in the contact hole 51 (SAC), when the silicide layer 48 below has a width of C-2x, the contact hole 51 having an effective opening width K substantially equal to the length of C-2x can be opened. The contact hole 52
In (SAC / BLC), when the silicide layer 48 below has a width of Ex, a contact hole 52 having an effective opening width L substantially equal to the length of Ex can be opened. Therefore, as shown in the conventional example, two contact holes 111 are used.
The loss of the interval of x and the loss of the interval of x in the contact hole 112 do not occur.
Contact area (if there is no silicide layer 48, the diffusion layer 4
The contact area between the contact layer 7 and the contact layer 53 does not decrease.
Therefore, an increase in contact resistance due to a decrease in the contact area is prevented, and a contact failure is prevented, so that the yield of the semiconductor device does not decrease.

Further, the effective opening widths K and L of the contact holes 51 and 52 are set to be smaller than those of the conventional contact holes 111 and 112.
In this embodiment, the distance between the gate electrode centers is A-2x (A in the related art) and the distance between the field insulating film and the gate electrode center is Bx (B in the related art). It can be shortened, and can greatly contribute to the improvement of the degree of integration.

The gap (K) between the adjacent gate electrodes 44 before the formation of the interlayer insulating film 50 is hardly affected by the thickness of the liner layer 49, and is not reduced as much as the required thickness of the liner layer 49. This prevents a sharp increase in the aspect ratio of the gap (K) between the gate electrodes 44, and secures a sufficient space for filling the Si oxide film forming the interlayer insulating film 50. Further, since the gap (K) between the adjacent gate electrodes 44 before the formation of the interlayer insulating film 50 can be kept wide, the liner layer 49 (S
The first etching for removing the Si oxide film under the condition that the etching rate of the interlayer insulating film 50 (Si oxide film) is sufficiently higher than that of the (iN film) can be performed more easily.

Further, even if the distance between the gate electrodes 44 is reduced by miniaturization in the horizontal direction with respect to the substrate surface, the gap (K) between the gate electrodes 44 is not affected by the thickness of the liner layer 49 as it is. Since there is no gap, the gap (K) between the gate electrodes 44 is not filled with the liner layer 49.
Thus, the thickness of the liner layer 49 can be set to a necessary and sufficient thickness determined by the difference between the etching rates of the Si oxide film and the SiN film and the thickness of the interlayer insulating film 50 without being restricted by the increase in the thickness. , The offset insulating film 45, the silicide layer 48, and the field insulating film 42.

Further, the first etching for opening the contact holes 53 and 54 can be stopped by the liner layer 49, so that the sidewall spacers 46 can be formed of a Si oxide film. In order to prevent problems such as fluctuations in the characteristics of MOS transistors and a decrease in reliability due to the occurrence of interface order due to the effect of being covered with the liner layer 49, a complicated sidewall structure is realized. No process is required.

Further, even if the liner layer 49 is formed on the side wall of the sidewall spacer 46, its thickness is small.
Hydrogen can pass through. Thereby, the gate oxide film 43 of the MOS transistor in which the characteristic variation becomes a problem
The characteristics of the gate electrode 44 and the gate electrode 44 are restored by heat treatment in an atmosphere containing hydrogen after the formation of the wiring layer 55, so that problems such as a change in the characteristics of the MOS transistor and a decrease in reliability due to the occurrence of interface order do not occur. can do.

Even if a metal oxide film such as Co or Al is formed as the liner layer 49, the characteristics of the MOS transistor do not fluctuate. In this case, the thinner liner layer 49
Therefore, a method for manufacturing a semiconductor device which is more advantageous in all aspects can be obtained.

[Fourth Embodiment] Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. 12 to 20 are sectional views showing the steps of a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, in which 71 is a Si substrate (semiconductor substrate), 72 is a field insulating film, and 73 is a gate oxide film ( Gate insulating film), 74a is a gate electrode film, 7
4 is a gate electrode, 75 is an offset insulating film (first insulating film), 76 is a sidewall spacer (sidewall insulating film),
77 is a diffusion layer, 78 is a silicide layer, 79 is a first liner layer (lower insulating film), 80 is a first liner layer α region, 8
1 is a first liner layer β region, 82 is a second liner layer (second insulating film), 83 is a second liner layer α region, 84 is a second liner layer β region, 85 is an interlayer insulating film, 86 is a contact Hole (SAC), 87 is a contact hole (SAC / BL)
C), 88 is an adhesion layer, 89 is a W plug, and 90 is a wiring layer.

First, the steps of FIGS. 12 to 15 are exactly the same as the steps of FIGS. 3 to 6 in the third embodiment.
Detailed description is omitted. Briefly describing only those shown in the figure, in the process of FIG. 12, for example, a field insulating film 72 in which a groove having a depth of 300 nm is formed and a Si oxide film is filled in, for example, a p-type Si substrate 71 is formed. A gate oxide film 73 made of, for example, a 3 nm-thick Si oxide film;
For example, a gate electrode film 74a made of a polysilicon film into which impurities are ion-implanted and an offset insulating film 75 made of a Si oxide film, a SiN film, or a multilayer film obtained by arbitrarily combining them are formed. In the step of FIG. 13, the gate electrode 74 is formed by etching the gate electrode film 74a. In the step of FIG. 14, a sidewall spacer 76 made of a Si oxide film and a diffusion layer 77 constituting a source / drain are formed, and the distance between two adjacent sidewall spacers 76 at this time is set to M. And In the step of FIG. 15, a silicide layer 78 of Co silicide or Ti silicide is formed on the diffusion layer 77 in a self-aligned manner.

Next, the step of FIG. 16 will be described.
A first liner layer 79 is formed on the field insulating film 72, on the silicide layer 78, on the offset insulating film 75, and on the sidewall spacer 76 (not on the side wall). The growth rate of the first liner layer 79 in the direction perpendicular to the Si substrate 71 is ideally high,
The film is formed using a film formation method in which the growth rate in the horizontal direction becomes zero. The first liner layer 79, using the SiO ₂ target by sputtering in Ar, but the thickness in the vertical direction to form a SiO ₂ film so that 20 nm, vertically suppressed horizontal growth In order to promote the growth of
A collimation sputtering method is used. By providing a slit plate (collimation) having a specific aspect ratio (approximately 2) between the SiO ₂ target and the Si substrate 71, SiO ₂ incident on the Si substrate 71 from an oblique direction is provided.
And suppresses horizontal growth. That is, the first liner layer 7 is formed on the side wall of the sidewall spacer 76.
Make 9 hardly grow.

The first liner layer 79 is not limited to the collimation sputtering method. The distance between the SiO ₂ target and the Si substrate 71 is set wider than usual, and the SiO ₂ incident on the Si substrate 71 obliquely reaches the first liner layer 79. It may be formed by using a method such as a long-distance sputtering method that prevents the occurrence of the problem.

Next, a second liner layer 82 is formed on the first liner layer 79. The second liner layer 82 is ideally formed using a film forming method in which the growth rate in the vertical direction with respect to the Si substrate 71 is high and the growth rate in the horizontal direction is zero. The second liner layer 82 is formed by performing a reactive sputtering in Ar and N ₂ using a Si target so that the vertical thickness becomes 40 nm. To promote vertical growth, a collimation sputtering method is used. Between the Si target and the Si substrate 71, a specific aspect ratio (2
Is provided on the Si substrate 71 in an oblique direction by providing a slit plate (collimation) having
Exclude N and suppress horizontal growth. That is, the second liner layer 82 is prevented from growing on the side wall of the sidewall spacer 76.

The second liner layer 82 is formed not only by the collimation sputtering method but also by the Si target and the Si substrate 7.
1 may be formed wider than usual, and a method such as a long-distance sputtering method may be used to prevent SiN incident on the Si substrate 71 from an oblique direction from reaching.

Here, for the sake of explanation, the upper surface of the silicide layer 78 having the diffusion layer 77 as the lower layer and the field insulating film 72
, That is, excluding the regions where the offset insulating film 75 and the sidewall spacers 76 are formed, the first liner layer 79 and the second liner layer 82
Are referred to as a first liner layer α region 80 and a second liner layer α region 83, respectively. In addition, it is formed only on the region excluding the upper surface of the silicide layer 78 having the diffusion layer 77 as a lower layer and the upper surface of the field insulating film 72, that is, the region where the offset insulating film 75 and the sidewall spacer 76 are formed. First liner layer 79, second liner layer 82
Are referred to as a first liner layer β region 81 and a second liner layer β region 84, respectively.

The first liner layer α region 80 is formed to reduce the influence of the stress of the second liner layer α region 83 on the silicide layer 78.

The first liner layer β region 81 has an end portion on the side wall spacer 76 formed in an overhanging shape. In order to prevent the second liner layer 82 from being formed on the side wall of the side wall spacer 76. Form. In some cases, the first liner layer 79 is formed thin on the side wall of the sidewall spacer 76, but by forming the end on the sidewall spacer 76 into an overhang shape, the second liner layer 82 It is not formed on the side wall of the wall spacer 76.

The second liner layer α region 83 functions as an etching stopper film at the time of the first etching for removing the interlayer insulating film 85 when forming a contact hole 86 and a contact hole 87 described later. Therefore, the second liner layer α
The region 83 has a difference in etching rate between the interlayer insulating film 85 (Si oxide film) and the second liner layer 82 (SiN film),
The thickness determined by the thickness of the interlayer insulating film 85, that is,
A film thickness necessary and sufficient to stop the first etching for removing the interlayer insulating film 85 in the second liner layer α region 83 is formed. After that, in the second etching, the SiN film remaining on the contact bottom after the first etching is removed, and a contact hole 86 and a contact hole 87 are formed.
With this configuration, the contact hole 87 does not break through the field insulating film 72 due to over-etching and does not reach the substrate.

The second liner layer β region 84 functions as an etching stopper film in the first etching for removing the interlayer insulating film 85 when forming the contact holes 86 and 87. Therefore, the second liner layer β region 8
Reference numeral 4 denotes a thickness determined by the difference between the etching rates of the Si oxide film and the SiN film and the thickness of the interlayer insulating film 85, that is, the first etching for removing the interlayer insulating film 85 in the second liner layer β region 84. Is formed to have a film thickness necessary and sufficient to stop the process. After that, in the second etching, SiN left in the middle portion of the contact side wall after the first etching
The film is removed, and a contact hole 86 and a contact hole 87 are formed. With such a configuration, the contact hole 86 does not reach the Si substrate 71 immediately below the sidewall spacer 76 due to over-etching.

Further, when the misalignment becomes larger and the contact hole 86 runs over the gate electrode 74, the offset insulating film 75 and the side wall spacer 7
6 prevents a short circuit between the adhesion layer 88 and the gate electrode 74.

The second liner layer 82 is not limited to the SiN film, but may be made of any material that can provide a high etching selectivity to the Si oxide film forming the interlayer insulating film 85. For example, a SiON film or a metal oxide film of Co, Al or the like can be used instead. In the case of a SiON film, an SiON film is formed by reactive sputtering by sputtering in Ar and N ₂ using an SiO ₂ target so that the film thickness in the direction perpendicular to the substrate surface becomes 40 nm. In order to suppress growth in the horizontal direction and promote growth in the vertical direction, it can be formed using a collimation sputtering method. Also, C
In the case of a metal oxide film of o, Al or the like, each metal film is formed by sputtering in Ar using each metal target, and thereafter, a heat treatment in oxygen or O 2
_{(2) An} oxidation treatment is performed by exposing to plasma, etc., so that the film thickness in the vertical direction is about 30 nm. Co, A
The metal oxide film such as 1 can obtain a higher etching selectivity with respect to the Si oxide film of the interlayer insulating film 85 than the SiN film or the SiON film.

Next, the step of FIG. 17 is the same as the step of FIG. 8 in the third embodiment, and the second liner layer 8
2 after formation, the thickness is 1500 n by plasma CVD.
An m-Si oxide film is formed on the entire surface. At this time, the Si oxide film is formed in a gap between two adjacent sidewall spacers 76.
Perform under conditions that allow filling. After that, planarization by CMP is performed so that the entire film thickness from the surface of the Si substrate 71 is 400 n.
m, an interlayer insulating film 85 is formed. When the silicide layer 78 and the gate electrode 74 are in contact with the wiring layer 90 (FIG. 20),
The transistor is prevented from impairing its function.

Next, in the step of FIG. 18, the interlayer insulating film 8
5 are formed, and the contact holes 8 are formed by a reduced projection exposure technique.
6 and a resist pattern for forming the contact hole 87 are formed. Using this resist pattern as a mask,
Compared to the second liner layer 82 (SiN film), the interlayer insulating film 8
First etching for removing the interlayer insulating film 85 (Si oxide film) is performed by anisotropic dry etching under the condition that the etching rate of 5 (Si oxide film) is sufficiently high. At this time,
As the etching of the contact holes 86 and 87 proceeds, the second liner layer 82 is exposed at the bottom.
Since the etching rate of the SiN film of the second liner layer 82 is sufficiently low, the etching is temporarily stopped at the SiN film.
Further, since the first etching is performed under the condition that the anisotropy is strong, the etching in the direction of the sidewall spacer 76 does not progress.

After removing and cleaning the resist pattern for forming the contact holes 86 and 87, in the step of FIG. 19, the bottom of the contact holes 86 and 87 is formed by the step of FIG. Exposed second
The liner layer 82 (SiN film) and the underlying first liner layer 79 (Si oxide film) are removed, and a second etching for exposing the surface of the silicide layer 78 is performed. Second
Is performed under the condition that the etching rates of the SiN film and the Si oxide film are substantially equal. It is important to select a condition having strong anisotropy in the first etching, but strong anisotropy is not required in the second etching. It is preferable that the etching in the lateral direction proceeds to the extent that the bottoms of the contact holes 86 and 87 are aligned with the ends of the silicide layer 78. This can increase the contact area. However, it must not extend beyond the end of the silicide layer 78. That is, a processing condition that allows the contact hole 86 to be opened at the interval M is selected. Therefore, the effective opening width of the contact hole 86 is M, and the silicide layer
8, the effective opening width N of the contact hole 87 is equal to the width Ex of the silicide layer 48 therebelow.
Is almost the same as

Since the step of FIG. 20 is the same as the step of FIG. 11 in the third embodiment, a detailed description will be omitted. As in the third embodiment, the contact holes 86
A contact layer 88 is formed in the contact hole 87 and
The plug 89 is filled. Next, a wiring layer 90 is formed,
Thereafter, a heat treatment is performed to recover the damage applied to the MOS transistor by various dry etchings.

As described above, a semiconductor device similar to that of the second embodiment can be manufactured. The effect of the present invention does not change even if the silicide layer 78 is not formed.

As described above, in the fourth embodiment of the present invention, instead of the liner layer 49 in the third embodiment, the first liner layer 79 (Si oxide film) and the second liner layer 82 ( (E.g., a SiN film).
The same effects as in the third embodiment can be obtained. That is,
The first liner layer 79 and the second liner layer 82 are formed thick only in the direction perpendicular to the substrate surface of the Si substrate 21, and the side surfaces of the sidewall spacer 76 formed on the side walls of the gate electrode 74 and the offset insulating film 75. And interlayer insulating film 85
Is hardly formed between Thereby, in the contact hole 86 (SAC), the silicide layer 7 thereunder is formed.
8 has a width of C-2x, a contact hole 86 having an effective opening width M substantially the same length as C-2x can be opened. In the contact hole 87 (SAC / BLC),
When the silicide layer 78 thereunder has a width of Ex, a contact hole 87 having an effective opening width N substantially the same length as Ex can be opened. Therefore, the contact area between the silicide layer 78 and the adhesion layer 88 (the silicide layer) does not occur, as shown in the conventional example, with no loss of 2 × interval in the contact hole 111 and no loss of x interval in the contact hole 112. In the case where there is no 78, the contact area between the diffusion layer 77 and the adhesion layer 88) does not decrease. Therefore, an increase in contact resistance due to a decrease in the contact area is prevented, and a contact failure is prevented, so that the yield of the semiconductor device does not decrease.

Further, the effective opening widths M and N of the contact holes 86 and 87 are set to be smaller than those of the conventional contact holes 111 and 112.
In this embodiment, the distance between the gate electrode centers is A-2x (A in the related art) and the distance between the field insulating film and the gate electrode center is Bx (B in the related art). It can be shortened, and can greatly contribute to the improvement of the degree of integration.

Since the gap (M) between the adjacent gate electrodes 74 before the formation of the interlayer insulating film 85 is not affected by the second liner layer 82, the gap (M) is not reduced as much as the required thickness of the second liner layer 82. Thereby, a sharp increase in the aspect ratio of the gap between the gate electrodes 74 can be prevented, and a sufficient space for filling the Si oxide film constituting the interlayer insulating film 85 can be secured. Since the gap (M) between the adjacent gate electrodes 74 before the formation of the interlayer insulating film 85 can be kept wide, the second liner layer 82 (SiN film) after the formation of the interlayer insulating film 85 can be maintained.
The first step of removing the Si oxide film under the condition that the etching rate of the interlayer insulating film 85 (Si oxide film) is sufficiently higher than that of the first embodiment.
Can be more easily etched.

Further, even if the distance between the gate electrodes 74 is reduced by miniaturization in the horizontal direction with respect to the substrate surface, the gap (M) between the gate electrodes 74 is reduced by the first and second liner layers 79 and 82.
The gap (M) between the gate electrodes 74 is not buried by the liner layers 79 and 82 because it is not affected by the film thickness of the gate electrode 74. As a result, the thickness of the second liner layer 82 can be reduced with the Si oxide film and the S
A necessary and sufficient thickness determined by the difference in the etching rate of the iN film and the thickness of the interlayer insulating film 85 can be formed on the offset insulating film 75, the silicide layer 78, and the field insulating film 72.

Further, the first etching for opening the contact hole 86 and the contact hole 87 can be stopped by the second liner layer 82, so that the sidewall spacer 76 can be formed of a Si oxide film. Due to the effect of being covered with the second liner layer 82, M
In order to prevent problems such as a change in the characteristics of the OS transistor and a decrease in reliability due to the occurrence of an interface order, a process for realizing a complicated sidewall spacer structure is not required.

Further, the second liner layer 82 is not formed on the side wall of the sidewall spacer 76. As a result, the gate oxide film 73 and the gate electrode 74 of the MOS transistor, in which the characteristic variation becomes a problem,
2 does not cover the entire surface, hydrogen can pass through the Si oxide film, the characteristics can be recovered by heat treatment in an atmosphere containing hydrogen after the formation of the wiring layer 90, and the characteristics of the MOS transistor can be changed and the interface order can be reduced. Decrease in reliability due to occurrence,
And other problems can be prevented.

Further, as in the fourth embodiment, the liner layer is formed by the first liner layer 79 (Si oxide film) and the second liner layer.
By forming a two-layer film with the liner layer 82 (SiN film), the first liner layer 79 can reduce the influence of the stress of the second liner layer 82 on the silicide layer 78. When the silicide layer 78 is not formed, the first liner layer 79 is
The effect of stress on the liner layer 82 can be reduced. In this embodiment, even when the liner layer is formed of a two-layer film, the liner layer is thickened, the gap between the gate electrodes 74 is reduced, and the aspect ratio is excessively increased. Since the problem that the insulating film 85 (Si oxide film) cannot be filled and the gap between the gate electrodes 74 is formed only by forming the liner layer, that is, the problem that the gap is filled with only the etching stopper film, do not occur. Becomes possible.

Even if a metal oxide film such as Co or Al is formed as the second liner layer 82, the characteristics of the MOS transistor do not fluctuate. In this case, the thinner second liner layer 82 can be used, so that a semiconductor device manufacturing method that is more advantageous in all aspects can be obtained. In addition, Co, Al
When a metal oxide film such as a metal oxide film is formed as the second liner layer 82, the second etching for forming the contact holes 86 and 87 is performed by etching the second liner layer 82 (metal oxide film) and the first etching. Preferably, the etching is performed separately from the etching of the liner layer 79 (Si oxide film).
When etching the liner layer 82 (metal oxide film), the first
The liner layer 79 (Si oxide film) functions as an etching stopper film.

[0144]

As described above, according to the present invention, little or no second insulating film (liner layer) is formed between the side surface of the sidewall insulating film (sidewall spacer) and the interlayer insulating film. Therefore, the thickness of the second insulating film can be increased, and the distance between the gate structures can be kept wide, and an opening (contact hole) having a larger contact area can be formed, and a good contact can be obtained. be able to. In addition, the distance between the gate structure portions is reduced, so that the degree of integration and the size of the semiconductor device can be reduced. Further, even if the substrate surface is miniaturized in the horizontal direction, a good contact opening can be formed. In addition, even if the thickness of the second insulating film is increased, the distance between the gate structures can be kept wide, so that the interlayer insulating film can be easily filled between the gate structures and the opening for forming the opening can be formed. Will also be easier. In addition, during the heat treatment in an atmosphere containing hydrogen, hydrogen does not become impossible to pass through the second insulating film, so that the characteristics can be easily recovered by the heat treatment, and the sidewall insulating film does not have a complicated structure. Problems such as fluctuations in the characteristics of the MOS transistor and a decrease in reliability due to the occurrence of interface order can be prevented. Therefore, the degree of integration can be improved, the power consumption of the semiconductor device can be reduced, the manufacturing cost can be reduced, the capacity can be increased, and an excellent semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process sectional view illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 6 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 7 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 8 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 9 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 10 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 11 is a process sectional view illustrating the method for manufacturing the semiconductor device of the third embodiment of the present invention.

FIG. 12 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 13 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 14 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 15 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 16 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 17 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 18 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 19 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 20 is a process sectional view illustrating the method for manufacturing the semiconductor device of the fourth embodiment of the present invention.

FIG. 21 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 22 is a process cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 23 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 24 is a process cross-sectional view illustrating a conventional method for manufacturing a semiconductor device.

FIG. 25 is a sectional view showing a problem in the conventional example.

FIG. 26 is a sectional view showing a problem in the conventional example.

[Explanation of symbols]

1, 21, 41, 71 Si substrate 2, 22, 42, 72 Field insulating film 3, 23, 43, 73 Gate oxide film 4, 24, 44, 74 Gate electrode 5, 25, 45, 75 Offset insulating film 6, 26, 46, 76 Sidewall spacer 7, 27, 47, 77 Diffusion layer 8, 28, 48, 78 Silicide layer 9, 49 Liner layer 12, 35, 50, 85 Interlayer insulating film 13, 36, 51, 86 Contact hole (SAC) 14, 37, 52, 87 Contact hole (SAC / BL
C) 15, 38, 53, 88 Adhesion layer 16, 39, 54, 89 W plug 17, 40, 55, 90 Wiring layer 29, 79 First liner layer 32, 82 Second liner layer

Continued on the front page F-term (reference) 4M104 BB01 BB02 BB14 BB18 BB20 BB28 BB30 BB33 DD08 DD16 DD18 DD37 DD43 DD79 DD84 EE14 EE16 EE17 FF13 FF14 FF18 FF22 HH15 5F033 HH04 HH07 HH09 HH18 H33 KK KK MM08 NN06 NN07 NN29 PP09 PP12 PP15 QQ08 QQ09 QQ10 QQ13 QQ16 QQ19 QQ25 QQ28 QQ31 QQ35 QQ37 QQ48 QQ58 QQ65 QQ73 RR03 RR04 RR06 RR08 SS08 SS09 SS13 SS15 TT08 XX03 XX09 5E08 EF09 EF09 EC08 EF09 EF09 EF09 EF09 EF09 EF09

Claims (16)

[Claims] A field insulating film embedded in a groove formed in a semiconductor substrate, wherein a gate insulating film, a gate electrode, and a first insulating film are sequentially stacked on the semiconductor substrate; And providing a plurality of gate structures in which side wall insulating films are formed on side walls of the first insulating film;
A source / drain diffusion layer is provided on the surface of the semiconductor substrate so as to sandwich the gate electrode, a second insulating film is provided on the semiconductor substrate and the gate structure, and an interlayer insulating film is provided on the second insulating film. A first opening where the surface of the semiconductor substrate is exposed between the gate structure portions by removing predetermined portions of the interlayer insulating film and the second insulating film, and the field insulating film; A second opening that exposes both surfaces of the semiconductor substrate, and a wiring layer electrically connected to the surface of the semiconductor substrate through the first opening and the second opening; A semiconductor device provided over an insulating film, wherein the second insulating film has a thickness between a side surface of the side wall insulating film and the interlayer insulating film, the thickness of the second insulating film being increased by heat treatment in an atmosphere containing hydrogen. Has a thin film thickness through which A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the thickness of the second insulating film between the side surface of the sidewall insulating film and the interlayer insulating film is zero. 3. The semiconductor device according to claim 1, wherein the sidewall insulating film and the interlayer insulating film are silicon oxide films. 4. The semiconductor device according to claim 1, wherein said second insulating film is in contact with a lower portion of said second insulating film.
3. The semiconductor device according to claim 2, wherein a lower insulating film is provided in the same region as said insulating film. 5. The semiconductor device according to claim 4, wherein the sidewall insulating film, the interlayer insulating film, and the lower insulating film are silicon oxide films. 6. The semiconductor device according to claim 1, wherein the second insulating film is a silicon nitride film or a silicon oxynitride film.
6. The semiconductor device according to 2, 3, 4, or 5. 7. The semiconductor device according to claim 1, wherein the second insulating film is a metal oxide film. 8. A step of forming a groove in a semiconductor substrate and embedding a field insulating film in the groove; and forming a gate insulating film, a gate electrode, and a first insulating film on the semiconductor substrate in that order; Forming a plurality of gate structures in which a sidewall insulating film is formed on sidewalls of the electrode and the first insulating film; and forming source / drain diffusion layers on the surface of the semiconductor substrate so as to sandwich the gate electrode. Forming a second insulating film on the semiconductor substrate and the gate structure by a method in which growth in a horizontal direction with respect to the surface of the semiconductor substrate is suppressed; and after forming the second insulating film. Forming an interlayer insulating film on the entire surface; and selectively etching the interlayer insulating film and the second insulating film to expose a surface of the semiconductor substrate between the gate structure portions. Forming a second opening in which both surfaces of the field insulating film and the semiconductor substrate are exposed at the same time as forming the opening in a self-aligning manner; and forming the first opening and the second opening. Forming a wiring layer electrically connected to the surface of the semiconductor substrate via the interlayer insulating film through the interlayer insulating film. 9. The method according to claim 8, wherein the step of forming the second insulating film is performed by strong anisotropy sputtering that extracts only a component that is perpendicularly incident on the surface of the semiconductor substrate. Of manufacturing a semiconductor device. 10. The step of forming the first and second openings includes a first etching step of selectively etching an interlayer insulating film, and a second etching step of selectively etching a second insulating film. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the method further comprises the step of: forming the second insulating film as a stopper film for etching in the first etching step. 11. The method for manufacturing a semiconductor device according to claim 8, wherein the sidewall insulating film and the interlayer insulating film are formed of a silicon oxide film. 12. Before forming a second insulating film, a lower insulating film is formed on the semiconductor substrate and the gate structure by a method in which growth in a horizontal direction with respect to the surface of the semiconductor substrate is suppressed. Forming the second insulating film on the lower insulating film, and forming the first and second openings, in addition to the interlayer insulating film and the second insulating film, The method according to claim 8, wherein the film is selectively etched. 13. The step of forming the first and second openings includes a first etching step of selectively etching an interlayer insulating film, and a selective etching of a second insulating film and a lower insulating film successively. 13. The method of manufacturing a semiconductor device according to claim 12, further comprising a second etching step of etching the first insulating film, wherein the second insulating film serves as a stopper film for the etching in the first etching step. 14. The method according to claim 12, wherein the sidewall insulating film, the lower insulating film, and the interlayer insulating film are formed of a silicon oxide film. 15. The method according to claim 8, wherein said second insulating film is formed of a silicon nitride film or a silicon oxynitride film. . 16. The semiconductor device according to claim 8, wherein the second insulating film is formed of a metal oxide film.
15. The method for manufacturing a semiconductor device according to 13 or 14.