JP2001077189A - Method for manufacturing semiconductor device - Google Patents

Abstract

[PROBLEMS] To provide a method of manufacturing a semiconductor device having a stable and highly reliable self-aligned contact without causing an etch stop, a short circuit of a wiring, and an increase in a chip size. SOLUTION: After forming a groove 6 in a semiconductor substrate 1, the groove 6 is formed.
A SiO ₂ film is formed so as to be embedded inside. After the portion 7a of the SiO ₂ film is left only inside the groove 6, the upper portion is selectively removed. After forming the SiN film 8 on the entire surface,
By performing the entire etch-back, the Si inside the groove 6 is
The SiN film 8 is left over the O ₂ film portion 7a. Polycrystalline S
The i film 3 and the SiO ₂ film 2 are removed, and the groove element isolation region 9 is removed.
To form After that, the SAC structure is formed on the semiconductor substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method suitably applied to a semiconductor device having a self-aligned contact structure.

[0002]

2. Description of the Related Art In recent years, high integration of ULSI has advanced to the next generation in three years, and the design rule has been reduced by 70% of the previous generation. With the reduction in size, the speed of the semiconductor device has also been increased. In particular, in a semiconductor device such as a MOS transistor to which a fine design rule is applied, high integration has been achieved by progress of a fine processing technique in a semiconductor device manufacturing process, particularly, by increasing a resolution of a light exposure technique.

[0003] Higher resolution of the light exposure technology has been achieved by improving the performance of an exposure apparatus, a resist material, and a resist process while satisfying dimensional accuracy and overlay accuracy corresponding to design rules.

However, it is difficult for the above-described exposure apparatus to reduce the variation in the alignment of the stepper. If the variation in the alignment is large, the design margin for the alignment must be increased. as a result,
It is difficult to reduce the cell size. Therefore, there is a demand for a technique capable of reducing the design margin for alignment and reducing the cell size.

As one of the techniques for reducing the cell size, a self-aligned contact (Self Aligned Contact, SA
C) The technology is attracting attention.

Here, a semiconductor device manufactured by using the SAC technique will be specifically described below. FIG. 9A
1 is a plan view illustrating a cell of a semiconductor device having a SAC structure.

[0007] As shown in FIG.
In a semiconductor device having a C structure, a Si substrate 101
Isolation region 10 whose surface is formed by STI technology
2 separates elements. A source / drain region 103 is provided in a portion sandwiched between the element isolation regions 102 in the Y direction. Further, an offset insulating film 104 is provided in a region sandwiched between the element isolation region 102 or the source / drain region 103 in the X direction. Further, sidewalls 105 are provided on both sides of these offset insulating films 104. Also, X
In the portion sandwiched between the two offset insulating films 104 and the sidewalls 105 in the directions, the source / drain regions 1
A contact hole 106 is provided in an interlayer insulating film (not shown in FIG. 9A) in a region covering 03.

FIG. 9B is a cross-sectional view taken along the line BB of FIG. As shown in FIG. 9B, a gate insulating film 107 is formed on an active region (channel formation region) of the silicon (Si) substrate 101 separated by an element isolation region (not shown in FIG. 9B) formed by the STI technique. Is formed. A gate electrode 108 made of polycrystalline Si is formed above the gate insulating film 107. Further, an offset insulating film 104 made of silicon nitride (SiN) is formed above the gate electrode 108. Further, sidewalls 105 made of SiN are formed on the sidewall surfaces of the gate electrode 108 and the offset insulating film 104. The gate electrode 108 is covered with the offset insulating film 104 and the sidewall 105. In the Si substrate 101 on both sides of the gate electrode 108, an LDD diffusion layer 103a containing a conductive impurity at a low concentration and source / drain regions 103 containing a high concentration are formed. , A gate insulating film 107, a gate electrode 108, an LDD diffusion layer 103a connected to the channel formation region, and the source / drain region 103 constitute a MOS field effect transistor.

An interlayer insulating film 109 made of borophosphosilicate glass (BPSG) is formed on the entire surface so as to cover the upper layer of the offset insulating film 104 and the side wall 105. A contact hole 106 penetrating through the interlayer insulating film 109 and reaching the source / drain region 103 is opened, and an upper wiring 110 connected to the LDD diffusion layer 103a (source / drain region 103) is formed on the inner wall surface.
Are formed.

Next, a method for manufacturing the above-described semiconductor device will be described. Note that FIGS. 10 and 11 below show cross-sectional views along the Y direction shown in FIG.
Shows a cross-sectional view along the X direction.

That is, first, as shown in FIG.
An SiO ₂ film 1 is formed on the entire surface of the Si substrate 101 by a thermal oxidation method.
11 is formed. The thickness of this SiO ₂ film 111 is 15 n
m. Next, the SiN film 112 is formed on the SiO ₂ film 111.
To form The thickness of the SiN film 112 is 200 nm. Next, a resist pattern 113 having an opening in a region where the element isolation region is to be formed is formed on the SiN film 112.

Next, as shown in FIG. 10B, patterning of the SiN film 112 is performed by anisotropic etching using the resist pattern 113 as a mask. Next, using the resist pattern 113 and the SiN film 112 as a mask, the SiO ₂ film 111 is patterned by an anisotropic etching method. After that, the resist pattern 113 is removed.

[0013] Next, as shown in FIG.
The Si substrate 101 is etched by an anisotropic etching method using the mask 12 and the SiO ₂ film 111 as a mask. Thus, a groove 114 is formed on the Si substrate 101.

Next, as shown in FIG. 11B, the film thickness is reduced to 7 by a high-density plasma chemical vapor deposition (HDP-CVD) method.
A 00 nm SiO ₂ film 115 is formed on the entire surface.

[0015] Next, as shown in FIG. 11C, by polishing the SiO ₂ film 115 by chemical mechanical polishing (CMP), SiO ₂ in the portion other than the inside of the groove 114 film 115
Is removed.

Next, as shown in FIG. 11D, the SiN film 112 and the SiO ₂ film 1 are formed by wet etching.
11 is removed.

As described above, the element isolation region 102 is formed above the Si substrate 101.

Next, as shown in FIG. 12A, a gate insulating film 107 is formed on the Si substrate 101 on which the element isolation region (not shown in FIG. 2A) is formed by a thermal oxidation method.
Next, a gate electrode layer 116 made of polycrystalline Si is formed on the entire surface of the gate insulating film 107 by the CVD method. Next, an offset insulating film 104 is formed by forming a SiN film over the gate electrode layer 116.

Next, as shown in FIG. 12B, after a resist pattern 117 having a gate electrode shape is formed on the offset insulating film 104 by a lithography process, the resist pattern 117 is used as a mask to perform anisotropic etching such as RIE. The gate electrode layer 116 and the offset insulating film 104 are etched by an etching method. Thus, a gate electrode 108 is formed. After that, the resist pattern 117 is removed.

Next, as shown in FIG. 12C, low-concentration conductive impurities are implanted into the Si substrate 101 using the offset insulating film 104 as a mask. Thereby, an LDD diffusion layer (low-concentration diffusion layer) 103a is formed in a self-aligned manner with respect to the offset insulating film 104 and the gate electrode.

Next, as shown in FIG. 13A, a SiN film 118 is formed on the entire surface so as to cover the offset insulating film 104 and the gate electrode 108.

Next, as shown in FIG. 13B, the entire surface is etched back by an anisotropic etching method such as the RIE method so that the side walls of the gate electrode 108 and the offset insulating film 104 are made of SiN.
5 is formed.

Next, as shown in FIG. 13C, a conductive impurity is ion-implanted into the Si substrate 101 at a high concentration using the side wall 105 and the offset insulating film 104 as a mask. As a result, the source / drain regions (high-concentration diffusion layers) 103 are formed in a self-alignment manner with the sidewalls 105 and the offset insulating film 104.

Next, as shown in FIG. 14A and FIG. 14B in a cross-sectional view in a direction perpendicular to the cross section of FIG. 14A, the entire surface is made of SiO ₂ so as to cover the offset insulating film 104 and the sidewalls 105. An interlayer insulating film 109 is formed. Next, an opening 119a is formed on the interlayer insulating film 109 in a region where a contact hole is to be formed by a lithography process.
Is formed.

Next, as shown in FIG. 15A and FIG. 15B which is a cross-sectional view in a direction perpendicular to the cross section of FIG. 15A, the source is formed by anisotropic etching such as RIE using the resist pattern 119 as a mask. / Drain region 1
Etching of the interlayer insulating film 109 is performed until the surface of the substrate 03 (LDD diffusion layer 103a) is exposed. As a result, a contact hole 106 is formed. Here, the etching conditions for forming the contact hole 106 are as follows: a magnetron etching apparatus is used as an etching apparatus;
Tetrafluorocarbon octafluoride (C ₄ F ₈ ) gas, carbon monoxide (CO) gas, and argon (Ar) gas are used as etching gases, and their flow rates are 15 sccm and 300, respectively.
sccm and 400 sccm and a pressure of 5.3 Pa,
The RF power (frequency 13.56 MHz) is set to 1700 W (etching condition (1)). With such etching conditions, the etching selectivity of the interlayer insulating film 109 with respect to the offset insulating film 104 and the sidewalls 105 can be set to about 10.

Next, after removing the resist pattern 119, a conductive layer such as an aluminum (Al) film is formed so as to cover the bottom and side surfaces of the contact hole 106.
The upper wiring 110 is formed by patterning into a predetermined wiring shape.

Thus, the semiconductor device shown in FIG. 9B is manufactured.

According to the method of manufacturing a semiconductor device described above,
Even if misalignment occurs during the formation of the resist pattern 119, the etching in the formation of the contact hole 106 stops once on the upper surfaces of the offset insulating film 104 and the sidewalls 105, so that misalignment of the resist pattern 119 occurs. However, exposure of a part of the gate electrode 108 can be prevented.
Thus, it is possible to prevent a short circuit between the gate electrode 108 and the upper layer wiring 110 formed later.

[0029]

However, the above-described method for manufacturing a semiconductor device has the following problems. In other words, the etching time generally depends on the interlayer insulating film 1.
09 in consideration of film thickness variation and etch rate variation. Therefore, it is necessary to perform so-called over-etching, which is longer than the just etching time for the thickness of the interlayer insulating film 109. Also, this large amount of etching is called an over-etch amount.

For example, in the case of manufacturing the semiconductor device shown in FIG. 9B, when the thickness of the interlayer insulating film 109 is set to 1 μm and the overetch amount is set to 50%, the etching amount is 1.5 μm.
become. However, if the over-etching amount is 50%, the edge portion 102a of the element isolation region 102 is shaved as shown in FIG.

Then, the edge 102a is shaved, so that etching damage such as lattice defects is introduced into the Si substrate 101, a junction leak occurs, and the device operation becomes unstable.

Therefore, as a method of avoiding the above problem, as shown in FIG. 17, an etching stopper made of a SiN film, a silicon nitride oxide (SiON) film, or the like is formed so as to cover the offset insulating film 104 and the side wall 105. After forming the film 120, the interlayer insulating film 109 is formed.
Can be considered. However, even when such an etching stopper film 120 is formed, the following problem occurs.

That is, as described above, for example, when the thickness of the interlayer insulating film 109 is 1 μm and the amount of overetch is set to 50% under the etching condition (1), the etching depth becomes 1.5 μm. The selectivity between the SiN film as the etching stopper film 120 and the SiO ₂ film as the interlayer insulating film 109 is about 10. Thus, the thickness of the etching stopper film 120 is (1 × 0.5 / 10 =) 0.05 μm (50
nm). Therefore, sidewall 1
The distance between the gate electrodes 108 including the area 05 is smaller by 0.1 μm than the distance when the etching stopper film 120 is not used (see FIG. 9B). As a result, the portion between the gate electrodes 108 of the interlayer insulating film 109 to be removed has a high aspect ratio.

As described above, the interlayer insulating film 109 to be removed
Is increased in aspect ratio,
As shown in FIG. 18, even if the etching of the interlayer insulating film 109 is performed until the upper surface of the etching stopper film 120 is exposed, an etch stop occurs during the etching, and the etching stopper film 120 between the sidewalls 105 is formed. The portion 109a of the interlayer insulating film 109 remains in the recess formed by the above. Then, there arises a problem that etching for exposing the surface of the source / drain region 103 cannot be performed in the next step.

Even if a contact hole can be formed so as to expose the surface of the source / drain region 103 without exposing the gate electrode 108 by adjusting the etching conditions optimally, the gate electrode 108 Since the space between them is small, the exposed area of the source / drain region 103 at the bottom of the contact hole is small, and a new problem that the contact resistance is increased arises.

Therefore, as a method of avoiding these problems, a method of enlarging a part of the element formation region separated by the element isolation region 102 can be considered. By using this method, even if misalignment occurs, the element isolation region 1
02 is not removed, so that the etching stopper film 120
Need not be formed, and the distance between the gate electrodes 108 is not reduced. However, adopting this method leads to an increase in chip size, which makes high integration difficult.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device having a stable and highly reliable self-aligned contact without causing an etch stop, a short circuit in a wiring, and an increase in chip size.

[0038]

In order to achieve the above object, the present invention relates to a method of manufacturing a semiconductor device having a self-aligned contact structure on a semiconductor substrate provided with a trench element isolation region. Is formed, a first insulating film is buried in the groove, an upper portion of the first insulating film in the groove is selectively removed, and an etching stopper film is formed on the first insulating film in the groove. Thus, a groove element isolation region is formed.

In the present invention, typically, the etching stopper film is made of a material having an etching selectivity with respect to the insulating film formed on the etching stopper film. Specifically, the etching stopper film is made of silicon nitride. Become. Further, the etching stopper film can be made of silicon nitride oxide or aluminum oxide. Further, in the present invention, the first embedded in the groove is provided.
The insulating film is specifically made of silicon oxide, but other material for element isolation can be used.

In the present invention, when forming a self-aligned contact, typically, a step of forming a first pattern and a second pattern on a semiconductor substrate, and a step of forming a first side on a side wall of the first pattern. While forming the wall,
Forming a second sidewall on the side wall of the second pattern, forming a second insulating film on the entire surface of the semiconductor substrate, and forming a first resist pattern on the second insulating film; A step of etching the second insulating film using the first resist pattern as a mask to form the first pattern and the first sidewall, the second pattern and the second side wall on the second insulating film; Forming a contact hole in a self-aligned manner with the wall. The etching stopper film is made of a material different from the material of the second insulating film so that the groove element isolation region is not etched when the contact hole is formed, and the etching stopper film is formed in the groove element isolation region. Used as an etching stopper. Therefore, the etching stopper film is set so that an appropriate selection ratio can be obtained. Also, the first pattern and the second pattern are typically formed by sequentially forming a first conductive layer and a third insulating film on a semiconductor substrate, and forming the first conductive layer and the third insulating film on the semiconductor substrate. It is formed by sequentially patterning the film. Here, the first
The conductive layer has a polycide structure in which a polycrystalline silicon film, a metal film such as aluminum or copper, or a silicide film such as a tungsten silicide film is stacked on the polycrystalline silicon film, and typically has a gate electrode. Is configured. Also,
Specifically, the third insulating film is made of a material selected from the group consisting of silicon nitride, silicon nitride oxide, and aluminum oxide, and the first sidewall and the second sidewall are made of silicon nitride, It is made of a material selected from the group consisting of silicon nitride oxide and aluminum oxide. The first and second sidewalls are typically formed by forming a first pattern and a second pattern on a semiconductor substrate and then forming the first pattern and the second pattern. An insulating film is formed so as to cover the substrate, and the insulating film is entirely etched back.

In the present invention, the LDD (Light
y Doped Drain) To form a structure, typically
After the step of forming the first pattern and the second pattern, and before the step of forming the first sidewall and the second sidewall, the semiconductor substrate is formed on the semiconductor substrate using the first pattern and the second pattern as a mask. After the step of forming a low concentration diffusion layer by introducing an impurity at a low concentration and forming a first side wall and a second side wall, the first pattern and the first side wall and the second pattern are formed. And using the second sidewall and the mask as a mask to form a high concentration diffusion layer by introducing impurities into the semiconductor substrate at a high concentration.

In the present invention, in order to form a groove and bury the first insulating film inside the groove, typically, a fourth insulating film, a second conductive layer and a fifth conductive layer are formed on a semiconductor substrate. Forming a fifth insulating film, patterning a fifth insulating film, a second insulating film, and a fourth insulating film;
Forming a groove in the semiconductor substrate by etching the semiconductor substrate using the fifth insulating film, the second conductive layer, and the fourth insulating film as a mask, and forming the first insulating film on the entire surface so as to fill the groove. , A step of selectively leaving the first insulating film inside the trench, and a step of removing the fifth insulating film. Here, the second conductive layer is made of a material containing silicon as a main component, and specifically, the second conductive layer is made of amorphous silicon or polycrystalline silicon. Also,
The fourth insulating film is made of silicon oxide, and the fifth insulating film is made of silicon nitride or silicon nitride oxide.

According to the method of manufacturing a semiconductor device according to the present invention having the above-described structure, after the first insulating film is embedded in the trench, the upper portion of the first insulating film inside the trench is selectively formed. And the etching stopper film is formed on the first insulating film, so that when forming a contact hole in the self-aligned contact, the groove element isolation region exposed at the bottom of the contact hole is removed. It can be prevented from being cut by etching.

[0044]

Embodiments of the present invention will be described below with reference to the drawings. In all the drawings of the following embodiments, the same or corresponding portions are denoted by the same reference numerals.

First, the method for fabricating the semiconductor device according to the first embodiment of the present invention will be described. 1 to 8 show a method of manufacturing the semiconductor device according to the first embodiment,
1 to 3 show a process of forming a trench element isolation region using the STI technique, and FIGS. 4 to 8 show a process of manufacturing a transistor having a self-aligned contact structure.

As shown in FIG. 1A, in the method of manufacturing a semiconductor device according to the first embodiment, first, a SiO 2 is formed on a semiconductor substrate 1 such as a Si substrate by a thermal oxidation method.
_{2 A} film 2 is formed. The thickness of the SiO ₂ film 2 is, for example, 1
5 nm. Next, a polycrystalline Si film 3 is formed on the SiO ₂ film 2 by, for example, a CVD method. This polycrystalline Si film 3
Is, for example, 20 nm. Next, a SiN film 4 is formed on the polycrystalline Si film 3 by, for example, a CVD method. The thickness of the SiN film 4 is, for example, 200 nm. Next, a resist pattern 5 having an opening 5a in the formation region of the groove element isolation region is formed by a lithography process.

Next, as shown in FIG. 1B, using the resist pattern 5 as a mask, the SiN film 4 is etched by an anisotropic etching method such as RIE. Next, using the resist pattern 5 and the SiN film 4 as a mask, the polycrystalline Si film 3 is etched by an anisotropic etching method. Subsequently, the resist pattern 5, the SiN film 4
Then, using the polycrystalline Si film 3 as a mask, the SiO ₂ film 2 is etched by an anisotropic etching method. After that, the resist pattern 5 is removed.

Next, as shown in FIG. 1C, the SiN film 4,
Using the polycrystalline Si film 3 and the SiO ₂ film 2 as a mask, the semiconductor substrate 1 is etched by an anisotropic etching method, thereby forming a groove 6.

Next, as shown in FIG.
-An SiO ₂ film 7 is formed on the entire surface so as to be embedded in the groove 6 by the CVD method.

Next, as shown in FIG.
By polishing the SiO ₂ film 7 by law, to remove the SiO ₂ film 7 in the portion other than the inside of the groove 6. As a result, a portion 7a of the SiO ₂ film 7 is left inside the groove 6.

Next, as shown in FIG. 2C, the SiN film 4 is removed by a wet etching method using, for example, hot phosphoric acid (H ₃ PO ₄ ).

Next, as shown in FIG. 3A, the SiO ₂ film 7a left inside the groove 6 is etched by about 100 nm by anisotropic etching, thereby selectively removing the upper portion thereof. Thereafter, a SiN film 8 is formed on the entire surface by, for example, a CVD method. The thickness of the SiN film 8 is, for example, 200 nm.

Next, as shown in FIG. 3B, the SiO ₂ film 7a inside the trench 6 is
The entire surface is etched back so that a part of the iN film 8 remains.

Next, as shown in FIG. 3C, after removing the polycrystalline Si film 3 by, for example, a wet etching method, the SiO ₂ film 2 is successively removed by, for example, a wet etching method.
Is removed.

As described above, the trench element isolation region 9 using the STI technique is formed. In FIGS. 4 and 5 in the subsequent steps, a cross-sectional view perpendicular to the cross-sections in FIGS. 1 to 3 is used.

Next, as shown in FIG. 4A, a gate insulating film 10 is formed on the active region of the semiconductor substrate 1 separated by the trench isolation region 9 by, for example, a thermal oxidation method. Next, a gate electrode layer 11 made of a polycrystalline Si film is formed on the entire surface of the gate insulating film 10 by, for example, a CVD method.
Next, an offset insulating film 12 made of, for example, a SiN film is formed on the entire surface of the gate electrode layer 11 by a CVD method using, for example, tetraethyloxosilane (TEOS) gas.

Next, as shown in FIG. 4B, a resist pattern 13 having a gate electrode shape is formed on the offset insulating film 12 by a lithography process. Next, using the resist pattern 13 as a mask, the offset insulating film 1 is formed by anisotropic etching such as RIE.
2. The gate electrode layer 11 and the gate insulating film 10 are sequentially etched. Thus, the gate electrode 14 made of polycrystalline Si is formed on the semiconductor substrate 1 via the gate insulating film 10.
Is formed.

Next, as shown in FIG. 4C, after the resist pattern 13 is removed, a conductive impurity is ion-implanted into the semiconductor substrate 1 at a low concentration using the offset insulating film 12 as a mask. Thus, the low-concentration diffusion layer 15 is formed on the semiconductor substrate 1 in a self-aligned manner with respect to the offset insulating film 12.
a is formed.

Next, as shown in FIG.
By the method, an SiN film 16 is formed on the entire surface so as to cover the offset insulating film 12, the gate electrode 14, and the gate insulating film 10.

Next, as shown in FIG.
The entire surface is etched back by an anisotropic etching method such as an etching method, so that the sidewalls 17 are left on the side surfaces of the gate electrode 14 and the offset insulating film 12.

Next, as shown in FIG. 5C, conductive impurities are ion-implanted into the semiconductor substrate 1 at a high concentration using the offset insulating film 12 and the side walls 17 as a mask. As a result, a high-concentration diffusion layer 15 is formed above the semiconductor substrate 1 in a self-aligned manner with respect to the offset insulating film 12 and the sidewall 17. The low-concentration diffusion layer 15a and the high-concentration diffusion layer 15 form source / drain regions having an LDD structure.

Next, as shown in FIG. 6A and FIG. 6B which is a cross-sectional view perpendicular to the cross section of FIG.
For example, an SiO ₂ film is grown at a low temperature over the entire surface of the semiconductor substrate 1 by a CVD method using an OS gas. As a result, the LTO film 19 is formed. The thickness of the LTO film 19 is, for example, 600 nm. Next, a resist pattern 20 having an opening in a contact hole formation region is formed on the LTO film 19.

Next, as shown in FIG. 7A and FIG. 7B in a sectional view perpendicular to the section of FIG. 7A, the surface of the source / drain region is formed by anisotropic etching using the resist pattern 20 as a mask. LTO film 1 until exposed
9 is etched. As a result, a contact hole 21 is formed in the LTO film 19. Here, as an example of etching conditions in forming the contact hole 21, a magnetron etching apparatus is used as an etching apparatus, and a C ₄ F ₈ gas, a CO gas, an Ar gas, and an O ₂ gas are used as an etching gas. The flow rates were 15 sccm, 150 sccm, 30
0 sccm and 7 sccm, pressure 4 Pa, RF
The power (frequency 13.56 MHz) is 1500 W. At this time, as shown in FIG. 7B, since the SiN film 8 is formed on the groove element isolation region 9 below the contact hole 21, the SiN film 8 is formed when the contact hole 21 is formed. It becomes an etching stopper film in region 9. Therefore, even if over-etching is performed during the formation of the contact hole 21, the trench element isolation region 9 is not etched.

Next, as shown in FIG. 8A and FIG. 8B in a cross section perpendicular to the cross section of FIG. 8A, after removing the resist pattern 20, the source is covered while covering the exposed surface of the inner wall of the contact hole 21. For example, a conductive layer such as an Al film is formed so as to connect to the / drain region. afterwards,
This conductive layer is patterned into a predetermined wiring shape. Thus, the upper wiring 22 is formed.

Thereafter, the interlayer insulating film, the connection hole, the connection hole plug, and the upper wiring are sequentially and repeatedly formed a desired number of times by a conventionally known method, whereby a desired semiconductor device is manufactured.

As described above, according to the method of manufacturing the semiconductor device according to this embodiment, the etching stopper has an etching selectivity with respect to the LTO film 19 above the trench element isolation region 9 and serves as an etching stopper film. Since the SiN film 8 is formed, the self-aligned contact (S
In the formation of the AC) structure, the trench element isolation region 9 is prevented from being etched when the contact hole 21 is formed without forming an etching stopper film so as to cover the sidewall 17 and the offset insulating film 12. be able to. Thereby, it is possible to prevent a junction leak due to a lattice defect in the semiconductor substrate 1 due to excessive overetching. Also, as before,
Since it is not necessary to form an etching stopper film on the sidewall 17 in forming the SAC structure, there is no need to consider an etch stop at the time of etching in forming the contact hole 21, and the contact hole 2
1 can increase the degree of freedom of the etching conditions. Further, since the bottom area of the contact hole 21 in the SAC structure can be increased as compared with the contact hole in the conventional SAC structure, the contact area between the source / drain region and the upper wiring 22 can be increased. An increase in contact resistance can be suppressed. Therefore, problems such as etch stop, junction leakage, and increase in contact resistance can be avoided, and a semiconductor device having a stable and highly reliable SAC structure can be manufactured.

Although the embodiment of the present invention has been specifically described above, the present invention is not limited to the above-described embodiment, and various modifications based on the technical idea of the present invention are possible. is there.

For example, the numerical values, materials, and etching conditions described in the above embodiments are merely examples, and different numerical values, materials, and etching conditions may be used as needed.

Also, for example, in the above-described embodiment, the present invention is applied to the manufacture of a dual gate MOS transistor. However, a semiconductor device such as a MOS transistor used for a dynamic RAM (DRAM) or a static RAM (SRAM), a bipolar device, The present invention can be applied to the manufacture of a semiconductor device having a contact hole formed in a self-aligned manner, such as a bipolar semiconductor device such as a transistor or a semiconductor device such as an A / D converter.

Further, for example, in the above-described embodiment, a polycrystalline Si film having a single-layer structure is used as the gate electrode 14. For example, a two-layer structure of a polycrystalline Si film and a silicide film, or a three-layer structure The above configuration may be adopted.

Further, for example, in the above-described embodiment, the SiN film 8 is used as the etching stopper film on the trench element isolation region 9 when the contact hole 21 is formed, but it is not necessarily limited to the SiN film. Instead, a nitrided oxide film such as a silicon nitride oxide (SiON) film or an alumina (Al ₂ O ₃ ) film can be used as the etching stopper film above the trench element isolation region 9. The degree of the etching selectivity between the interlayer insulating film and the etching stopper film is optimized by the thickness of the interlayer insulating film and its variation, and the etching stopper film is configured to have this etching selectivity. Is determined.

Further, for example, in the above-described embodiment, an Al film is used as the upper wiring 22. However, the present invention is not necessarily limited to the Al film, and the upper wiring 22 may be, for example, a polycrystalline Si film or an amorphous film. It is also possible to use a high quality Si film or a Cu film. Further, the upper layer wiring 22 is not limited to a wiring having a single layer structure.
It may have a layered structure or a configuration of three or more layers.

Further, for example, in the above-described embodiment, the groove 6 is formed, and the Si
After the O ₂ film 7 is formed, a portion 7a of the SiO ₂ film 7 is left only inside the groove 6 by the CMP method.
It is also possible to use the following method. That is,
After forming the SiO ₂ film 7, an SiO ₂ film 7 on the SiN film 4 is removed by CMP, followed by selectively removing the SiN film 4, a polycrystalline Si film 3 and SiO ₂ film 2 is removed After that, the SiO ₂ raised above the upper surface of the semiconductor substrate 1
The portion of the film 7 is removed by polishing by the CMP method, so that the portion 7a of the SiO ₂ film 7 is left only inside the groove 6. Further, in forming the groove 6, after etching the SiN film 4, a sidewall is formed on the inner wall of the opening formed in the SiN film 4, and the semiconductor substrate 1 is etched using the SiN film 4 and the sidewall as a mask. By doing so, the groove 6 may be formed.

[0074]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, a semiconductor device having a stable and highly reliable self-aligned contact without causing an etch stop, a short circuit, and an increase in chip size. The device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 8 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to one embodiment of the present invention;

9A and 9B are a plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional technique.

FIG. 10 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 11 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 12 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 13 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 14 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 15 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to a conventional technique.

FIG. 16 is a cross-sectional view for describing a problem in a conventional semiconductor device manufacturing method.

FIG. 17 is a cross-sectional view for explaining another example of a method for manufacturing a semiconductor device according to a conventional technique.

FIG. 18 is a cross-sectional view for describing a problem of another example in a method of manufacturing a semiconductor device according to a conventional technique.

[Explanation of symbols]

1 ... semiconductor substrate, 2,7 ··· SiO ₂ film, 4,
8, 16: SiN film, 6: groove, 9: groove element isolation region, 15: high concentration diffusion layer, 15a: low concentration diffusion layer, 17: side wall, 19 ... LT
O film, 21 ... contact hole

Claims (12)

[Claims] 1. A method of manufacturing a semiconductor device having a self-aligned contact structure on a semiconductor substrate provided with a trench element isolation region, wherein a trench is formed in the semiconductor substrate, and a first insulating film is formed inside the trench. Burying, selectively removing an upper portion of the first insulating film inside the trench, and forming an etching stopper film on the first insulating film inside the trench, thereby forming the trench element isolation region. A method for manufacturing a semiconductor device, characterized in that it is formed. 2. The method according to claim 1, wherein said first insulating film is made of silicon oxide. 3. The method according to claim 1, wherein said etching stopper film is made of silicon nitride. 4. A step of forming a first pattern and a second pattern on the semiconductor substrate, forming a first sidewall on a side wall of the first pattern, and a side wall of the second pattern. Forming a second sidewall on the semiconductor substrate, forming a second insulating film on the entire surface of the semiconductor substrate, forming a first resist pattern on the second insulating film, By etching the second insulating film using the first resist pattern as a mask, the first pattern, the first sidewall, the second pattern, and the second pattern are formed on the second insulating film. Forming a contact hole in a self-aligned manner with respect to a side wall, wherein in the step of forming the contact hole, the etching stopper film is separated by the groove element. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the stopper is used as the etching stopper in the separation region. 5. A method according to claim 1, wherein a first conductive layer and a third insulating film are sequentially formed on the semiconductor substrate, and the first conductive layer and the third insulating film are patterned. 5. The method according to claim 4, wherein said second pattern is formed. 6. The method according to claim 5, wherein the third insulating film is made of a material selected from the group consisting of silicon nitride, silicon nitride oxide, and aluminum oxide.
The manufacturing method of the semiconductor device described in the above. 7. The semiconductor device according to claim 4, wherein said first side wall and said second side wall are made of a material selected from the group consisting of silicon nitride, silicon nitride oxide and aluminum oxide. Of manufacturing a semiconductor device. 8. A fourth insulating film and a second insulating film on the semiconductor substrate.
Forming a conductive layer and a fifth insulating film sequentially, patterning the fifth insulating film, the second conductive layer and the fourth insulating film, and forming the fifth insulating film.
Forming the groove in the semiconductor substrate by etching the semiconductor substrate using the second conductive layer and the fourth insulating film as a mask; Forming a film, and selectively leaving the first insulating film inside the trench;
2. The method according to claim 1, further comprising the step of removing the fifth insulating film. 9. The method according to claim 8, wherein said second conductive layer is made of a material containing silicon as a main component. 10. The semiconductor device according to claim 8, wherein said second conductive layer is made of amorphous silicon or polycrystalline silicon.
The manufacturing method of the semiconductor device described in the above. 11. The method according to claim 8, wherein the fourth insulating film is made of silicon oxide. 12. The method according to claim 8, wherein said fifth insulating film is made of silicon nitride or silicon nitride oxide.