JP2006128328A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inhibit the generation of a crystal defect in the element forming region of a semiconductor substrate. <P>SOLUTION: A gate oxide film is formed by two oxidation methods of an ISSG oxidation method and the other oxidation method. Accordingly, since the stress of an STI can be made smaller than the case only of a conventional single oxidation method, the generation of the crystal defect can be inhibited in the element forming region of the semiconductor substrate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a semiconductor device having a field effect transistor in an element formation region of a semiconductor substrate partitioned by a trench type element isolation region and a manufacturing technique thereof.

  As a field effect transistor mounted on a semiconductor device, for example, an insulated gate field effect transistor called MISFET (Metal Insulator Semiconductor Field Effect Transistor) is known. In a MISFET whose gate insulating film is made of a silicon oxide film, it is usually called a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  In the MISFET, side wall spacers made of an insulating film are formed on the side walls of the gate electrode, and impurities are implanted into both ends thereof to form source and drain regions. In many cases, crystal defects are generated in the silicon substrate at the ends of the source and drain regions. As a method for preventing such crystal defects, for example, Japanese Patent Application Laid-Open No. 08-97210 discloses FIG. 21 (schematic cross-sectional view). As shown in FIG. 4, the oxide film 33 is interposed between the side surface of the gate electrode 31 and the side wall spacer 34 made of a silicon nitride film and between the side wall spacer 34 and the silicon substrate 1 therebelow. It is disclosed. In FIG. 21, 30 is a gate insulating film, and 32 and 35 are a pair of semiconductor regions which are a source region and a drain region.

  On the other hand, as one of element isolation techniques for electrically isolating element formation regions on the main surface of a semiconductor substrate, for example, a trench type element isolation technique called STI (Shallow Trench Isolation) or SGI (Shallw Groove Isolation) is used. Are known. In this trench type element isolation technique, a main surface of a semiconductor substrate is mainly thermally oxidized to form a pad oxide film, and then, for example, a silicon nitride film is formed on the pad oxide film as an antioxidant film by CVD (Chemical Vapor Deposition). After that, the silicon nitride film and the pad oxide film are patterned to form an etching mask made of the silicon nitride film and the pad oxide film on the element formation region of the main surface of the semiconductor substrate, After that, the main surface (groove forming region) of the semiconductor substrate around the etching mask is etched to form a groove, and then, for example, an oxidation film is formed on the main surface of the semiconductor substrate including the inside of the groove as an insulating film. A silicon film is formed by a CVD method, and then the silicon oxide film is made, for example, by CMP (Chemical Mechanical Research) so that the silicon oxide film remains only in the trench. This is a technique for electrically separating adjacent element formation regions by removing the material by a chemical mechanical polishing (Chemical) method. In this trench type element isolation technique, it is possible to miniaturize an element isolation region that electrically isolates adjacent element formation regions as compared with an element isolation technique called LOCOS (Local Oidation of Silicon). Therefore, high integration of the semiconductor device can be achieved.

  The groove type element separation technique is described in, for example, Japanese Patent Application Laid-Open No. 11-177047.

Japanese Patent Application Laid-Open No. 08-97210 JP-A-11-177047

  The present inventor has found that the structure disclosed in Japanese Patent Application Laid-Open No. 08-97210 cannot sufficiently suppress crystal defects generated in the substrate of the active region (element forming region) including the source and drain regions. It was.

  This is because the occurrence of crystal defects is not determined solely by the stress of the gate electrode, but the stress (STI stress) of element isolation (Shallow Trench Isolation) has a significant influence that cannot be ignored.

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can solve the above-described problems, can suppress defects generated in the source and drain regions of a substrate, and have better performance.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  In order to achieve the above object, the present invention uses two methods for forming a gate insulating film: an ISSG oxidation method and a conventional wet or dry oxidation method. This makes it possible to reduce the stress of STI as compared with a single case of only the conventional wet oxidation method and the dry oxidation method, and thus it is possible to suppress the occurrence of crystal defects in the element formation region of the semiconductor substrate. Specifically, it can have the following configuration.

  The inventor of the present invention has an element isolation region formed on a substrate, a gate structure is formed in the element formation region, and further when an impurity such as arsenic or phosphorus is implanted at a high concentration into a silicon substrate, We examined the possibility of crystal defects. As a result, when an impurity is implanted into the substrate, a high stress (impurity-induced stress) is generated in the impurity-implanted region (impurity formation region), and this impurity-induced stress is generated in the gate structure and the element isolation formation process ( It was ascertained that crystal defects occur due to restraint by (STI stress). From this, it was considered that crystal defects can be prevented by reducing the stress generated in the process of forming the element isolation region so as not to restrain the impurity stress.

In element isolation, a trench is formed in a silicon substrate and a buried oxide film is buried. There are many silicon substrate oxidation processes in the transistor formation process. Oxygen serving as an oxidizing species diffuses through the buried oxide film even inside the trench, so that the oxide film grows also on the trench sidewall. When Si is changed to SiO ₂ , volume expansion of about twice occurs. Since this volume expansion is restricted by the buried oxide film, a high compressive stress is generated in the silicon substrate. In order to reduce this compressive stress, two types of methods, ISSG oxidation method and conventional wet or dry oxidation method, are used for forming the gate insulating film.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  According to the present invention, it is possible to suppress the occurrence of crystal defects in the element formation region of the semiconductor substrate.

  In addition, according to the present invention, it is possible to improve the performance of a semiconductor device having a MISFET.

  Examples of embodiments of the present invention will be described below with reference to the drawings.

  In the first embodiment, an example in which the present invention is applied to a semiconductor device having a MISFET as a field effect transistor will be described.

1 to 16 are diagrams related to a semiconductor device which is Embodiment 1 of the present invention.
FIG. 1 is a schematic cross-sectional view showing a schematic configuration of a MISFET mounted on a semiconductor device.
FIG. 2 is a schematic cross-sectional view enlarging a part of FIG.
2 to 13 are schematic cross-sectional views showing a manufacturing process of a semiconductor device,
FIG. 14 is a diagram for explaining the ISSG oxidation method;
FIG. 15 is a view showing a generation mechanism of STI stress,
FIG. 16 is a diagram showing a comparison between the STI stress when the gate insulating film is formed by the wet oxidation method and the STI stress when the gate insulating film is formed by the ISSG oxidation method and the wet oxidation method.

  As shown in FIG. 1A, the semiconductor device according to the first embodiment is mainly composed of a silicon substrate 1 made of, for example, p-type single crystal silicon as a semiconductor substrate. An element isolation region 1 a for partitioning an element formation region (active region) 1 s used as a transistor element formation region is selectively formed on the main surface (element formation surface, circuit formation surface) of the silicon substrate 1. ing. The element isolation region 1a has a groove type structure formed by, for example, a well-known STI (Shallow Trench Isolation) technique. In the element isolation region 1a by the STI technique, a groove 4 having a depth of, for example, about 300 [nm] is formed on the main surface of the silicon substrate 1, and then the silicon substrate 1 is thermally oxidized to form a thermal oxide film on the inner surface of the groove 4. (Silicon oxide film) 5 is formed, and then, for example, a silicon oxide film 6 is formed as an insulating film on the main surface of the silicon substrate 1 by CVD (Chemical Vapor Deposition). It is formed by flattening by a CMP (Chemical Mechanical Polishing) method so as to remain selectively inside. That is, the element isolation region 1a of the first embodiment includes a groove 4 formed on the main surface of the silicon substrate 1, a thermal oxide film 5 formed along the inner surface of the groove 4, and a groove via the thermal oxide film 5. 4 is configured to include an insulating film (silicon oxide film 6) embedded in 4. Here, the silicon oxide film 6 embedded in the trench 4 may be referred to as a buried oxide film 6.

  A p-type well region 7 and an n-channel conductivity type MISFET (hereinafter simply referred to as an n-type MISFET) Q1 are formed in the element formation region 1s on the main surface of the silicon substrate 1 partitioned by the element isolation region 1a.

  The n-type MISFET-Q1 mainly includes a channel formation region, a gate insulating film 10, a gate electrode 13, a source region, and a drain region. The gate insulating film 10 is provided in the element forming region on the main surface of the silicon substrate 1, and the gate electrode 13 is provided on the element forming region on the main surface of the silicon substrate 1 with the gate insulating film 10 interposed therebetween to form a channel. The region is provided in the surface layer portion of the silicon substrate 1 immediately below the gate electrode 13. The source region and the drain region are provided in the surface layer portion of the silicon substrate 1 so as to sandwich the channel formation region in the channel length (gate length) direction of the channel formation region.

  The source region and the drain region of the n-type MISFET-Q1 have a pair of n-type semiconductor regions (impurity diffusion layers) 16 that are extension regions and a pair of n-type semiconductor regions (impurity diffusion layers) 18 that are contact regions. It has become. The n-type semiconductor region 16 is provided in the element formation region on the main surface of the silicon substrate 1 in alignment with the gate electrode 13. The n-type semiconductor region 18 is provided in the element formation region of the main surface of the silicon substrate 1 in alignment with the side wall spacer 17 provided on the side wall of the gate electrode 13. The side wall spacer 17 is formed of, for example, a silicon nitride film as an insulating film.

  The n-type semiconductor region 18 that is a contact region has a higher impurity concentration than the n-type semiconductor region 16 that is an extension region. That is, the n-type MISFET-Q1 of Embodiment 1 has an LDD (Lightly Doped Drain) structure in which impurities on the channel forming region side of the drain region are reduced in concentration.

  As shown in FIG. 1B, the gate electrode 13 is not limited to this. For example, a polysilicon film (doped silicon film) 11 into which an impurity for reducing the resistance value is introduced, and the polysilicon film 11 are formed. A multi-layer structure including the tungsten film 12 provided on the substrate. An insulating film 14 made of, for example, a silicon nitride film is provided on the upper surface of the gate electrode 13 so as to cover the upper surface.

  The gate insulating film 10 includes a thermal oxide film (for example, silicon oxide film) 8 formed by an ISSG (In-situ Steam Generation) oxidation method, and a thermal oxide film (for example, silicon oxide film) 9 formed by another oxidation method. It is configured to include. Other oxidation methods include a wet oxidation method and a dry oxidation method, but the thermal oxide film 9 of the first embodiment is formed by a wet oxidation method. The thermal oxide film 9 is formed between the silicon substrate 1 and the thermal oxide film 8, and is formed to be thicker than the thermal oxide film 8. In the first embodiment, the thermal oxide film 8 is formed with a thickness of about 10 [nm], for example, the thermal oxide film 9 is formed with a thickness of about 15 [nm], and the gate insulating film 10 is, for example, 25 The film thickness is about [nm].

Here, the ISSG oxidation method, as shown in FIG. 14, includes H ₂ (hydrogen) and O ₂ (oxygen) in a film formation chamber (chamber) 23 in which a semiconductor wafer 24 (silicon substrate 1) is disposed. Is directly introduced and water vapor (H ₂ O) is generated in the film formation chamber 23 to form an oxide film.

  As shown in FIG. 1A, an interlayer insulating film 19 made of, for example, a silicon oxide film is provided on the main surface of the silicon substrate 1 so as to cover the n-type MISFET-Q1. A connection hole 20 that reaches the n-type semiconductor region 18 from the surface of the interlayer insulating film 19 is provided on the n-type semiconductor region 18, and a conductive plug 21 is embedded in the connection hole 20. Yes. The n-type semiconductor region 18 is electrically connected to the wiring 22 extending on the interlayer insulating film 19 through the conductive plug 21. The conductive plug 21 is formed of, for example, a polysilicon film into which an impurity for reducing the resistance value is introduced.

  Next, manufacturing of the semiconductor device will be described with reference to FIGS.

  First, as a semiconductor substrate, for example, a silicon substrate 1 made of p-type single crystal silicon having a specific resistance of about 10 [Ωcm] is prepared, and then the main surface of the silicon substrate 1 is thermally oxidized to have a thickness of 5 to 15 [ A pad oxide film 2 made of a silicon oxide film with a thickness of about [nm] is formed, and then a silicon nitride film 3 with a thickness of, for example, about 150 [nm] is formed on the pad oxide film 2 by a CVD method as an anti-oxidation film. Thereafter, the silicon nitride film 3 and the pad oxide film 2 are preliminarily patterned (etched) to selectively remove the silicon nitride film 3 and the pad oxide film 2 on the groove forming region of the main surface of the silicon substrate 1. Thereafter, the groove forming region on the main surface of the silicon substrate 1 is etched to form a groove 4 having a predetermined angle with respect to the main surface of the silicon substrate 1 as shown in FIG. The pad oxide film 2 is a buffer film for preventing thermal strain from remaining on the surface of the silicon nitride film 3 formed directly on the silicon main surface and causing crystal defects.

  Next, the inner surface including the side surface and the bottom surface of the groove 4 is thermally oxidized in an oxidizing atmosphere in the range of 900 ° C. to 1150 ° C., and the thickness is several nm to several tens nm along the inner surface of the groove 4 as shown in FIG. A thermal oxide film 5 made of a silicon oxide film is formed. The ISSG method is suitable for forming the thermal oxide film 5.

  Next, as shown in FIG. 4, for example, a silicon oxide film 6 is formed as an insulating film on the main surface of the silicon substrate 1 including the inside of the groove 4 by a CVD method or a HDP (High Density Plasma) CVD method.

  Next, the silicon oxide film 6 is selectively removed and planarized by, for example, a CMP (Chemical Mechanical Polishing) method or a dry etching method so that the silicon oxide film 6 remains only in the trench 4. In this step, the silicon oxide film 6 is selectively embedded in the trench 4. In this step, the silicon nitride film 3 used as the antioxidant film serves as an etching stopper and functions to prevent the silicon substrate 1 under the silicon nitride film 3 from being etched.

  Next, heat treatment is performed in a nitrogen atmosphere of 900 ° C. to 1150 ° C., an argon atmosphere, and an oxidizing atmosphere to densify the silicon oxide film 6 inside the groove 4, and then the silicon nitride film 3 and the pad oxidation are performed. The film 2 is removed. By this step, as shown in FIG. 5, the groove 4 formed on the main surface of the silicon substrate 1, the thermal oxide film 5 formed along the inner surface of the groove 4, and the groove 4 via the thermal oxide film 5 are formed. An element isolation region 1a including the buried silicon oxide film 6 is formed, and the element formation region 1s is partitioned by the element isolation region 1a. Note that the silicon oxide film 6 buried in the trench 4 may be referred to as a buried oxide film 6.

Next, the surface (main surface) of the silicon substrate 1 is heat-treated in an oxidizing atmosphere at 900 to 1100 ° C. to form a thermal oxide film having a thickness of about 10 [nm], and then the thermal oxide film is buffered. As a layer, an impurity (for example, adjacent (P)) is ion-implanted under the condition that the dose is about 1E13 (1 × 10 ¹³ [atoms / cm ² ]) to form the p-type well region 7. The buffer layer may be substituted with the pad oxide film 2. However, since the formation of a new oxide film may improve the electrical reliability of the gate insulating film formed thereafter, the pad oxide film 2 is removed to form a new thermal oxide film. Is preferred. In this case, the ISSG oxidation method is preferable from the viewpoint of reducing the STI stress. Thereafter, the thermal oxide film (buffer layer) is removed with diluted HF.

Next, as shown in FIG. 6, a gate insulating film 10 including a thermal oxide film 8 and a thermal oxide film 9 is formed in the element formation region 1 s on the main surface of the silicon substrate 1. The gate insulating film 10 is formed by first using an ISSG oxidation method to oxidize the element formation region on the main surface of the silicon substrate 1 in an ISSG oxidation atmosphere (H ₂ concentration 5%) at about 1050 ° C. and thermally oxidize it. The film 8 is formed, and then the thermal oxidation film 9 is formed by oxidizing the element formation region on the main surface of the silicon substrate 1 in a wet oxidation atmosphere at 850 ° C. to 950 ° C., for example, using a wet oxidation method. Do. In the first embodiment, the thermal oxide film 8 is formed with a film thickness of about 10 [nm], for example, and the thermal oxide film 9 is formed with a film thickness of about 15 [nm], for example, for a total of about 25 [nm]. A gate insulating film 10 of about [nm] is formed. The thermal oxide film 9 is formed between the silicon substrate 1 and the thermal oxide film 8 as shown in FIG.

  Next, as shown in FIG. 7, the gate electrode 13 is formed on the element formation region of the main surface of the silicon substrate 1 with the gate insulating film 10 interposed therebetween. For the gate electrode 13, for example, a polysilicon film 11 is formed on the entire surface of the silicon substrate 1 including the gate insulating film 10 by a CVD method, and then a tungsten film 12 is formed on the polysilicon film 11 by a sputtering method. Thereafter, a silicon nitride film 14 is formed as an insulating film on the tungsten film 12 by a CVD method, and then these films are sequentially patterned. Impurities that reduce the resistance value are introduced into the polysilicon film 11.

Next, a thermal oxide film (silicon oxide film) 15 having a film thickness of, for example, about 3 to 10 [nm] is formed in the element formation region 1s on the main surface of the silicon substrate 1 by heat treatment in an oxygen atmosphere. The oxide film 15 is used as a buffer layer, and an impurity (for example, arsenic (As)) is ion-implanted into the element formation region of the main surface of the silicon substrate 1 to match a pair of gate electrodes 13 as shown in FIG. An n-type semiconductor region (extension region) 16 is formed. Impurity ion implantation is performed, for example, under the conditions of an acceleration energy of about 30 to 50 KeV and a dose of 1E13 (1 × 10 ¹³ ([atoms / cm ² ]).

  Next, sidewall spacers 17 made of, for example, a silicon nitride film are formed on the sidewalls of the gate electrode 13. The sidewall spacer 17 is formed by forming, for example, a silicon nitride film as an insulating film on the entire main surface of the silicon substrate 1 by a CVD method, and thereafter performing anisotropic etching such as RIE (Reactive Ion Etching) on the silicon nitride film. It is formed by applying. The sidewall spacer 17 is formed in alignment with the gate electrode 13.

Next, an impurity (for example, arsenic (As)) is ion-implanted into the element formation region on the main surface of the silicon substrate 1, and a pair of n-type semiconductor regions (contacts) aligned with the sidewall spacers 17 as shown in FIG. Region) 18 is formed. Impurity ion implantation is performed under conditions of, for example, an acceleration energy of about 30 to 50 KeV and a dose amount of 5E14 (5 × 10 ¹⁴ ([atoms / cm ² ]) to 3E15 (5 × 10 ¹⁵ ([atoms / cm ² ])). This step almost completes the n-type MISFET-Q1.

  Next, an interlayer insulating film 19 made of, for example, a silicon oxide film is formed on the entire surface of the silicon substrate 1 including the n-type MISFET-Q1 by the CVD method, and then the interlayer insulating film 19 is formed as shown in FIG. The surface is flattened by, for example, a CMP method.

  Next, the interlayer insulating film 19 is partially removed by anisotropic dry etching to form a connection hole 20 on the n-type semiconductor region 18 as shown in FIG.

  Next, a conductive material such as metal or polysilicon is buried in the connection hole 20 to form a conductive plug 13 as shown in FIG. 13, and then a wiring 21 is formed on the interlayer insulating film 19. By this step, the structure shown in FIG. 1 is obtained.

Next, the function and effect of the present invention will be described.
Many crystal defects are based on experience so far when an element isolation region is formed on a substrate and a gate structure is formed in the element formation region. Further, impurities such as arsenic and phosphorus are implanted at a high concentration into the silicon substrate. It is known that it is likely to occur when This is because when an impurity is implanted into the silicon substrate, the surface of the silicon substrate becomes amorphous due to the implanted atoms, and the subsequent heat treatment causes the amorphous layer to crystallize in accordance with the atomic arrangement of the underlying silicon substrate. It is considered that crystal defects occur when crystal forces are disturbed when an external force (stress) is applied during crystallization. That is, it is considered that external stress induces crystal defects. Therefore, it is considered that if external stress can be reduced, recrystallization proceeds smoothly and crystal defects can be reduced. As the external stress, STI stress can be considered as the main stress in addition to the stress of the gate electrode. The mechanism of this STI stress is as follows (see FIG. 15).

There are many silicon substrate oxidation processes in the transistor formation process. Therefore, oxygen that becomes an oxidizing species diffuses through the buried oxide film 6 inside the groove 4, and an oxide film grows on the side wall of the groove 4. When the oxide film (SiO ₂ ) is changed from Si, the volume expansion is approximately twice, and this volume expansion is restricted by the buried oxide film 6. A high compressive stress is generated in the element formation region 1 s in the silicon substrate 1 due to the influence of the reaction force due to this constraint. This compressive stress is called STI stress.

  Since the STI stress is caused by oxidation of the side wall of the groove 4, it is considered that the STI stress can be reduced if the oxidation amount of the side wall of the groove 4 can be reduced. In general, the wet oxidation method used for forming the gate insulating film has a high diffusion rate of the oxidized species in the oxide film, so that many oxidized species reach the side walls and the bottom of the trench 4. Therefore, high STI stress is induced.

  On the other hand, in the ISSG oxidation method, it is relatively difficult to form an oxide film thickness of about 15 [nm] or more even if the oxidation time is increased. That is, in the ISSG oxidation method, the amount of oxidation on the side wall of the groove 4 can be reduced as compared with the conventional wet oxidation method. From this, it is considered that the STI stress is considerably reduced when all the oxide films are formed in the semiconductor manufacturing process by the ISSG oxidation method. However, in a peripheral circuit such as an input / output circuit, the gate insulating film may have to be formed with a thickness of 15 [nm] or more because of the gate voltage. In this case, the ISSG oxidation method, which is difficult to form an oxide film thickness of about 15 [nm] or more, cannot be applied. Therefore, for example, when the gate insulating film is formed with a thickness of 25 [nm], an oxide film having a thickness of about 10 to 15 [nm] is formed by the ISSG oxidation method, and then the oxide film is formed by the wet oxidation method. Then, an oxide film having a total film thickness of 25 [nm] is formed.

  FIG. 16 shows the result of analysis of this effect using an oxidation stress simulator.

The case where the gate insulating film thickness 25 [nm] was set to ISSG oxidation 10 [nm] + wet oxidation 16 [nm] and only wet oxidation 25 [nm] was compared. FIG. 16 shows that the STI stress is reduced by about 200 MPa by forming the gate insulating film by ISSG oxidation + wet oxidation. This effect can be obtained by changing the wet oxidation to dry oxidation. However, the electrical reliability of the gate insulating film formed by the dry oxidation method is generally lower than that of the wet oxidation. Is preferable. Needless to say, the STI stress decreases when most of the oxide film of 25 [nm] is subjected to ISSG oxidation. However, if the H ₂ concentration in the ISSG oxidation condition is increased, the electrical reliability of the gate insulating film is deteriorated. Therefore, the H ₂ concentration is preferably 33% or less, preferably 20% or less, and practically 10% or less.

  There are two types of gate processes in which the gate oxide film thickness of the peripheral circuit is about 25 [nm] (thick film gate oxide film) and the gate oxide film thickness of the logic circuit and memory circuit is about 8 [nm] (thin film gate oxide film). is there. In general, the formation method in this case oxidizes the surface of the silicon substrate by about 20 [nm], and then removes the thick gate oxide film in the thin film gate oxide film formation region to form the thin film gate oxide film at 8 [nm]. Then, a thick gate oxide film 25 [nm] and a thin gate oxide film 8 [nm] are formed. This method is effective even when such a two-type gate oxide film is formed. First, an oxide film of 10 to 15 [nm] is formed by the ISSG oxidation method, and later, an oxide film of several nm is formed by the wet oxidation method to form a thick gate oxide film and a thin gate oxide film.

Since the oxide film grows from the Si / SIO ₂ interface, the thick gate oxide film in this case has a wet oxide film and an ISSG oxide film in this order from the Si substrate surface. Since the density of the ISSG oxide film is higher than that of other oxide films, it has been clarified by the X-ray reflectometry (GIXR). By examining the density by this method, the formation of the gate oxide film can be improved. It can be determined whether or not the oxidation + wet oxidation method is used.

  As a method for reducing the stress of STI, heat treatment is performed in NO gas after forming the pad oxide film (thermal oxide film) 2 shown in FIG. 2 to form oxynitride at the interface between the silicon substrate 1 and the pad oxide film 2. There are a method, a method of forming an oxynitride on the surface of the pad oxide film 2 by exposure to nitrogen plasma, a method of forming an STI (groove type isolation region) by forming the gate electrode 13 and the like. These methods suppress the diffusion of oxygen or reduce the amount of oxidation to reduce the STI stress. However, since the STI stress cannot be made completely zero, even when these are performed, The method is effective. That is, this method is effective when there is a stress caused by STI.

  The STI stress increases in a flash memory having many oxidation steps and a large amount of oxidation. Therefore, this method is particularly effective for flash memory. The STI stress increases rapidly when the STI width (groove width w: see FIG. 15) is 0.2 [μm] or less. For this reason, this method is particularly effective for a semiconductor device having an STI width w (width of a trench type element region) of 0.2 [μm] or less. Furthermore, crystal defects in the silicon substrate 1 occur when the STI stress increases even when no impurities are implanted. Therefore, this method is effective even in a semiconductor device that does not implant impurities at a high concentration. Since it is difficult to form a high-quality oxide film of about 15 [nm] or more by the ISSG oxidation method, it is particularly effective when the thickness of the gate insulating film is 15 [nm] or more.

  In order to form the gate insulating film, there is a stack type oxide film in which a CVD oxide film (an oxide film formed by a CVD method) is deposited on a thermal oxide film. Also in this method, since the CVD oxide film does not oxidize the inside of the groove, the STI stress can be reduced. However, in this method, the electrical reliability of the gate insulating film is deteriorated as compared with the ISSG oxidation method and the wet oxidation method, so the ISSG oxidation + wet oxidation method is superior in this respect.

  Thus, according to the first embodiment, it is possible to suppress the occurrence of crystal defects in the element formation region 1s on the main surface of the silicon substrate 1 partitioned by the groove-type element isolation region 1a.

  In addition, since generation of crystal defects in the element formation region 1s on the main surface of the silicon substrate 1 can be suppressed, high performance of the semiconductor device having the n-type MISFET-Q1 can be achieved.

  In the second embodiment, an example in which the present invention is applied to a semiconductor device having two levels of MISFETs having different gate breakdown voltages will be described.

17 to 20 are diagrams related to a semiconductor device which is Embodiment 2 of the present invention.
FIG. 17 is a schematic cross-sectional view showing a schematic configuration of a MISFET mounted on a semiconductor device;
18 to 20 are schematic cross-sectional views showing the manufacturing process of the semiconductor device.

  As shown in FIG. 17, the semiconductor device according to the first embodiment is mainly configured by a silicon substrate 1 made of, for example, p-type single crystal silicon as a semiconductor substrate.

  The main surface (element formation surface, circuit formation surface) of the silicon substrate 1 has element formation regions (active regions) 1m and 1n partitioned by an element isolation region (inactive region) 1a. The p-type well region 7 and the n-type MISFET-Q1 are formed, and the p-type well region 7a and the n-type MISFET-Q2 are formed in the element formation region 1n.

  The n-type MISFETs Q1 and Q2 have different gate breakdown voltages. The n-type MISFET-Q1 is a high voltage MISFET that is driven by a power supply voltage of 10 to 12 [V], for example, and the n-type MISFET-Q2 is a power supply voltage of 1.8 [V] or 3.3 [V], for example. It is a low breakdown voltage MISFET driven by The n-type MISFET-Q2 has basically the same configuration as the n-type MISFET-Q1, but the gate insulating film 25 is formed with a film thickness thinner than the gate insulating film 10 of the n-type MISFET-Q1, and the channel The length (gate length) is narrower than MISFET-Q1. In the second embodiment, the gate insulating film 10 of the n-type MISFET-Q1 is formed with a film thickness of about 25 [nm], for example, and the gate insulating film 25 of the n-type MISFET-Q2 is about 15 [nm], for example. It is formed with a film thickness.

  As shown in FIG. 20, the gate insulating film 10 of the n-type MISFET-Q1 includes a thermal oxide film 8 formed by an ISSG oxidation method and a thermal oxide film 9 formed by, for example, a wet oxidation method. Yes. The gate insulating film 25 of the n-type MISFET-Q2 is made of a thermal oxide film 9 formed by, for example, a wet oxidation method.

  Next, formation of gate insulating films having different thicknesses will be described with reference to FIGS.

First, after forming the element isolation region 1a and the p-type well region (7, 7a) by the same method as in the first embodiment, an ISSG oxidation method is used, in an ISSG oxidation atmosphere of about 1050 ° C. (H _The silicon substrate 1 is heat-treated at ₂ concentration (5%) to form a thermal oxide film 8 in the element formation region (1m, 1n) on the main surface of the silicon substrate 1 as shown in FIG.

  Next, as shown in FIG. 19, the thermal oxide film 8 in the element formation region 1n is selectively removed, and then the silicon substrate 1 is used in a wet oxidation atmosphere at 850 ° C. to 950 ° C., for example, using a wet oxidation method. As shown in FIG. 20, a thermal oxide film 9 is formed in the element formation region (1m, 1n) on the main surface of the silicon substrate 1. By this step, the gate insulating film 10 made of the thermal oxide film 8 and the thermal oxide film 9 is formed in the element forming region 1m, and the gate insulating film 25 made of the thermal oxide film 9 is formed in the element forming region 1n.

  Then, the structure shown in FIG. 17 is obtained by forming the gate electrode 13, the n-type semiconductor region 16, the sidewall spacer 17, the n-type semiconductor region 18 and the like by performing the same process as in the first embodiment. .

  As described above, also in the second embodiment, as in the first embodiment, the crystal defects in the element formation regions (1m, 1n) on the main surface of the silicon substrate 1 partitioned by the groove-type element isolation region 1a. Occurrence can be suppressed.

  Further, since the generation of crystal defects in the element formation region (1m, 1n) on the main surface of the silicon substrate 1 can be suppressed, the performance of the semiconductor device having the n-type MISFETs Q1 and Q2 having different gate breakdown voltages can be improved. Can be planned.

  Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.

  For example, in the first and second embodiments, the example in which the present invention is applied to a semiconductor device having an n-channel conductivity type MISFET has been described. However, the present invention relates to a semiconductor device having a p-channel conductivity type MISFET, and n The present invention can be applied to a semiconductor device having a channel conductivity type MISFET and a p channel conductivity type MISFET (complementary MISFET).

It is typical sectional drawing which shows schematic structure of MISFET mounted in the semiconductor device which is Example 1 of this invention. FIG. 2 is a schematic cross-sectional view in which a part of FIG. 1 is enlarged. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device being Example 1. FIG. It is a figure for demonstrating an ISSG oxidation method. It is a figure which shows the generation | occurrence | production mechanism of STI stress. It is a figure which shows the comparison with the STI stress at the time of forming a gate insulating film by the wet oxidation method, and the STI stress at the time of forming a gate insulating film by the ISSG oxidation method and the wet oxidation method. It is typical sectional drawing which shows schematic structure of MISFET mounted in the semiconductor device which is Example 2 of this invention. 10 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device being Example 2. FIG. 10 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device being Example 2. FIG. 10 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device being Example 2. FIG. It is typical sectional drawing which shows the conventional MISFET.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 1a ... Element isolation region, 1m, 1n, 1s ... Element formation region, 2 ... Pad oxide film, 3 ... Silicon nitride film, 4 ... Groove, 5 ... Thermal oxide film, 6 ... Silicon oxide film (embedding) Oxide film), 7, 7a ... p-type well region, 8,9 ... thermal oxide film, 10 ... gate insulating film, 11 ... polysilicon film, 12 ... tungsten film, 13 ... gate electrode, 14 ... silicon nitride film, 15 ... thermal oxide film, 16 ... n-type semiconductor region, 17 ... sidewall spacer, 18 ... n-type semiconductor region, 19 ... interlayer insulating film, 20 ... connection hole, 21 ... conductive plug, 22 ... wiring, 23 ... film formation Chamber, 24 ... Semiconductor wafer, 25 ... Gate insulating film, Q1, Q2 ... MISFET.

Claims (12)

Forming a trench in the main surface of the semiconductor substrate, and then embedding an insulating film in the trench to form an element isolation region;
Forming a gate insulating film on the main surface of the semiconductor substrate partitioned by the element isolation region,
In the gate insulating film forming step, a first oxide film is formed on the main surface of the semiconductor substrate by an ISSG oxidation method, and a second oxide film is formed on the main surface of the semiconductor substrate by another oxidation method. A method for manufacturing a semiconductor device, comprising: a step. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the other oxidation method is a wet oxidation method or a dry oxidation method. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first oxide film is formed before the second oxide film. In the manufacturing method of the semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the groove has a width of 0.2 μm or less. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first oxide film is thicker than the second oxide film. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the thickness of the gate insulating film is 15 [nm] or more. An element isolation region including a groove formed in a main surface of a semiconductor substrate and an insulating film embedded in the groove;
A field effect transistor having a gate electrode provided on a main surface of the semiconductor substrate partitioned by the element isolation region with a gate insulating film interposed therebetween;
2. The semiconductor device according to claim 1, wherein the gate insulating film includes a first oxide film formed by an ISSG oxidation method and a second oxide film formed by another oxidation method. The semiconductor device according to claim 7,
The semiconductor device, wherein the second oxide film is formed by a wet oxidation method or a dry oxidation method. The semiconductor device according to claim 7,
The semiconductor device, wherein the second oxide film is formed between the semiconductor substrate and the first oxide film. The semiconductor device according to claim 7,
The semiconductor device, wherein the first oxide film is thicker than the second oxide film. The semiconductor device according to claim 7,
The semiconductor device according to claim 1, wherein the gate insulating film has a thickness of [15] nm or more. The semiconductor device according to claim 7,
The width of the groove is 0.2 μm or less.

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