JP2003031659A - Semiconductor device having borderless contact structure and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: A semiconductor device having a borderless contact structure and a method of manufacturing the same are provided. SOLUTION: Gate electrode 109 and semiconductor substrate 10
Then, an etching protection layer 116 is formed on the substrate 0. A spacer 118 is formed on the etching protection layer 116 on both sides of each gate electrode 109. The source / drain ion implantation is performed using the gate electrode 109 including the spacer 118 as a mask, and then the spacer 118 is removed. After sequentially forming an etching stop layer 124 and an interlayer insulating film 126 on the entire surface of the resultant structure, the resultant structure is etched to form a first layer.
A contact hole 128a and a second contact hole 128b for borderless contact are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a borderless contact.
The present invention relates to a semiconductor device having a ct) structure and a manufacturing method thereof.

[0002]

2. Description of the Related Art Contact formation for connecting isolated element regions formed in a semiconductor substrate by using a highly conductive thin film consists of securing an alignment margin and an element separation margin. Occupies a considerable area in. Therefore, the contact acts as a major factor in determining the size of the memory cell.

In the recently developed semiconductor device having a design rule of 0.12 μm or less, a short-channel effect of a transistor is caused by miniaturization of the design rule.
In order to prevent this, LDD (lightly dope)
d drain) structure is used. In order to implement the LDD structure, a spacer having a role of separating the high concentration source / drain region from the gate electrode by a predetermined distance must be formed on the sidewall of the gate electrode.

In addition, a borderless contact process for forming a contact hole over the active region and the field region is introduced by reducing a margin for forming the contact hole on the active region which is an operating region of the transistor. There is. The borderless contact process is a process of forming a contact hole over the active region and the field region so that the size of the contact is not reduced while maintaining the distance between the gate electrode of the transistor and the contact.

In the initial borderless contact process, the interlayer insulating film formed on the silicon substrate was etched to expose a part of the field oxide film and the surface of the silicon substrate adjacent to the field oxide film, which was exposed in this case. There is a problem that recesses are formed in the oxide film. At this time, since the depth of the recess becomes deeper than the source / drain junction of the active region and becomes closer to the junction boundary,
A direct contact path between the contact and the silicon substrate is generated to induce a leakage current.

Further, even if the contact hole is formed thinner than the source / drain junction in the active region, if the contact hole is formed up to the portion adjacent to the junction, the barrier layer and the silicon used during the subsequent contact formation are formed. The leakage current is generated by the reaction of. That is, when the barrier layer made of Ti / TiN is heat-treated, silicon in the source / drain regions reacts with Ti / TiN to form a silicide film that acts on a conductor, thereby generating a leakage current.

Therefore, in order to prevent a recess from being formed on the surface of the field oxide film during the borderless contact process, the etch stop layer (etch) can protect the field oxide film during contact etching.
A method of forming a stopping layer was developed.

1 to 4 are sectional views for explaining a method of forming a contact hole of a semiconductor device using a borderless contact process according to a conventional method.

As shown in FIG. 1, after forming a mask pattern (not shown) on the semiconductor substrate 10, the semiconductor substrate 10 is etched using the mask pattern as an etching mask to form a trench. Then, an oxide is deposited by chemical vapor deposition so that the trench is filled in the entire surface of the semiconductor substrate 10 in which the trench is formed.
It is deposited by a vapor deposition (CVD) method. Then, etch-back or chemical mechanical polishing is performed until the surface of the mask pattern is exposed.
Then, the field oxide film 12 is formed only inside the trench by performing a CMP method. Then, the semiconductor substrate 10 is separated into the active region and the field region by the field oxide film 12. Then, the mask pattern is removed.

After that, a gate oxide film 14 is formed on the active region of the semiconductor substrate 10, and a gate electrode 15 of the transistor is formed thereon. The gate electrode 15 has a polycide structure in which a polysilicon layer 16 doped with impurities and a metal silicide layer 18 are stacked. continue,
By ion-implanting the first impurity 20 using the gate electrode 15 as a mask, the low concentration source / drain regions 22, that is, L
A DD area is formed.

As shown in FIG. 2, a nitride film, for example, a silicon nitride (SiN) film is vapor-deposited on the entire surfaces of the gate electrode 15 and the semiconductor substrate 10, and is etched back to form side walls of the gate electrode 15. The spacer 24 is formed. Then, the gate electrode 15 and the spacer 24
The second impurity 26 is ion-implanted by using the mask as a mask, so that the high-concentration source / drain region 2 is formed on the surface (that is, the active region) of the semiconductor substrate 10 on both sides of the spacer 24.
8 is formed.

As shown in FIG. 3, a nitride film, for example, silicon nitride (SiN) is deposited on the entire surface of the spacer 24, the gate electrode 15 and the semiconductor substrate 10 in an amount of about 300 to 50.
An etching stopper layer 30 is formed by vapor deposition to a thickness of about 0Å. The etch stop layer 30 has a role of protecting the field oxide film 12 in a subsequent borderless contact process.

As shown in FIG. 4, the etching stop layer 30 is formed.
An oxide such as BPSG (Boro-Phosph)
oSilicate glass) or PSG (Ph
The interlayer insulating film 32 is formed by vapor-depositing phosphosilicate glass. After forming a photoresist pattern (not shown) on the interlayer insulating film 32 by a photolithography process, the interlayer insulating film 32 and the etching stop layer 30 are sequentially dry-etched by using the photoresist pattern as an etching mask to form a gate. Electrode 1
Between the first and second contact holes 34a for exposing the surface of the semiconductor substrate 10 and the second contact hole 34b for borderless contact exposing the surface of the semiconductor substrate 10 adjacent to the field oxide film 12 and a part of the surface of the field oxide film 12. Form.

As the degree of integration of semiconductor devices increases,
In a semiconductor device having a design rule of 0.12 μm or less, a space (s
space) critical dimensions
ion (CD) and the gate electrode space critical dimension is reduced. According to the conventional method described above, the gate electrode 1
In a state where the LDD spacer 24 is formed on the side wall of No. 5, the etching stop layer 30 for borderless contact is thick enough to sufficiently prevent the recess of the field oxide film 12, for example, 300 Å or more. Evaporate to a thickness. Thereby, the gate electrode 15 and the gate electrode 15
And the space between the gate electrodes 15 becomes narrower and the space between the gate electrodes 15 is filled with the etching stop layer 30 (see A in FIG. 3). That is, the spacer 24 and the etch stop layer 30 reduce the critical dimension of the space between the gate electrodes 15, so that the critical dimension of the bottom surface of the first contact hole 34 a formed between the gate electrodes 15 (bottom C).
D) cannot be secured sufficiently.

Therefore, during the subsequent contact hole etching process, the gate electrode 15 and the gate electrode 1 are
In the space between 5, the etching stop layer 30 remains without being completely etched, so that the contact-not
-A defect such as an open will occur (see B in Fig. 4).

In order to solve the not-open of the first contact hole 34a, an etching process of the interlayer insulating film 32 and the etching stop layer 30 is performed until the surface of the semiconductor substrate 10 between the gate electrodes 15 is completely exposed. When proceeding, a borderless contact hole formed at the boundary between the field region and the active region, that is, the second
There arises a problem that the contact hole 34b is formed while the field oxide film 12 is excessively etched.

[0017]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a borderless contact structure capable of preventing not-opening of a contact hole formed in an active region between gate electrodes. To provide.

Another object of the present invention is to provide a semiconductor device having a borderless contact structure capable of preventing not-opening of a contact hole formed in an active region between gate electrodes. Another object of the present invention is to provide a method for forming a contact hole in a semiconductor device, which is suitable for manufacturing the semiconductor device.

[0019]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a semiconductor substrate having an active region and a field region separated by a field oxide film, and a plurality of semiconductor substrates formed on the active region of the semiconductor substrate. On the gate electrode and the semiconductor substrate in order to protect the gate electrode and the semiconductor substrate from an etching process for widening the width between the gate electrodes by forming the gate electrode and the gate electrode with a spacerless structure. The first contact hole is formed between the formed etching protection layer and the gate electrode which is laminated on the etching protection layer to prevent the recess of the field oxide film due to the borderless contact formation and which is widened by the gate electrode having no spacer. An etching stop layer formed so that a space for forming A first contact hole penetrating the etching protection layer and the etching stop layer so as to expose the surface of the semiconductor substrate between the gate electrodes and a portion of the field oxide film adjacent to the field oxide film and the field oxide film. An interlayer insulating film having a second contact hole for borderless contact penetrating the etching protection layer and the etching stop layer so as to expose the surface, and extending between the gate electrodes without forming a spacer between the gate electrodes. Provided is a semiconductor device, wherein an etching protection layer and an etching stop layer protect a gate electrode and a semiconductor substrate during an etching process for forming a first contact hole and a second contact hole for obtaining a uniform width. .

The present invention for attaining the above and other objects comprises the steps of forming a plurality of gate electrodes on the active region of a semiconductor substrate separated into an active region and a field region by a field oxide film. Forming an etching protection layer on the gate electrode and the semiconductor substrate; forming a spacer made of a material having an etching selection ratio with the etching protection layer on the etching protection layer on both sides of each gate electrode; Source / drain ion implantation using a gate electrode including a mask as a mask, removing a spacer to secure a space for forming a first contact hole between the gate electrodes, and Forming an etch stop layer on the front surface to prevent depression of the field oxide film due to borderless contact formation A step of forming an interlayer insulating film on the etching stopper layer, and a step of sequentially etching the interlayer insulating film, the etching stopper layer and the etching protective layer to expose the surface of the semiconductor substrate between the gate electrodes and the field. Forming a second contact hole for borderless contact exposing a surface of the semiconductor substrate adjacent to an oxide film and a partial surface of the field oxide film, and forming a borderless contact between the field region and the active region. A method for forming a contact hole in a semiconductor device is provided.

According to the present invention, the spacers formed on the sidewalls of the gate electrode are removed to realize the LDD structure of the transistor after the high concentration source / drain ion implantation. Sufficiently secure the basal plane critical dimension of the first contact hole to be formed. Therefore, it is possible to prevent a defect in which the first contact hole formed in the active region between the gate electrodes is not opened.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

5 to 13 are sectional views for explaining a method of forming a contact hole of a semiconductor device according to the first embodiment of the present invention.

FIG. 5 shows a step of forming the field oxide film 102. After forming a mask pattern (not shown) for limiting a portion where a field oxide film is formed on the semiconductor substrate 100, for example, after forming a mask pattern including a pad oxide film and a nitride film pattern laminated thereon. ,
By using the mask pattern as an etching mask, the semiconductor substrate 100 is etched to a predetermined depth to form the trench 101. The trench 101 is generally formed so as to have a depth of about 4000 to 6000Å and a width of about 4000 to 6000Å from the surface of the semiconductor substrate 100, but the semiconductor device is highly integrated and separated. It may be variously changed depending on the shape of the active region, the resolution of the photolithography process, and the like.

Then, an oxide film (not shown) is formed on the entire surface of the semiconductor substrate 100 in which the trench 101 is formed by chemical vapor deposition (CVD) so that the trench 101 is completely filled.
Vapor deposition method. Desirably, the oxide film is US
G, O3-TEOS USG or high density plasma (HD
P) oxide-like gap filling (gap filli)
ng) Use a material with excellent characteristics.

Subsequently, a planarization process such as an etch back or a chemical mechanical polishing (CMP) process is performed until the upper nitride film pattern of the mask pattern is exposed, and then the mask pattern is removed. Then, the field oxide film 102 is formed inside the trench 101,
The semiconductor substrate 100 is separated into an active region and a field region by the field oxide film 102.

In the present embodiment, the shallow trench isolation (shallow trench isolation;
Although the field oxide film 102 is formed by using STI, the partial oxidation of silicon (local oxide) is performed.
The field oxide film can be formed by using a non-silicon (LOCOS) process or an improved LOCOS process.

Subsequently, an oxide film 103 is formed by a thermal oxidation process on the active region of the semiconductor substrate 100 on which the field oxide film 102 is formed. As the gate film, for example, a polysilicon layer 105 doped with impurities and a metal silicide layer 107 are sequentially deposited on the oxide film 103. The metal silicide layer 107 is, for example, tungsten silicide (WSix) or tantalum silicide (TaSi).
₂ ) and at least one metal silicide selected from molybdenum silicide (MoSi ₂ ) is deposited to a predetermined thickness.

Then, a nitride such as silicon nitride (SiN) is deposited on the metal silicide layer 107 by a low pressure chemical vapor deposition (LPCVD) method to a thickness of about 800 Å to form an anti-reflective layer.
layer) (not shown). The antireflection layer serves to prevent light from being reflected from the lower substrate during a subsequent photolithography process and facilitates formation of a photoresist pattern.

FIG. 6 shows a step of forming the gate oxide film 104 and the gate electrode 109. After forming a photoresist pattern (not shown) on the antireflection layer by a photolithography process, the antireflection layer is patterned into a gate pattern using the photoresist pattern as an etching mask. Then, after removing the photoresist pattern, the patterned antireflection layer is used as an etching mask to sequentially dry-etch the metal silicide layer 107, the polysilicon layer 105, and the oxide film 103, whereby the semiconductor substrate 100 is removed. A gate oxide film 104 and a gate electrode 109 are formed on the active region of. Most of the antireflection layer is removed during the photolithography process described above.

FIG. 7 shows a low concentration source / drain region 11
2 shows the step of forming 2. As described above, after forming the gate electrode 109, the first impurity 110 is ion-implanted using the gate electrode 109 as a mask. Then, low-concentration source / drain regions 112, that is, LDD regions are formed on the surface of the semiconductor substrate 100 on both sides of the gate electrode 109.

Subsequently, the implanted ions are activated, and at the same time, the semiconductor substrate 10 generated by ion implantation is activated.
A heat treatment process is performed to compensate for 0 lattice defects and the like.

FIG. 8 shows a step of forming the buffer layer 114, the etching protection layer 116 and the insulating film 117. Gate electrode 109 and low concentration source / drain region 1
An oxide is deposited on the entire surface of the semiconductor substrate 100 on which 12 is formed to a thickness of about 30 to 100 Å to form a buffer layer 114.

Then, SiN and S are formed on the buffer layer 114.
A nitride such as iON or BN is deposited to a thickness of about 50 to 300Å, preferably about 200Å to form the etching protection layer 116. The buffer layer 114 has an etching protection layer 116 made of a nitride and has a semiconductor substrate 100.
It has the role of preventing direct contact with. The etching protection layer 116 has a role of preventing the lower gate electrode 106, the semiconductor substrate 100 and the field oxide film 102 from being damaged when the LDD spacer is subsequently removed.

Subsequently, an insulating layer 117 made of a material having an etching selection ratio to the material forming the etching protection layer 116 is formed on the etching protection layer 116 in a thickness of about 500 to 800 Å. To do.
Desirably, the insulating layer 117 is silicon oxide (SiO ₂ ).
It is formed of an oxide such as.

FIG. 9 shows the step of forming the spacer 118 and the high concentration source / drain region 122. The insulating layer 117 is etched back to form spacers 118 made of oxide on both side walls of the gate electrode 109.

Subsequently, the second impurity 120 is ion-implanted by using the spacer 118 and the gate electrode 109 as a mask, so that the high concentration source / drain regions 122 are formed on the surface of the semiconductor substrate 100 on both sides of the spacer 118.
To form.

When the thickness of the etching protection layer 116 made of nitride formed on the semiconductor substrate 100 is 300 Å or more at the time of source / drain ion implantation, the etching protection layer 116 may be source / drain ion implantation. To reduce the saturation current of the transistor and reduce the threshold voltage (Threshold voltage).
By moving the voltage (Vth), the electrical characteristics of the transistor are deteriorated. Therefore, the etching protection layer 116 is thin enough to reduce the blocking effect of the source / drain ion implantation, preferably 200 Å.

Subsequently, the implanted ions are activated, and at the same time, the semiconductor substrate 10 generated by the implantation of the ions is activated.
A heat treatment process is performed to compensate for the 0 lattice defect and the like.

FIG. 10 shows the step of removing the spacer 118. After forming the high-concentration source / drain regions 122 as described above, an etchant having a nitride to oxide etch selectivity of 20: 1, such as hydrofluoric acid (H
F) or BOE (Buffered oxide e)
The spacer 118 is removed only by carrying out wet etching using a (tchant).

At this time, the etching protection layer 116 is formed on the gate electrode 10 during the wet etching process described above.
9. Prevent the active region of the semiconductor substrate 100 and the field oxide film 102 from being damaged. As mentioned above,
When the spacer 118 is removed, only the etching protection layer 116 remains on the upper surface and the side surface of the gate electrode 109 with a uniform thickness.

In the conventional semiconductor device, the LDD spacers formed on the sidewalls of the gate electrodes reduce the width between the gate electrodes in which the contact holes are formed, thereby smoothly performing the borderless contact process in the subsequent process. Therefore, when the etch stop layer is deposited, the space between the narrow gate electrodes is filled with the etch stop layer. Therefore, the etching stopper layer is not completely removed and remains between the gate electrodes in the subsequent contact hole etching process, so that the contact holes are not exposed.
The defect that it becomes t-open occurs.

On the other hand, in the present invention, the LD formed on the side wall of the gate electrode 109 after the source / drain ion implantation is performed.
By removing the D spacer 118, the width between the gate electrodes 109 is widened. Thereafter, when the etch stop layer is deposited for a borderless contact process in a subsequent process, the etch stop layer is deposited along the topology between the gate electrodes 109 and the thickness of the etch stop layer formed on the field oxide layer 102. Gate electrode 109
The thickness of the etching stop layer formed between and becomes uniform. Therefore, it is possible to secure the critical dimension of the base surface of the contact hole formed between the gate electrodes 109 and prevent the contact hole from becoming not-open.

As shown in FIG. 11, after removing the spacer 118 as described above, silicon nitride (Si) is formed on the entire surface of the gate electrode 109 and the semiconductor substrate 100.
A nitride such as N) is deposited to a thickness of about 100-1000Å, preferably about 200Å to form the etch stop layer 124.

The etch stop layer 124 etches the interlayer insulating film deposited on the etch stop layer 124 in a subsequent process to form a borderless contact hole from the surface of the semiconductor substrate 100 adjacent to the field oxide film 102 to a part of the surface of the field oxide film 102. Has a role of preventing etching together with a part of the field oxide film 102 made of the same material as or similar to the interlayer insulating film.

In the conventional semiconductor device, in order to prevent the recess of the field oxide film 102 during the contact hole etching step, the etching stop layer is formed to a thickness of about 500Å or more. Meanwhile, in the first embodiment of the present invention, since the etching protection layer 116 remaining on the upper surface and the side surface of the gate electrode 109 is formed of the same nitride as or similar to the etching stop layer 124, a subsequent contact hole etching process may be performed. At this time, it has a role of preventing the field oxide film 102 from being etched. Therefore, even if the thickness of the etching protection layer 116 is taken into consideration and the etching stopper layer 124 is thinly formed to a thickness of about 200 Å or less, it is possible to sufficiently prevent the field oxide film 102 from being etched.

As shown in FIG. 12, the etching stop layer 1 is formed.
24 on the oxide, for example, BPSG (Boro-Pho
sposilicate glass) or PSG
(PhosphoSilicate glass) is deposited by plasma-excited chemical vapor deposition (PECVD) to a thickness of about 300 to 1000Å to form an interlayer insulating film 126.
To form. At this time, in order to flatten the surface of the interlayer insulating film 126, etch back or chemical mechanical polishing (C
The MP) step can also be carried out.

As shown in FIG. 13, a photoresist pattern (not shown) defining a region where a contact hole is formed is formed on the interlayer insulating film 126 by a photolithography process. Then, using the photoresist pattern as an etching mask, a mixed gas having an etching selectivity of 10 to 15: 1 for the interlayer insulating film 126 made of an oxide to the etching stopper layer 124 made of a nitride is used. The interlayer insulating film 126 is etched by the dry etching process described above. Then, the photoresist pattern is removed, and the exposed etching stopper layer 124 and the etching protection layer 116 and the buffer layer 114 thereunder are dry-etched using the interlayer insulating film 126 as an etching mask.

Then, the first contact hole 1 exposing the surface of the semiconductor substrate 100 between the gate electrodes 109 is exposed.
A second contact hole 128b for borderless contact is formed to expose the surface of the semiconductor substrate 100 adjacent to 28a and the field oxide film 102 and a part of the surface of the field oxide film 102.

As described above, according to the first embodiment of the present invention, the gate electrode 10 is formed to implement the LDD structure of the transistor after the high concentration source / drain ion implantation.
By removing the spacer 118 formed on the side wall of the gate electrode 9, a sufficient width between the gate electrodes 109 is secured.

After that, the etching stop layer 124 for the borderless contact process is formed to form the etching stop layer 1 formed on the field oxide film 102.
The thickness of 24 and the thickness of the etching stop layer 124 formed between the gate electrodes 109 become uniform. Therefore, in order to form the contact hole, the etching stop layer 12 is formed.
The problem that the etching stopper layer 124 deposited between the gate electrodes 109 is not removed when etching 4 is prevented, so that not-opening of the contact hole can be prevented.

Further, since the etching protection layer 116 remaining on the upper surface and the side surface of the gate electrode 109 is formed of a nitride which is the same as or similar to the etching stop layer 124, the thickness of the etching protection layer 116 is taken into consideration. Even if the etching stop layer 124 is thinly formed to a thickness of about 200 Å or less, the field oxide film 102 can be sufficiently prevented from being etched during the contact hole etching process.

14 to 18 are sectional views for explaining a method of forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

As shown in FIG. 14, a normal device isolation process, for example, shallow trench device isolation (shallow) is performed.
A field oxide film 202 is formed on the semiconductor substrate 200 by a trench isolation (STI) process to separate the semiconductor substrate 200 into an active region and a field region. Then, a gate oxide film 204 and a gate electrode 209 are formed on the active region of the semiconductor substrate 200.
Desirably, the gate electrode 209 is formed of an impurity-doped polysilicon layer 206 and a metal silicide layer 20.
8 is laminated to form a polycide structure.

Then, the gate electrode 209 is used as a mask to ion-implant the first impurity to form low-concentration source / drain regions 212, that is, LDD regions, on the surface of the semiconductor substrate 200 on both sides of the gate electrode 209. To do.
After that, a heat treatment process is performed to activate the implanted ions and at the same time, to compensate the lattice defects of the semiconductor substrate 200 generated by the ion implantation.

Gate electrode 209 and low concentration source /
An oxide such as silicon oxide (SiO ₂ ) is formed on the entire surface of the semiconductor substrate 200 on which the drain region 212 is formed by about 50.
An etching protection layer 216 is formed by vapor deposition to a thickness of 300 Å. The etching protection layer 216 is formed on the gate electrode 20 below the LDD spacer when the LDD spacer is removed.
9. It has a role of preventing the semiconductor substrate 200 and the field oxide film 202 from being damaged.

Subsequently, an insulating layer 217 made of a material having an etching selection ratio to the material forming the etching protection layer 216 is formed on the etching protection layer 216 to a thickness of about 500 to 800 Å in an arbitrary etching process. Form. Desirably, the insulating layer 217 is formed of a polysilicon layer.

As shown in FIG. 15, the insulating layer 217 is etched back to form spacers 218 made of a polysilicon layer on both side walls of the gate electrode 209. Then, the spacer 218 and the gate electrode 209 are used as a mask to implant a second impurity, so that the spacer 21
A high concentration source / drain region 222 is formed on the surface of the semiconductor substrate 200 on both sides.

In this embodiment, since the etching protection layer 216 formed on the semiconductor substrate 200 is formed of oxide at the time of source / drain ion implantation, it is possible to prevent deterioration of transistor characteristics due to ion implantation blocking. it can.

Subsequently, the implanted ions are activated, and at the same time, the semiconductor substrate 20 generated by the implantation of the ions is activated.
A heat treatment process is performed to compensate for 0 lattice defects and the like.

As shown in FIG. 16, as described above, after forming the high concentration source / drain regions 222, the etching selection ratio of oxide to polysilicon is 30: 1.
Wet etching using a polysilicon etchant is performed to remove only the spacer 218. At this time, the etching protection layer 216 is formed on the gate electrode 209 and the semiconductor substrate 200 during the above-described wet etching process.
Of the active region and the field oxide film 202 are prevented from being damaged. As described above, when the spacer 218 is removed, only the etching protection layer 216 remains on the upper surface and the side surface of the gate electrode 209 to have a uniform thickness.

As described above, when the spacer 218 is removed, the width between the gate electrodes 209 is widened and the gate electrode 2 is removed.
It is possible to secure the critical dimension of the base surface of the contact hole formed between the holes 09.

As shown in FIG. 17, after removing the spacer 218 as described above, silicon nitride (Si) is formed on the entire surface of the gate electrode 209 and the semiconductor substrate 200.
A nitride such as N) is deposited to a thickness of about 300 Å or more to form the etch stop layer 224.

In a subsequent process, the etching stop layer 224 is formed by etching an interlayer insulating film deposited thereon to form a borderless contact hole from the surface of the semiconductor substrate 200 adjacent to the field oxide film 202 to a part of the surface of the field oxide film 202. Has a role of preventing a part of the field oxide film 202 made of the same or similar material as the interlayer insulating film from being etched together.

In this embodiment, since the etching protection layer 216 remaining under the etching stop layer 224 is formed of oxide, in order to sufficiently prevent the recess of the field oxide film 202 during the contact hole etching process, The etch stop layer 224 should be formed to a thickness of about 300Å or more.

As shown in FIG. 18, the etching stop layer 2 is formed.
24 on the oxide, for example, BPSG (Boro-Pho
sposilicate glass) or PSG
(PhosphoSilicate glass) is deposited by plasma-excited chemical vapor deposition (PECVD) to a thickness of about 3000 to 10000Å to form an interlayer insulating film 2.
26 is formed. At this time, an etch back or a chemical mechanical polishing (CMP) process may be further performed to flatten the surface of the interlayer insulating film 226.

A photoresist pattern (not shown) defining a region where a contact hole is formed is formed on the interlayer insulating film 226 through a photolithography process.
Then, using the photoresist pattern as an etching mask, a mixed gas having an etching selectivity of 10 to 15: 1 for the interlayer insulating film 226 made of oxide to the etching stop layer 224 made of nitride is used. The interlayer insulating film 226 is etched by the dry etching process. After that, the photoresist pattern is removed, and the etching stopper layer 224 exposed by using the interlayer insulating film 226 as an etching mask and the etching protection layer 2 therebelow.
16 is dry-etched.

Then, the first contact hole 2 exposing the surface of the semiconductor substrate 200 between the gate electrodes 209.
28 a and the field oxide film 202, a second contact hole 228 b for borderless contact is formed to expose the surface of the semiconductor substrate 200 and a part of the surface of the field oxide film 202.

As described above, according to the second embodiment of the present invention, the etching protection layer 216 provided for removing the spacer 218 for LDD is formed of silicon oxide (Si).
By forming it with an oxide such as O ₂ ).
The blocking effect of the drain ion implantation can be prevented and the electrical characteristics of the transistor can be improved.

The embodiment of the present invention has been described in detail above, but the present invention is not limited to this, and the idea and the spirit of the present invention are deviated from those having ordinary knowledge in the technical field to which the present invention belongs. Without departing from the invention, modifications or variations could be made.

[0071]

According to the present invention, a spacer for embodying an LDD structure is formed on a sidewall of a gate electrode formed on a semiconductor substrate, and a spacer is formed using the spacer to form a high concentration source / drain region. The spacers are removed to secure a region where a contact hole is formed between the gate electrodes. After that, an etch stop layer and an interlayer insulating film for protecting the field oxide film during the borderless contact process are sequentially formed on the entire surface of the resultant product, and this is etched to form a contact hole.

Therefore, it is possible to prevent the etching stop layer formed between the gate electrodes from being formed thicker than the etching stop layer formed on the field oxide film. It is possible to prevent the contact hole exposing the surface of the semiconductor substrate between the electrodes from becoming not-open.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a method of forming a contact hole of a semiconductor device according to a conventional method.

FIG. 2 is a cross-sectional view illustrating a method of forming a contact hole of a semiconductor device according to a conventional method.

FIG. 3 is a cross-sectional view illustrating a method of forming a contact hole of a semiconductor device according to a conventional method.

FIG. 4 is a cross-sectional view illustrating a method of forming a contact hole of a semiconductor device according to a conventional method.

FIG. 5 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating a method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

FIG. 7 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

FIG. 8 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

FIG. 10 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

FIG. 11 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

FIG. 12 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating the method of forming a contact hole in a semiconductor device according to the first embodiment of the present invention.

FIG. 14 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

FIG. 15 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

FIG. 16 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

FIG. 17 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

FIG. 18 is a sectional view illustrating a method of forming a contact hole in a semiconductor device according to a second embodiment of the present invention.

[Explanation of symbols]

100, 200 Semiconductor substrate 102,202 Field oxide film 104, 204 Gate oxide film 109, 209 Gate electrode 112,212 Low concentration source / drain area 114 buffer layer 116, 216 Etching protection layer 118,218 Spacer 122,222 High concentration source / drain area 124, 224 Etching stop layer 126, 226 interlayer insulating film 128a, 228a First contact hole 128b, 228b Second contact hole

Continued front page    F-term (reference) 4M104 AA01 BB01 BB40 CC05 DD04                       DD07 DD08 DD09 DD15 DD16                       DD17 DD18 DD19 DD26 DD34                       DD65 EE05 EE12 EE14 EE17                       FF14 HH12 HH14 HH20                 5F033 HH04 HH28 HH29 HH30 LL04                       MM07 PP19 QQ04 QQ08 QQ09                       QQ10 QQ11 QQ19 QQ21 QQ25                       QQ28 QQ37 QQ48 QQ65 QQ73                       RR04 RR05 RR06 RR08 RR14                       RR15 SS10 SS13 SS15 TT02                       TT08 WW02 XX01 XX02 XX03                       XX04

Claims (27)

[Claims] 1. A semiconductor substrate having an active region and a field region separated by a field oxide film, a plurality of gate electrodes formed on the active region of the semiconductor substrate, and the gate electrode having a spacer-free structure. hand,
An etching protection layer formed on the gate electrode and the semiconductor substrate to protect the gate electrode and the semiconductor substrate from an etching process for widening the width between the gate electrodes, and the field formed by borderless contact formation. Formed so as to form a space for forming a first contact hole between the gate electrodes, which are stacked on the etching protection layer to prevent the recess of the oxide film and are widened by the gate electrode without the spacer. An etching stopper layer, a first contact hole formed on the etching stopper layer and penetrating the etching protection layer and the etching stopper layer to expose the surface of the semiconductor substrate between the gate electrodes, and the field oxide film. Surface of adjacent semiconductor substrate and part of the field oxide film And an interlayer insulating film having a second contact hole for borderless contact that penetrates the etching protective layer and etch stop layer to expose the surface, without forming a spacer between the gate electrodes,
The first to obtain an expanded width between the gate electrodes
A semiconductor device, wherein the etching protection layer and the etching stop layer protect the gate electrode and the semiconductor substrate during an etching process for forming a contact hole and the second contact hole. 2. The semiconductor device according to claim 1, further comprising a high-concentration source region and a drain region in the active region of the semiconductor substrate. 3. The thickness of the etching stopper layer formed on the field oxide film and the thickness of the etching stopper layer formed between the gate electrode and the gate electrode are uniform. Semiconductor device. 4. The semiconductor device according to claim 1, wherein the etching stopper layer contains a material similar to the material of the interlayer insulating film for preventing formation of a recess on the field oxide film. 5. The semiconductor device according to claim 1, wherein the etching protection layer contains a material similar to the material of the etching stop layer. 6. The semiconductor device according to claim 5, wherein the etching protection layer is made of nitride. 7. The etching protection layer is formed to a thickness of about 50 to 300Å, and the etching stop layer is formed to a thickness of 100 to 300.
7. The semiconductor device according to claim 6, wherein the semiconductor device is formed to have a thickness of about 1000Å. 8. The method according to claim 5, further comprising a buffer layer made of an oxide formed between the semiconductor substrate including the gate electrode and the etching protection layer.
The semiconductor device according to. 9. The etching protection layer contains an oxide.
The semiconductor device according to claim 1, which has a thickness of about 0 to 300Å. 10. The semiconductor device according to claim 9, wherein the etching stop layer is formed to have a thickness of 300 Å or more. 11. Forming a plurality of gate electrodes on the active region of a semiconductor substrate separated into an active region and a field region by a field oxide film, and forming an etching protection layer on the gate electrode and the semiconductor substrate. Forming, forming a spacer made of a material having an etching selection ratio with the etching protection layer on the etching protection layer on both sides of each gate electrode, and using the gate electrode including the spacer as a mask. Source / drain ion implantation using the same, removing the spacer to secure a space for forming the first contact hole between the gate electrodes, and borderless contact on the front surface of the resultant structure. Forming an etch stop layer to prevent depressions in the field oxide layer due to formation And forming an interlayer insulating film on the etching stop layer, and sequentially etching the interlayer insulating film, the etching stop layer and the etching protection layer to expose a surface of the semiconductor substrate between the gate electrodes. Forming a second contact hole for borderless contact exposing a surface of the semiconductor substrate adjacent to the first contact hole and the field oxide film and a partial surface of the field oxide film;
Forming a borderless contact between the field region and the active region. 12. The step of forming the interlayer insulating film includes the step of forming an interlayer insulating film having a material similar to the material of the etching stop layer for preventing formation of a recess on the oxide film. The method of forming a contact hole of a semiconductor device according to claim 11. 13. The step of forming the etch stop layer is such that the thickness of the etch stop layer formed on the field oxide layer and the thickness of the etch stop layer formed between the gate electrode are uniform. The method of forming a contact hole of a semiconductor device according to claim 11, further comprising the step of forming an etching stop layer. 14. The method of claim 11, wherein the etching protection layer is made of oxide and the spacer is made of polysilicon. 15. The step of removing the spacer has an etching selectivity ratio of oxide to polysilicon of 30: 1.
15. The method of forming a contact hole in a semiconductor device according to claim 14, wherein the etching is performed by wet etching using the etchant. 16. The etching protection layer is 50 to 300 Å
15. The method of forming a contact hole in a semiconductor device according to claim 14, wherein the contact hole is formed with a thickness of about a certain degree. 17. The etch stop layer comprises a nitride of 300.
The method for forming a contact hole in a semiconductor device according to claim 11, wherein the contact hole is formed by vapor deposition to have a thickness of Å or more. 18. A step of forming a plurality of gate electrodes on the active region of a semiconductor substrate separated into an active region and a field region by a field oxide film, and an etching protection layer on the gate electrode and the semiconductor substrate. Forming a spacer on the etching protection layer on both sides of each gate electrode, the spacer including a material having an etching selection ratio to the etching protection layer; and using the gate electrode including the spacer as a mask. Source / drain ion implantation, removing the spacers, forming an etch stop layer on the entire surface of the resultant structure, including a material similar to the material of the etch protection layer, Forming an interlayer insulating film on the etching stopper layer, and forming the interlayer insulating film, the etching stopper layer, and And the etching protection layer are sequentially etched to expose a surface of the semiconductor substrate between the gate electrodes and a surface of the semiconductor substrate adjacent to the field oxide film and a part of the surface of the field oxide film. Forming a second contact hole for borderless contact, and forming a borderless contact between the field region and the active region, the method for forming a contact hole in a semiconductor device. 19. The contact of the semiconductor device as claimed in claim 18, further comprising the step of performing LDD ion implantation using the gate electrode as a mask before the step of forming the etching protection layer. Hole formation method. 20. The step of forming the etching protection layer includes the step of depositing a nitride on the gate electrode and the semiconductor substrate, and the step of forming the spacer includes depositing an oxide on the etching protection layer. The method of forming a contact hole of a semiconductor device according to claim 18, further comprising: 21. The nitride is SiN, SiON and B.
21. The method for forming a contact hole in a semiconductor device according to claim 20, wherein the method is any one selected from the N group. 22. The semiconductor according to claim 20, wherein the step of removing the spacer is performed by wet etching using an etchant having an etching selectivity of nitride to oxide of 20: 1. Method for forming contact hole of device. 23. The step of forming the etching protection layer includes the step of forming an etching protection layer having a thickness that can reduce a blocking effect of performing the source / drain ion implantation process. The method of forming a contact hole of a semiconductor device according to claim 20. 24. The method of claim 23, wherein the etching protection layer has a thickness of about 50 to 300Å. 25. The method of claim 18, wherein the step of forming the etch stop layer includes the step of forming an etch stop layer having a thickness of about 100 to 1000Å. . 26. The method may further include the step of depositing an oxide on the gate electrode and the semiconductor substrate to form a buffer layer before the step of depositing the nitride to form the etching protection layer. The method of forming a contact hole of a semiconductor device according to claim 20. 27. The method of forming a contact hole in a semiconductor device according to claim 26, wherein the buffer layer is formed to have a thickness of about 30 to 100Å.