JP2000048560A - Semiconductor circuit - Google Patents

Abstract

[PROBLEMS] To reduce the number of refreshes in both a self-refresh mode and a normal operation mode in a DRAM / logic embedded LSI with a small-scale circuit. SOLUTION: The refresh interval timer 4 is a DRAM.
2 to output a timing signal indicating the refresh timing. Refresh address generating means 5 outputs an address signal indicating memory cell group 1. The phase counter 6 outputs a reference signal corresponding to the cycle of the address indicating the memory cell group 1. The phase storage table 7 stores refresh information including, for example, a refresh skip number for each memory cell group 1 and outputs a refresh information signal corresponding to the refresh information. The phase comparing means 8 outputs a refresh execution request signal when the refresh information signal and the reference signal correspond to each other. Refresh control means 9 receives a refresh execution request signal and performs a refresh operation on memory cell group 1 indicated by the address signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRAM (Dyn).
BACKGROUND OF THE INVENTION The present invention relates to a semiconductor circuit in which an amic RAM) and a logic circuit are mounted on a single chip, and more particularly to a semiconductor circuit that controls refresh of a DRAM.

[0002]

2. Description of the Related Art With the miniaturization of semiconductor devices, it has become possible to integrate processors, memories or other circuits on a single chip. Circuit and DRAM 1
It has become possible to combine them on one chip.

[0003] Since the memory cells (storage elements) of the DRAM are composed of capacitors, the individual memory cells are small.
A DRAM has an advantage that a chip area can be greatly reduced as compared with a case where an SRAM (Static RAM) is mounted, but a charge holding data in a capacitor of a memory cell as time passes. However, there is a disadvantage in that data is lost due to discharge.
Note that the time during which the memory cell can retain information is referred to as data retention time.

By the way, in order to cope with the problem that data in a memory cell is lost, an operation called refresh for holding data in a memory cell is required.
Refresh is a series of operations in which data of a DRAM consisting of memory cells arranged in a matrix is read all at once (rows), detected by a sense amplifier, and the detected value is written to the read memory cells. Name. During the refresh operation, reading or writing to the DRAM cannot be performed. In the following,
A set of memory cells in which data is held by one refresh operation among the memory cells included in the DRAM is referred to as a memory cell group.

[0005] The conventional refresh control for a general-purpose DRAM is performed in a normal operation mode in which the DRAM can be read or written from the outside.
In a data holding mode such as at the time of battery backup, a DRAM controller provided outside the DRAM performs a refresh control circuit provided inside the DRAM. Hereinafter, the refresh mode performed by the refresh control circuit in the DRAM is referred to as a self-refresh mode. Since it takes time to switch between these modes, even if there is an external request to read or write data to the DRAM during the self-refresh mode,
This request will not be accepted immediately.

Regarding the data retention time of a DRAM, there is a large variation between the data retention times of individual memory cells, and the number of memory cells having a short data retention time contained in one DRAM is very small (Iwata). Also, "
In spite of "Circuit technology for realizing ultra-low holding current DRAM", IEICE report, ICD95-50), refresh is performed at the same cycle for all memory cell groups. Refreshing is performed with excessive frequency for a memory cell group that does not include a memory cell having a short data retention time.

In order to prevent power consumption due to excessive refreshing, Japanese Patent Laid-Open Publication No. 4-31794 discloses a technique of measuring the data retention time of each memory cell group of a DRAM in advance and determining the memory retention time in accordance with the data retention time. A method has been proposed in which the number of refreshes is reduced by setting a refresh cycle for each cell group, that is, by setting the number of times the refresh execution is skipped for each memory cell group.

[0008]

However, the method of reducing the number of refreshes disclosed in Japanese Patent Application Laid-Open No. 4-31794 discloses a counter (221) for counting the number of times the refresh execution is skipped, and a counter for counting the number of refreshes. Since it is necessary to provide a comparing means (211) for comparing the output count signal (22a) with the maximum mask numerical signal (31a) for each memory cell group, there is a problem that the circuit scale becomes enormous.

A DRAM / logic mixed LSI is
The aim is to dramatically improve the processing performance of the logic part by combining DRAM and logic circuits on a single chip with a high memory bandwidth. (Iwashita et al., "Overview of the Next-Generation General-Purpose Microprocessor Architecture PPRAM" ”, Information Processing Society of Japan Research Report, ARC-113-1,
August 1998). However, in a DRAM / logic embedded LSI, refresh and access to the DRAM performed by the logic circuit compete with each other, so that access to the DRAM is waited for every refresh.
If the refresh is performed frequently, the time required for accessing the DRAM becomes longer, and the problem that the processing capability of the logic circuit is restricted is highlighted.

In the conventional DRAM, since the refresh cycle is predetermined to a predetermined length as an external specification, measurement is performed after a measure for repairing a defect (ie, replacement of a memory cell group) is performed. If there is at least one memory cell group whose data retention time does not satisfy the predetermined length in spite of performing the defect remedy,
The DRAM including the memory cell group is treated as a defective product. However, even if the DRAM has a small number of memory cells whose data retention time is less than the predetermined length,
If there is no problem in the function and performance of the whole AM / logic embedded LSI, it may be possible to treat it as a good product.
For example, even if the data holding time of one memory cell group is short, if accesses are not concentrated on the one memory cell group, the one memory cell group is refreshed more frequently than the other memory cell groups. , The overall power consumption increases, and the refresh and DR of the logic circuit
Increasing contention with access to the AM is not particularly problematic.

In view of the above, it is an object of the present invention to provide a DRAM / logic-mixed LSI in which the number of refreshes in both the self-refresh mode and the normal operation mode can be reduced by a small-scale circuit. A second object is to make it possible to change the minimum refresh cycle after the LSI is created.

[0012]

In order to achieve the first object, a semiconductor circuit according to the present invention has a plurality of memory cell groups each including a plurality of memory cells, and a DRAM for storing data. A logic circuit for accessing data stored in the DRAM, a timing signal generating means for outputting a timing signal indicating a refresh timing for the DRAM, and a timing signal output from the timing signal generating means, An address signal generating means for updating an address indicating a group and outputting an address signal; and receiving an input of an address signal output from the address signal generating means. A reference signal generating means for outputting a reference signal according to the cycle; Refresh information storage for storing refresh information including the number of refresh skips, refresh cycle or data holding time, and outputting a refresh information signal according to the refresh information when an address signal output from the address signal generating means is input. Means for receiving a refresh information signal output from the refresh information storage means and a reference signal output from the reference signal generation means, and generating a refresh execution request signal when the input refresh information signal corresponds to the reference signal. Request signal generating means for outputting, and arbitration of competition between a refresh execution request signal output from the request signal generating means and an access signal to the DRAM from the logic circuit, and an address signal generating means for selecting the refresh execution request signal. From And a refresh control means for performing a refresh operation for the memory cell group indicated by the address signal force.

According to the semiconductor circuit of the present invention, each time an address indicating a memory cell group is updated, a reference signal generating means for outputting a reference signal according to the cycle of the address;
Refresh information storage means for storing refresh information including a refresh skip count, a refresh cycle or a data holding time for each memory cell group, and outputting a refresh information signal corresponding to the refresh information; Request signal generating means for outputting a refresh execution request signal when the information signal and the reference signal correspond to each other, the request signal generating means determines the number of refresh skips for each cycle of the memory cell group address A refresh execution request signal can be output according to refresh information including a refresh cycle or a data holding time.

In the semiconductor circuit according to the present invention, it is preferable that the reference signal generating means includes one counter.

In the semiconductor circuit of the present invention, it is preferable that the reference signal generating means comprises a plurality of counters.

In order to achieve the second object, in the semiconductor circuit of the present invention, it is preferable that the timing signal generating means has means for changing a time interval for outputting the timing signal.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A semiconductor circuit according to a first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a part of a circuit necessary for executing refresh in a semiconductor circuit in which a DRAM and a logic circuit according to the first embodiment are mixed.

As shown in FIG. 1, the semiconductor circuit diagram according to the first embodiment has a plurality of memory cell groups 1 each of which includes a plurality of memory cells and stores data.
It has a RAM 2 and a logic circuit 3 for accessing data stored in the DRAM 2.

The refresh interval timer 4 as a timing signal generator outputs a timing signal indicating the timing of refreshing the DRAM 2.

The refresh address generating means 5 as the address signal generating means includes a refresh interval timer 4
When the timing signal output from the memory cell is input, the address indicating the memory cell group 1 is updated and an address signal (refresh column address signal) is output.

Phase counter 6 as reference signal generating means
Receives the input of the address signal output from the refresh address generating means 5, and every time the update of the address indicating the memory cell group 1 completes (that is, the address update for all the memory cell groups 1 constituting the DRAM 2 is performed). Each time one round), a reference signal corresponding to the address round is output.

The phase storage table 7 as refresh information storage means stores refresh information including the number of refresh skips, the refresh cycle or the data holding time for each memory cell group 1 and the refresh address generation means 5. When the address signal output from the terminal is input, the refresh information signal corresponding to the refresh information is output.

Phase comparing means 8 as request signal generating means
Receives a refresh information signal output from the phase storage table 7 and a reference signal output from the phase counter 6, and outputs a refresh execution request signal when the input refresh information signal and the reference signal correspond to each other. I do.

The refresh control means 9 arbitrates between the refresh execution request signal output from the phase comparison means 8 and the access from the logic circuit 3 to the DRAM 2 and, when selecting the refresh execution request signal, from the refresh address generation means 5 For the memory cell group 1 indicated by the output address signal, a refresh operation including reading of data from the memory cell group 1 and writing of the read data to the memory cell group 1 is performed. Specifically, the refresh control unit 9 is configured to output a refresh execution request signal and a DRAM from the logic circuit 3.
2 arbitrates with an access request to the access request 2 and selects a selection signal based on the arbitration result.
Output to 0. The arbitration is not limited to the case where one of the requests is selected when the refresh execution request and the access request conflict, and the case where the right is given to the request when the refresh execution request does not conflict with the access request. Including. In other words, this means granting a right to the request regardless of whether there is a conflict.

The selector 10 includes a refresh control means 9
The address signal output from the refresh address generating means 5 or the logic circuit 3 based on the selection signal from
And outputs the selected column address signal to the DRAM 2. In this case, the refresh control means 9
When there is only one of the access request to the AM 2 and the refresh control request to the DRAM 2, the request is executed, and when the access to the DRAM 2 is performed, the refresh control request to the DRAM 2 is issued. After the access to the DRAM 2 is completed, the refresh control for the DRAM 2 is performed. When the access control to the DRAM 2 is requested while the refresh control for the DRAM 2 is being performed, the access to the DRAM 2 is performed after the refresh control for the DRAM 2 is completed. When a request for access to the DRAM 2 and a request for refresh control for the DRAM 2 are simultaneously generated, the access to the DRAM 2 is performed after the refresh control for the DRAM 2 is performed.

Hereinafter, each of the above-described units constituting the semiconductor circuit diagram according to the first embodiment will be specifically described.
In the first embodiment, a distributed refresh method in which the memory cell group 1 is refreshed at predetermined time intervals is employed.

The refresh interval timer 4 has a counter updated by a clock as a timer for clocking, and outputs a timing signal every time a predetermined time elapses.

When the timing signal output from the refresh interval timer 4 is input, the refresh address generator 5 updates the address indicating the memory cell group 1 and outputs an address signal (refresh column address signal). This address signal also has a function of indicating a field of the phase storage table 7.

Here, the predetermined time interval at which the timing signal is output from the refresh interval timer 4 will be described with reference to FIGS.

FIG. 2 shows a first method for obtaining a predetermined time interval at which the timing signal is output.
As shown in FIG. 2, the maximum delay time between the refresh request and the execution of the refresh (the maximum delay time from when the refresh request is made until the refresh is performed) is determined from the data holding time defined as the external specification of the DRAM 2. A predetermined time interval can be obtained by dividing the time obtained by subtracting (value) by the number of memory cell groups 1. The reason for this is that the data holding time of the memory cell group having the shortest data holding time is divided by the number of memory cell groups 1 without considering the delay time from when the refresh request is made until the refresh is executed. If the logic circuit 3 accesses the DRAM 2 when there is a refresh execution request, the refresh target is set while the refresh execution is delayed. This is because the data of the memory cell group 1 may be volatilized.

FIG. 3 shows a second method for obtaining a predetermined time interval at which the timing signal is output. By the way, the refresh control means 3 performs the refresh control on the memory cell group 1 in accordance with the timing signal output from the refresh interval time counting means 4, but if the logic circuit 3 is accessing the DRAM 2 at this time, the refresh control is performed. The means 3 arbitrates the access of the logic circuit 3 after the access to the DRAM 2 is completed, and thereafter performs the refresh control on the memory cell group 1. Therefore, as shown in FIG. 3, at least the time obtained by dividing the data holding time of the memory cell group having the shortest data holding time by the number of memory cell groups 1 among all the memory cell groups constituting the DRAM 2 is shown. One DRAM
By reducing the access time to 2, a predetermined time interval is obtained. The reason for this is obtained by dividing the data holding time of the memory cell group having the shortest data holding time by the number of memory cell groups 1 without considering the access time of the logic circuit 3 to the DRAM 2. If the time is set to a predetermined time interval, if the logic circuit 2 is accessing the DRAM 1 when the refresh control unit 3 attempts to perform the refresh, the refresh execution is delayed, so that the refresh execution is delayed. Cell group 1 to be refreshed while
This is because there is a risk that the data of this will volatilize.

The refresh interval timer 4 is based on a predetermined time interval obtained by the second method shown in FIG.
, The refresh interval time counting means 4 is initialized every time the refresh control means 3 actually controls the refresh, and a new time is started. Updates the address indicating the memory cell group 1 and outputs an address signal.

The phase counter 6 receives the input of the address signal output from the refresh address generating means 5,
Every time the address indicating the memory cell group 1 is updated,
A reference signal corresponding to the cycle of the address is output.

The phase storage table 7 stores refresh information for each memory cell group 1 and, when an address signal output from the refresh address generating means 5 is input, outputs a refresh information signal corresponding to the refresh information.

The phase comparing means 8 receives the input of the reference signal output from the phase counter 6 and the refresh information signal output from the phase storage table 7, and when the input reference signal and the refresh information signal correspond to each other. To output a refresh execution request signal.

Here, the reference signal output from the phase counter 6, the refresh information stored in the phase storage table 7, and the specific method by which the phase comparison means 8 compares the reference signal with the refresh information signal will be described. An example in which the number of cell groups 1 is four will be described with reference to FIG.

The phase counter 6 outputs b00 as a reference signal in the first cycle of the address, outputs b01 in the second cycle of the address, b10 in the third cycle of the address, and outputs b10 in the third cycle of the address. B11 is output at the round, and the above-mentioned reference signal is repeatedly output at each round of the address thereafter.

The phase storage table 7 stores b00 (meaning the number of skips: 0 or the refresh cycle: 1) for the first memory cell group having the address of A0 as the refresh information, and stores the address of A1. B11 (the number of skips:
3 or refresh cycle: 4)
B for the third memory cell group having the address of A2
00 (number of skips: 0 or refresh cycle: 1)
And the fourth memory cell group having the address of A3 stores b01 (means skip count: 1 or refresh cycle: 2).
The stored refresh information is output as a refresh information signal. The number of skips means the number of skips without performing a refresh when a refresh request is issued to a corresponding memory cell group, and the skip cycle means On the other hand, it means a cycle in which refresh is executed when a refresh request is issued. For example, the meaning of storing the number of skips: 1 for the fourth memory cell group is as follows. That is, since the timing signal is output according to the shortest data holding time, the data holding time of the fourth memory cell group is changed to the memory cell group having the shortest data holding time (for example, the first or third memory cell group). If it is more than twice the data retention time of the cell group),
For the fourth memory cell group, execution of refresh is 1
There is no danger of data volatilizing even if skipped twice.

The specific method by which the phase comparing means 8 compares the reference signal with the refresh information signal is as follows. That is, the phase comparison means 8 outputs the reference signals (b00, b01, b10, b11) output from the phase counter 6.
And a refresh information signal (b00, b11, b00, b01) output from the phase storage table 7, and when both satisfy a predetermined relationship, a refresh execution request signal is output.

For example, in the example shown in FIG. 4, a memory cell group (A0 and A0) having b00 as a refresh information signal
For (2), a refresh execution request signal is output irrespective of the type of reference signal, and for the memory cell group (A3) having b01 as the refresh information signal, refresh is performed when the reference signal is b00 or b10. An execution request signal is output, and a refresh execution request signal is output to the memory cell group (A1) having b11 as the refresh information signal when the reference signal is b00. Therefore,
In the first cycle where the reference signal of b00 is output, A
In the second cycle in which the refresh execution request signal is output to the memory cell groups 0, A1, A2, and A3 and the reference signal b01 is output, the refresh execution request signal is output to the memory cell groups A0 and A2. A signal is output and b10
In the third round in which the reference signal is output, A0, A
In the fourth cycle in which the refresh execution request signal is output to the memory cell group A2 and A3 and the reference signal b11 is output, the refresh execution request signal is output to the memory cell groups A0 and A2. You. As a result, the memory cell group of A0 has the skip count of 0, the memory cell group of A1 has the skip count of 3, the memory cell group of A2 has the skip count of 0, and the memory cell group of A3 has the skip count of 1. Become.

In this manner, the execution of the refresh can be skipped according to the data holding time of each memory cell group, so that the number of times the refresh is executed can be reduced.

As long as each memory cell group is refreshed in a cycle in which the data holding time is satisfied, the reference signal output from the phase counter 6 and the phase storage table 7
And the combination of the reference signal and the refresh information signal for the phase comparison means 8 to output the refresh execution request signal can be appropriately set.

In the first embodiment, the DRA
Although the number of memory cell groups 1 forming M2 is four, if the number of memory cell groups 1 increases or decreases, the address of the address signal output from the refresh address generation means 5 according to the increase or decrease of the memory cell group 1. Length and phase storage table 7
This can be handled by increasing or decreasing the number of fields.

In the first embodiment, the case where the number of times of skipping the refresh is 0, 1, and 3 has been described. However, the number of skips is 2 ^N -1 (N is an integer of 0 or more). Can be selected from among the values included in. In this case, the word length of the reference signal output from the phase counter 6, the word length of the refresh information signal output from the phase storage table 7, and the reference signal and the refresh signal for the phase comparison means 8 to output the refresh execution request signal. The combination with the information signal may be changed according to the number of skips.

In the first embodiment, the phase storage table 7 has the number of skips or the refresh cycle as the refresh information, but may have a data holding time instead. In this case, if the data holding time is rounded, it becomes easy to set the combination of the reference signal and the refresh information signal for the phase comparison means 8 to output the refresh execution request signal.

Further, in the first embodiment, the distributed refresh method in which refresh is performed on the memory cell group 1 at a predetermined time interval is employed, so that one refresh request is executed by one refresh request. This is performed on the memory cell group.
Refresh may be performed on a plurality of memory cell groups 1 determined in advance in response to a refresh request. In this case, the refresh address generation means 5 updates the address indicating the memory cell group 1 by the number of memory cell groups 1 to be refreshed, and outputs an address signal.

In the method disclosed in Japanese Patent Application Laid-Open No. 4-34794, since a clock counting means and a comparing means are provided for each memory cell group, for example, several hundred to several thousand memory cells are provided by the number of memory cells constituting the DRAM. Since the clock counting means and the comparing means are required, the circuit scale must be increased. On the other hand, according to the first embodiment, the phase counter 6 and the phase comparing means 8 each having a circuit scale substantially equal to that of the clock counting means and the comparing means disclosed in Japanese Patent Application Laid-Open No. 4-34794 are provided one by one.
Since only one phase storage table 7 is provided as a whole, the circuit scale as a whole is significantly reduced.

(Second Embodiment) A semiconductor circuit according to a second embodiment of the present invention will be described below with reference to FIGS.

FIG. 5 shows a circuit of a portion necessary for executing refresh in a semiconductor circuit in which a DRAM and a logic circuit according to the second embodiment are mounted together. In the second embodiment, a memory cell group 1, a DRAM 2, a logic circuit 3, a refresh interval timer 4 as a timing signal generator, and a refresh as an address signal generator having functions similar to those of the first embodiment. Since there are provided an address generation means 5, a phase storage table 7 as a refresh information storage means, a refresh control means 9 and a selector 10, the same reference numerals as in the first embodiment are used and the description is omitted.

As a feature of the second embodiment, each time an address signal output from the refresh address generating means 5 is input and the address indicating the memory cell group 1 is updated, the address corresponding to the cycle of the address is updated. A first phase counter 6A and a second phase counter 6B as reference signal generating means for outputting a reference signal, and a first phase counter 6A
Reference signal output from the second phase counter 6
Receiving the second reference signal output from B and the refresh information signal output from the phase storage table 7,
Phase comparison means 8 is provided as a request signal generation means for outputting a refresh execution request signal when the input refresh information signal and the first reference signal or the second reference signal correspond to each other.

As shown in FIG. 6, the first phase counter 6
A outputs b00 as the first reference signal in the first cycle of the address, b01 in the second cycle of the address, and b01 in the third cycle of the address, as in the first embodiment. b1
0 is output, b11 is output in the fourth cycle of the address, and these first reference signals are repeatedly output for each cycle of the address. Also, the second phase counter 6B outputs b00 as the second reference signal in the first cycle of the address,
B01 is output in the second cycle of the address, b10 is output in the third cycle of the address, and these second reference signals are repeatedly output for each cycle of the address. That is, the second phase counter 6B outputs b00 in the fourth cycle of the address without outputting b11.

The phase storage table 7 stores b00 (meaning the number of skips: 0 or the refresh cycle: 1) for the first memory cell group having the address of A0 as the refresh information, and stores the address of A1. B11 (meaning the number of skips: 3 or the refresh cycle: 4) is stored for the second memory cell group having the following, and b10 (the number of skips: 2 or refresh cycle: 3), and b01 (the number of skips: 4) for the fourth memory cell group having the address of A3
1 or a refresh cycle: 2), and outputs the stored refresh information as a refresh information signal.

The phase comparing means 8 supplies a refresh information signal to the first memory cell group having the address A0, the second memory cell group having the address A1 and the fourth memory cell group having the address A3. And the first reference signal, and for the third memory cell group having the address of A2, the refresh information signal is compared with the second reference signal.

For example, in the example shown in FIG. 6, the first memory cell group (A
0), a refresh execution request signal is output irrespective of the type of the first reference signal. For the second memory cell group (A1) having b11 as the refresh information signal, the first reference signal is output. When the signal is b00, a refresh execution request signal is output, and b1 is used as a refresh information signal.
For the third memory cell group (A2) having 0, the second
When the first reference signal is b00 or b10, the refresh execution request signal is output when the first reference signal is b00 or b10, and the fourth memory cell group (A3) having b01 as the refresh information signal is refreshed. Outputs an execution request signal.

Therefore, in the first cycle in which b00 is output as the first reference signal and the second reference signal, the phase comparison means 8 refreshes the memory cell groups A0, A1, A2, and A3. In the second cycle in which the execution request signal is output and the reference signal of b01 is output as the first reference signal and the second reference signal, the refresh execution request signal is output to the memory cell group of A0. In the third cycle in which the reference signal b10 is output as the first reference signal and the second reference signal, a refresh execution request signal is output to the memory cell groups A0 and A3, and the first reference signal is output. In the fourth cycle in which b11 is output and b00 is output as the second reference signal, A0, A
In the fifth cycle in which the refresh execution request signal is output to the memory cell group No. 2 and b00 is output as the first reference signal and b01 is output as the second reference signal, A0, A1,. A refresh execution request signal is output to the memory cell group A3. As a result, the memory cell group of A0 has a skip count of 0, the memory cell group of A1 has a skip count of 3, the memory cell group of A2 has a skip count of 2, and the memory cell group of A3 has a skip count of 1. Become. That is, in the first embodiment, the number of skips is of three types: 0, 1, and 3, but in the second embodiment, the first cycle of the address is again performed in the fourth cycle of the address. Since the second phase counter 6B for outputting the second reference signal returning to the above is provided, the number of skips is four, that is, 0, 1, 2, and 3.

In the second embodiment, a first phase counter 6A and a second phase counter 6B are provided as reference signal generating means, and the number of skips is 0, 1 and 2.
Although the number of phase counters is set to two or three, the number of phase counters as reference signal generating means is increased, and the phase comparing means 8 outputs the reference signals output from the plurality of phase counters and the phase storage table 7. If the refresh execution request signal is output by comparing the output with the refresh information signal to be output, the type of the number of skips can be increased.

According to the second embodiment, as compared with the first embodiment, the number of skips or the type of the skip period can be increased simply by increasing the number of phase counters by one or more. .

The number of necessary phase counters is determined by the number of skips or the number of types of skip cycles. In a 64 Mb DRAM, at most ten refresh cycles are sufficient (Youji Idei).
Other, Dual-Period Self-RefreshScheme for Low-Power D
RAM's with On-Chip PRAM Mode Register, IEEE Journa
l of Solid-State Circuits 1998), usually, any one of 1 to 8 is sufficient as the number of refresh skips or the type of cycle. When the number of refresh skips or the cycle type is 8, the number of refresh skips is seven (1, 2,.
3,..., 7), therefore, four phase counters are sufficient. Specifically, 1, 2, 4, and 8 times the cycle, that is, 0 times (b000), 1 time (b001), 3 times (b011), and 7 times (b111)
1st phase counter (b111
000), and a cycle three or six times, that is, twice (b010), 5
Phase counter for counting the number of skips (b101)
(initialized to b000 in b101), 5 times cycle, ie 4 times (b100)
And a fourth phase counter for counting the number of skips of seven times the cycle, that is, six times (b110).
It is only necessary to provide four phase counters composed of the above phase counters (initialized to b000 in b110).

(Third Embodiment) A semiconductor circuit according to a third embodiment of the present invention will be described below with reference to FIG.

FIG. 7 shows a part of a circuit necessary for executing refresh in a semiconductor circuit in which a DRAM and a logic circuit according to the third embodiment are mounted. In the third embodiment, a memory cell group 1, a DRAM 2, a logic circuit 3, a refresh address generator 5 as an address signal generator, and a phase as a reference signal generator having the same functions as those of the first embodiment. A counter 6, a phase storage table 7 as refresh information storage means,
Since it includes the phase comparison means 8, the refresh control means 9, and the selector 10 as request signal generation means, the first
The description is omitted by attaching the same reference numerals as those of the embodiment.

As a feature of the third embodiment, the refresh interval timer 4 as a timing signal generator is
After the DRAM / logic embedded LSI is manufactured, a refresh interval time can be set, and a refresh interval storage means 4a for storing the set refresh interval time is provided. As the refresh interval storage means 4a, for example, f
used ROM, EPROM, EEPROM, flu
A sh memory, an FPGA, a RAM, or the like can be used.

The refresh interval timer 4 includes:
By setting the range of the value counted by the counter, which is a timer, by the refresh interval storage means 4a, it is possible to set the time interval of the timing signal output from the refresh interval timer means 4. For example, a counter that counts up is used as a counter included in the refresh interval timer 4, and the upper limit of the count value counted by the counter is set in the refresh interval storage 4a, and every time the count reaches the upper limit. By initializing the counter, the time interval measured by the refresh interval timer 4 can be freely set. Also, a counter that performs a countdown is used as a counter included in the refresh interval timer 4.
The same function can be realized even if the count value is initialized to the value set in the refresh interval storage means 4a every time the count value becomes the minimum value.

The value set in the refresh interval storage means 4a, and hence the time interval of the timing signal output from the refresh interval timer means 4, are the first method or the second method described in the first embodiment. Set by.

According to the third embodiment, it is possible to set the time interval of the timing signal output from the refresh interval timer 4 as the timing signal generator after the production of the DRAM / logic embedded LSI. The time interval of the timing signal can be set in accordance with the data retention time of the memory cell group 1 having a very short data retention time among the memory cell groups 1 constituting the DRAM 2. Therefore, for example, even when there is a memory cell group in which the data retention time measured after the defect relief is performed does not satisfy the predetermined length, the time interval of the timing signal is set in accordance with the data retention time of the memory cell group. Since it can be set, it is possible to avoid a situation where the DRAM including the memory cell group is treated as a defective product.

[0066]

According to the semiconductor circuit of the present invention, the request signal generating means is provided for every cycle of the address of the memory cell group, for the number of refresh skips, refresh cycle, or data holding stored for each memory cell group. A refresh execution request signal is output according to the refresh information consisting of time, and the refresh control means performs a refresh operation on the corresponding memory cell group based on the refresh execution request signal output from the request signal generation means. Therefore, the refresh operation is not performed on the memory cell group that does not correspond, that is, the memory cell group that does not need refreshing in relation to the data holding time, so that the refresh operation can be reduced with a small-scale circuit. The refresh control means arbitrates a conflict between the refresh execution request signal output from the request signal generation means and the access signal to the DRAM from the logic circuit, so that the refresh control means operates in both the normal operation mode and the self refresh mode. , The refresh operation can be reduced with a small-scale circuit.

Accordingly, the power consumption can be reduced with the reduction in the refresh operation, and the competition between the refresh operation and the access of the logic circuit to the DRAM is reduced. , The decrease in the processing capability of the logic circuit can be reduced.

In the semiconductor circuit according to the present invention, if the reference signal generating means comprises one counter, the reference signal can be output with a simple configuration, so that the refresh operation can be reduced with a very small circuit.

In the semiconductor circuit according to the present invention, if the reference signal generating means comprises a plurality of counters, the time interval of the timing signal indicating the refresh timing for the DRAM can be reduced, so that refresh is not necessary in relation to the data holding time. The refresh operation can be finely deleted from the memory cell group. Therefore, when only a discrete cycle (for example, 1, 2, 4, 8) can be provided, there is no cycle that exactly satisfies the data holding time of a certain memory cell group, so that refreshing must be performed with an unnecessary short cycle. That situation can be avoided. In addition, by using this function, it is possible to care for a memory cell group having a short data retention time, so that an effect of preventing defective DRAM / logic embedded LSI from being defective can be obtained.

In the semiconductor circuit of the present invention, if the timing signal generating means has means for changing the time interval for outputting the timing signal, the output from the timing signal generating means after the fabrication of the DRAM / logic embedded LSI. Since the time interval of the timing signal to be set can be set, the memory cell group having a short data holding time can be set by setting the time interval of the timing signal according to the data holding time of the memory cell group having a very short data holding time. It is possible to reduce the situation in which the included DRAM becomes defective, thereby improving the yield.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a main part of a semiconductor circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a first method applied to each embodiment of the present invention for setting a predetermined time interval at which a timing signal is output from a refresh interval timer.

FIG. 3 is a diagram illustrating a second method applied to each embodiment of the present invention for setting a predetermined time interval at which a timing signal is output from a refresh interval timer.

FIG. 4 is a diagram illustrating a method in which a phase comparison unit compares a reference signal and a refresh information signal in the semiconductor circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram of a main part of a semiconductor circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a method in which a phase comparison unit compares a reference signal and a refresh information signal in a semiconductor circuit according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of a main part of a semiconductor circuit according to a third embodiment of the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell group 2 DRAM 3 logic circuit 4 refresh interval timer 4a refresh interval storage 5 refresh address generator 6 phase counter 7 phase storage table 8 phase comparator 9 refresh controller 10 selector

Claims (4)

[Claims] 1. A DRAM that has a plurality of memory cell groups each including a plurality of memory cells and stores data.
A logic circuit that accesses data stored in the DRAM; a timing signal generator that outputs a timing signal indicating a refresh timing for the DRAM; and a timing signal output from the timing signal generator. Address signal generating means for updating an address indicating the memory cell group and outputting an address signal; receiving an input of an address signal output from the address signal generating means, and updating the address indicating the memory cell group by one cycle A reference signal generating means for outputting a reference signal corresponding to a cycle of an address, a refresh skip count for each of the memory cell groups,
Refresh information storage means for storing refresh information comprising a refresh cycle or data holding time, and outputting a refresh information signal according to the refresh information when an address signal output from the address signal generation means is input; Receiving a refresh information signal output from the refresh information storage means and a reference signal output from the reference signal generating means, and outputting a refresh execution request signal when the input refresh information signal corresponds to the reference signal; Request signal generating means for arbitrating contention between a refresh execution request signal output from the request signal generating means and an access signal to the DRAM from the logic circuit, and selecting the refresh execution request signal when selecting the refresh execution request signal. Signal generation Semiconductor circuit, characterized in that and a refresh control means for performing a refresh operation to the memory cell group showing address signals output from the stage. 2. The semiconductor circuit according to claim 1, wherein said reference signal generating means comprises one counter. 3. The semiconductor circuit according to claim 1, wherein said reference signal generating means comprises a plurality of counters. 4. The semiconductor circuit according to claim 1, wherein said timing signal generating means has means for changing a time interval for outputting said timing signal.