JPH0793971A - Dynamic semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] To provide a dynamic semiconductor memory device capable of omitting an unnecessary short cycle refresh operation for each address and reducing refresh power consumption. In a dynamic semiconductor memory device that requires a refresh operation of a memory cell within a fixed pause time, a refresh address generation circuit 12 that generates a refresh address in a fixed cycle and a pause time within the refresh address are the shortest ( (T _REFmax ), the refresh address is set to T _{REFmax to} N × T _REFmax ,
N × T _{REFmax to} N ′ × T _REFmax , N ′ × T _REFmax to 3
Omitting unnecessary refresh cycles for memories 16 and 17 that classify and store them into types, and for refresh addresses that belong to a class in which the pause time is twice or more longer than the shortest refresh address based on the classified and stored information. And a circuit for doing so.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device which requires a refresh operation, and more particularly to a dynamic semiconductor memory device which has reduced power consumption by eliminating unnecessary refresh.

[0002]

2. Description of the Related Art A dynamic semiconductor memory device (DRA
In M), charges are stored in the memory cell capacitor to store information. However, since the storage electrode of this capacitor is not completely insulated from the surroundings, the stored charge amount decreases with time. Therefore, it is necessary to rewrite (refresh) data in the memory cell before a certain period of time has passed. FIG. 16A shows the state of leakage of charges from the cell capacitor. Also, FIG.
6 (b) shows the change with time of the accumulated charge, and the readable limit is the maximum period at which data can be taken out without being destroyed.

In the formation of DRAM memory cells, not all cells are exactly the same, but there is a slight variation in each cell, and there is a variation in the readable limit of each cell. In the conventional DRAM, since the read limit for each refresh address cannot be stored or set, the refresh operation is performed for all the addresses according to the refresh cycle of the shortest refresh address included in the chip. Therefore, depending on the refresh address, re-refreshing is performed at a cycle sufficiently shorter than the cycle required for the address not to cause a read failure, resulting in extra refresh time and power consumption.

[0004]

As described above, in the conventional dynamic semiconductor device, the bit having the worst pause characteristic in the chip is prevented from causing a read failure.
All refresh addresses are refreshed at a cycle in which that bit does not cause a defect. That is, unnecessary refresh operation is performed, and extra power consumption and refresh time are consumed. Also, when the DRAM controller chip performs a refresh operation, the refresh cycle for each refresh address is the same, so extra power consumption and refresh time are consumed.

The present invention has been made in consideration of the above circumstances, and an object thereof is to make it possible to omit an unnecessary refresh operation of a short cycle for each address, thereby reducing refresh power consumption. An object is to provide a dynamic semiconductor memory device to be obtained.

[0006]

In order to solve the above problems, the present invention employs the following configurations. That is, according to the present invention, in a dynamic semiconductor memory device that requires a refresh operation of a memory cell within a fixed pause time, a refresh address generation circuit for generating a refresh address in a fixed cycle and a pause time within the refresh address are the shortest. Means for classifying and storing the refresh address into two or more types according to the bit of, and for the refresh address belonging to the class in which the refresh time is twice or more longer than the shortest refresh address based on the classified and stored information. , And means for omitting refreshing in unnecessary cycles.

The following are preferred embodiments of the present invention. (1) Set the refresh address to the shortest pause time T
_From the bit of _REFmax to N × T _REFmax (first classification),
The pause time is classified into two such as N × T _REFmax or more (second classification), only the refresh addresses belonging to the first classification are stored in the memory, and the refresh addresses of the first classification stored in this memory are stored. Refresh is performed each time a refresh signal is input, and N × is applied to the second-class refresh address not stored in the memory.
_Omit refreshes other than the T _REFmax period. Note that N is a positive integer of 2 or more. (2) Set the refresh address to the shortest pause time T
_From the bit of _REFmax to N × T _REFmax (first classification),
The pause time is classified into _three from N × T _REFmax to N ′ × T _REFmax (second classification) and pause time is N ′ × T _REFmax or more (third classification), and the first and second classifications. Only the refresh address belonging to the above is stored in the memory, the refresh address for the first classification is refreshed every time a refresh signal is input, and the refresh address for the second classification is refreshed in a cycle other than N × T _REFmax. , And for refresh addresses of the third classification, refresh other than N ′ × T _REFmax periods is omitted. (3) A means for switching the function of the circuit omitting the refresh operation should be provided. (4) Must have a circuit that allows the refresh cycle to be set arbitrarily. (5) In the DRAM control circuit, a function that allows the control circuit to set an individual refresh cycle for each refresh address by storing the pause characteristics as 1-bit or more data in the internal or externally connected memory Equipped with.

[0008]

With the structure of the present invention, the pause characteristic is T _REFmax.
When an external refresh signal is input in a cycle of T _REFmax for a refresh address more than N times, the internal refresh signal is generated once every N times so that unnecessary refresh operation is not performed in the chip. Therefore, the refresh current during standby can be reduced. In addition, since the memory that stores a plurality of refresh addresses classified according to the pause characteristics may store some refresh addresses instead of all refresh addresses, it is possible to reduce the memory capacity and the number of write operations. is there.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a DRAM according to a first embodiment of the present invention.
3 is a block diagram showing a schematic configuration of FIG. 11 in the figure is / RA
A refresh controller that compares the rising edges of S and / CAS to determine whether or not a refresh is performed, 12 is a self-refresh counter that automatically generates a refresh address internally, 13 is a refresh cycle, and refresh cycles NT _REFmax , N ′ T _REFmax , N ”
Refresh cycle counter that outputs T _REFmax , 1
Reference numeral 4 is an internal address bus, and 15 is an external address bus.

16 is the pause time from T _REFmax to N × T
_A first nonvolatile memory for storing a refresh address of _REFmax , 17 has a pause time of N × T _REFmax to N ′ ×
A second nonvolatile memory that stores a refresh address of T _REFmax (N ′> N), 18 is a comparator that compares the refresh address from the first memory 16 and the refresh address from the self-refresh counter 12, and 19 is a memory 17 Is a comparator that compares the refresh address from the self refresh counter 12 with the refresh address from the self refresh counter 12.

Reference numeral 21 is a row address buffer, and a refresh address is input to the row address buffer 21 from the internal address bus 14 and the external address bus 15. The row address buffer 21 receives the internal address bus 1 according to the output CBR of the refresh controller.
4 and the external address bus 15 are switched, and the row decoder 22 is operated according to the contents of the output.

_{Reference numeral} 23 is an AND gate for inputting the output of the comparator 19 and the refresh cycle N × T _REFmax ,
24 is the output of the comparator 18, the refresh cycle N '
× T _REFmax , an OR gate for inputting the output of the AND gate 23, 25 is an AND gate for inputting the output of the internal RAS and the OR gate 24, and the output of the AND gate 25 and the internal address selection signal CBR are the row address buffer 21.
Has been entered in.

In such a configuration, the pause characteristic of each memory cell of the DRAM is measured, and the refresh address from the pause time T _REFmax to N × T _REFmax is first stored in the non-volatile memory 16 as the first classification due to the difference in the pause characteristics. Memorize and pause time from N × T _REFmax to N ′ × T
The refresh address of _REFmax is stored as a second classification in another non-volatile memory 17 that specifies that classification, and all addresses are divided into several classifications. Here, the third classification, which is a refresh address having a pause time longer than N ′ × T _REFmax , is not stored in the memory, but the first and second
Since the classification is stored, the rest will be known as the third classification.

In the mode in which an address is automatically generated in the DRAM, the counter is conventionally set to 1 for each refresh signal.
Although all addresses are refreshed one by one in sequence, this method does not generate an internal refresh signal for an internal refresh address having a refresh unnecessary cycle by referring to an internally generated address with the address classification memory.

Specifically, when the refresh address of the pause time T _REFmax to N × T _REFmax is output from the self-refresh counter 12, the comparator 1
The output enable 0 of 8 becomes "H", and this is the OR gate 2
4 and the AND gate 25 are input to the row address buffer 21, so that each refresh address is refreshed.

When the self-refresh counter 12 outputs a refresh address having a pause time of N × T _REFmax to N ′ × T _REFmax , the output enable 1 of the comparator 19 becomes “H”, which is passed through the AND gate 23. It is input to the OR gate 24. AND gate 23
Another input is for a refresh cycle to be output for each N × T _REFmax period, except in N × T _REFmax-cycle refresh is omitted.

When the refresh address whose pause time is longer than N '× T _REFmax is output from the self-refresh counter 12, neither of the outputs of the comparators 18 and 19 becomes "H", but every N' × T _REFmax cycle. The refresh cycle N ', which is output to the OR gate 24, is input to the OR gate 24. Therefore, the internal refresh operation is always performed in N '* T _REFmax cycle.

As described above, according to this embodiment, unnecessary refresh operations can be omitted in the chip, and refresh power consumption during standby can be reduced. Also, instead of storing all refresh addresses classified by pause time, the pause time is N ′ ×
Since there is no need to store refresh addresses longer than T _REFmax, there is an advantage that the memory capacity and the write operation can be reduced.

FIG. 2 shows a D according to the second embodiment of the present invention.
It is a block diagram which shows schematic structure of RAM. Note that FIG.
The same parts as those of the above are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, the non-volatile memory 2 for setting the output of the refresh cycle counter 13 to an arbitrary base number
6, and if necessary, a circuit for setting the method shown in the first embodiment or the normal full address T _REFmax cycle refresh method is provided in the chip. Then, after performing a normal pause test, calculate the refresh address division method that can minimize the refresh power consumption,
Based on this, the all address refresh method is set in the same mode as the conventional method, or the abbreviated refresh method shown in the present invention is set in the nonvolatile memory A, and N × T _REFmax is set to minimize power consumption due to variation in pause characteristics. , N ′ × T
_REFmax , N ″ × T _REFmax, etc. are set in the non-volatile memory.

As described above, according to the present embodiment, since the optimum setting suitable for each chip characteristic can be performed, the function of the circuit shown in the first embodiment can be utilized to the maximum extent. If the nonvolatile memory is not set, the conventional normal operation is performed.

FIG. 3 shows a D according to the third embodiment of the present invention.
It is a block diagram which shows schematic structure of RAM. Note that FIG.
The same parts as those of the above are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, the refresh cycle division for each refresh address is set as K-bit data for each refresh address, so that the optimal cycle for each refresh address is divided with a small number of memories and a minimum number of writes. The

Specifically, a nonvolatile memory 27 for storing K-bit data for each refresh address,
A logic circuit 28 for determining whether refresh is necessary or not is provided in different cycles of 2 ^K divisions.

As an example of the operation method of this embodiment, when K is set to 2, four categories can be classified for each refresh address, and a determination logic circuit for determining an ENABLE signal which is an internal refresh operation instruction corresponding to each category. An example of the truth table is shown in (Table 1) below (Table 1) in parentheses indicates the setting of the non-volatile memory and is (fuse1 setting, fuse2 setting).

[0026]

[Table 1]

Here, the "set fuse" value is set to 1 when writing is performed, and, for example, in this circuit,
The cycle division in which both fuse1 and fuse2 are written is (1,
The refresh address of 1) outputs ENABLE = 1 which enables the refresh operation in the cycle of T _REFmax . In this example, the default value of the cycle section for each address is (0, 0), and the sections having the smallest number of addresses belonging to the cycle section are (1, 1), (1, 0),
Set as (0,1) and (0,0). As a result, the number M of actual writing operations is: M = 2 × {number of refresh addresses in (1,1) section} + 1 × {number of refresh addresses in (1,0) section} + 1 × {(0,1) section Refresh address number}, and many divisions can be efficiently performed with the minimum write amount.

A specific example of a circuit that implements this method is shown below. 4 and 5 show the entire circuit.
A circuit 31 for detecting RAS, a counter circuit 32 for adding the number of times to generate a refresh address, a shift register circuit 33 for setting the output of only an address corresponding to the refresh address to a high level, and a refresh cycle of each refresh address are stored. Fuse (f
user's set 34 (34a, 34b), the determination circuit 35 (35a, 35b) for determining whether the fuse of the refresh address whose output is high level in the circuit 33 is in the cut or non-cut state, and the fuse The refresh cycle determination circuit 36 for permitting the refresh operation for the refresh cycle determined by the above, and the refresh cycle counter 37 for counting the refresh cycle.

When a refresh operation command based on an internal address, that is, a CAS signal is input prior to the RAS signal from the outside of the DRAM, the circuit 31 detects it and outputs the pulse signal C.
Generate BR. Each time a CBR pulse signal is input, 1 is added to the address counter 32 to sequentially generate refresh addresses. The output Co of the first stage of the address counter 32 is subjected to waveform conversion necessary for driving the shift register circuit 33, and PHYa, / PHYa, PHYb,
After being set to / PHYb, it is input to the shift register circuit 33. Here, a circuit for converting the waveform of Co is shown in FIG.
Shown in. Further, a specific configuration of the shift register circuit 33 is shown in FIG.

The output signal Qk of the shift register circuit 33 is transferred to the output of the next stage every time the CBR pulse signal is input. Here, at the start of use, the reset signal (RS)
Thus, the address counter is set to 0, and a reset circuit is built in so that only the first two stages of the shift register become high level. The input signal RS required for this reset,
FIG. 6 shows a circuit for obtaining RSb, RS2, RS2b.
It shows in (b). By doing so, the output of the shift register becomes high level only in the adjacent two stages among all the stages, so that there can always be a one-to-one relationship between the output of the refresh address counter and the output of the shift register. become. Then, by making the final stage input of the shift register the first stage input, this one-to-one relationship can be made permanent because it is repeated.

All the outputs Qk of the shift register are input to the fuse cut / non-cut determination circuit 35 of the corresponding address. The specific configuration of the determination circuit 35 is shown in FIGS. The determination circuit 35 sets the node 1 or the node 2 to the high level during standby, and when the determination operation command CLKref becomes the high level, the adjacent two stages of the shift register output are at the high level. , When the fifth stage is selected in FIG. 8 is shown as nodes 3 and 4) so that the fuse is not blown so that the nodes 0 and 1 are at the low level,
If it is disconnected, the high level is maintained (however, the hold pMOS transistors Tr1 and Tr2 of the precharge circuit are
Drive capacity of the nMOS transistor groups 1 and 2 is sufficiently smaller than that of the nMOS transistor groups 1 and 2. When the decision operation command CLKref falls to low level, the level of this node is held in the latch circuit section of the decision circuit. The blown states of the n fuses provided for each address are output in this manner.

On the other hand, an m-stage (ACT) circuit is added to the final stage output of the address counter, and 1 is added every time the number of refresh instructions reaches all refresh addresses (4k in this example), and the count number. Is a circuit that outputs a multiple of the basic refresh cycle. This is referred to as a refresh cycle cow 37.

This output (C12 to C16) is input to the period setting block A1, block A2, and block A3, and the period setting fuse group (a1 to b5, c1 to d5, e1 to e1).
Each digit part of f5) is cut so as to be a multiple of the target basic refresh cycle, and for example, a1, a2, b3, b4, in order for the block A1 to have an output of four times the basic cycle.
Set by cutting the fuse of b5.

When the refresh cycle is classified into the shortest T _REFMAX , the signal for permitting the internal refresh operation is obtained as the logical product of the outputs ENBLG0 and ENBLG1 of the decision circuit 35 by the circuit shown in FIG. 9A. for that reason,
Every refresh cycle Internal refresh signal ENABLE
The refresh operation is performed each time 1 is output. Next, a circuit for outputting a signal ENABL4 for permitting internal refresh at a cycle N ″ × T _REFMAX to all refresh addresses regardless of the output of the determination circuit 35 is shown in FIG.
It shows in (b). By setting the period setting fuse group (a1 to b5) by this circuit, all refresh addresses obtain a signal for permitting the internal refresh operation in this period. By doing so, the refresh _operation classified into N ″ × T _REFMAX having the longest refresh cycle is refreshed for N ″ × T _REFMAX cycle with the default value set in the circuit 34.

On the other hand, the refresh cycle is T _REFMAX <N ×
_Regarding T _REFMAX , N ′ × T _REFMAX <N ″ T _REFMAX , the output of the determination circuit 35 and the set value of the refresh cycle must correspond to each other, and the circuits of the block B1 of FIG. 10 and the block B2 of FIG. Thus, the refresh cycle and the output of the determination circuit 35 are logically ANDed.

In FIG. 9A, / ENBLG0, /
A logic circuit that outputs a signal that permits an internal refresh operation in a T _REFMAX cycle based on _ENBLG1 . FIG. 9B shows
A circuit that permits the refresh operation with the longest cycle N ″ × T _REFMAX for all addresses.
Output (/ ENBLG0, ENBLG1) is (1, 1)
And a circuit (block B1) for permitting the internal refresh operation in the refresh cycle N × T _REFMAX and N × T
_REFMAX cycle setting circuit (block A2). FIG. 11 is a circuit (block B2) that permits the internal refresh operation in the refresh cycle N ′ × T _REFMAX when the output (ENBLG0, / ENBLG1) of the determination circuit 35 is (1, 1).
And N ″ × T _REFMAX cycle setting circuit (block A3). FIG. 9C is a circuit that outputs ENABLE when any one of the ENABLE1 to 4 signals is selected.

In this way, ENBLG is changed according to the blown state of the fuse assigned to each refresh address.
The output of 0 to / ENBLG1 is determined, and accordingly, the ENABLE of the refresh cycle determination circuit 36 for each cycle setting is set.
The i (i = 1 to 4) signal output unit 36a outputs ENABLE1 to ENABLE4 permitting the refresh operation. The output is the ENA of the refresh cycle determination circuit 36.
The BLE signal output section 36b collects and outputs the final internal refresh permission ENABLE.

Here, the method will be described by taking the case where the refresh cycle is divided into two sections according to the pause characteristic as an example. As shown in FIG. 12A, since the variation in the pause time is caused by the variation in the process, the number of refresh addresses with a short pause time and the number of refresh addresses with a long pause time are small and many refresh addresses are small. Pause time is concentrated in the center. Focusing on this, in order to minimize the number of blown fuses, which leads to a decrease in yield due to defective blown fuses, circuits for refresh cycle setting are divided according to the following policy.

First, since the number of refresh addresses having a short pause time is small, they are allotted to the refresh of the basic refresh cycle by cutting all two setting fuses. At that time, both of the outputs of the determination circuit 35 are at the low level, so that the output is as shown in FIG. Next, in the present example of n = 2, there are two refresh cycle settings by cutting one fuse. In FIG. 12A, there are few refresh addresses having a long pause time, so that it can be selected, but even if the refresh cycle of a small number of refresh addresses is lengthened, there is not much improvement effect.

Therefore, as shown in FIG. 12B, the refresh cycle is set for the required minimum number of refresh addresses in order from the one having the shortest pause time. Then, in a refresh cycle required by a majority of refresh addresses, a circuit such as a block B in FIG. 9B is used so that the refresh is performed regardless of the fuse setting. If the circuit that can set the refresh cycle according to this policy is used, the number of fuse cutting operations can be reduced,
Power consumption can be improved by efficient refresh operation.

When two types of refresh cycles, T _RM and T _RM ′, are adopted as shown in FIG. 12B, the number of refresh addresses causing a defect in the region (I) causes a defect in the region (II). Less than number. Therefore, the refresh address when the refresh cycle setting fuse is in the cut state is T _RM.
The refresh address in which the refresh and fuse are not cut is a logic circuit in which the refresh of T _RM ′ is selected (the number of defective refresh addresses in the region (I) << the number of defective refresh addresses in the region (II)).

The circuit shown in FIG. 13 selects whether the internal omission function of the refresh operation is effectively operated for the refresh address having a long pause time according to this method. If the fuse in the circuit is blown, the DRAM
The reset operation at startup sets the SSM node to a high level.

FIG. 14 shows an embodiment of a circuit for speeding up the output from the shift register circuit and the fuse read determination circuit in the present invention. Since the shift register circuit and the determination circuit need to be downsized, the operating speed becomes low. In order to compensate for this, several stages of latch circuits capable of high-speed reading are added between the determination circuit 5 and the refresh cycle determination circuit 36, and the data of the fuses that are sequentially read are taken into this latch circuit in advance to respond to the external refresh command. In this case, the circuit 36 determines whether the internal refresh operation is executed or omitted by using the output ENBLGx signal of the latch circuit.

FIG. 15 shows a block diagram of a circuit to be added when the refresh address is increased in the present invention. While the refresh address increases, it is necessary to add the upper bits of the counter necessary for generating the address. Then, the refresh cycle setting fuse circuit 34 for the increased refresh address and its read determination circuit 35 are added in parallel to the existing shift register circuit. Since the circulation of the shift register can be determined from the additional upper digit of the refresh address counter according to the number of refresh operations, ENBLGx to be referenced can be selected in the refresh cycle determination circuit 36.

[0045]

As described above, according to the present invention, the unnecessary refresh operation of a short cycle for each address is omitted, so that the refresh power consumption of the entire device can be significantly reduced and this function is added. The increase in area can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a DRAM according to a first embodiment.

FIG. 2 is a block diagram showing a schematic configuration of a DRAM according to a second embodiment.

FIG. 3 is a block diagram showing a schematic configuration of a DRAM according to a third embodiment.

FIG. 4 is a diagram showing a specific circuit example for implementing the first to third embodiments.

FIG. 5 is a diagram showing a specific circuit example for implementing the first to third embodiments.

FIG. 6 is a diagram showing a shift register input clock waveform shaping circuit.

FIG. 7 is a diagram showing a specific configuration of a shift register circuit.

FIG. 8 is a diagram showing a specific configuration of a fuse cut / non-cut judgment circuit.

FIG. 9 is a diagram showing a specific configuration of a refresh cycle setting circuit and a determination circuit.

FIG. 10 is a diagram showing a specific configuration of a refresh cycle setting circuit.

FIG. 11 is a diagram showing a specific configuration of a refresh cycle setting circuit.

FIG. 12 is a diagram showing the relationship between the occurrence rate of defective read addresses and the pause time.

FIG. 13 is a diagram showing a circuit for determining whether or not to enable a refresh circuit function at reset.

FIG. 14 is a block diagram of an additional circuit according to an increase in refresh address.

FIG. 15 is a block diagram of a circuit added between a determination circuit required for high-speed reading of fuse settings and a refresh determination circuit.

FIG. 16 is a diagram showing leakage of charges from a memory cell capacitor of a DRAM. The figure which shows the time-dependent change of the electric charge in a cell capacitor.

[Explanation of symbols]

 11 ... Refresh controller 12 ... Self-refresh counter 13 ... Refresh cycle counter 14 ... Internal address 15 ... External address bus 16, 17, 26, 27 ... Non-volatile memory 18, 19 ... Comparator 28 ... Logic circuit

Claims (1)

[Claims] 1. In a dynamic semiconductor memory device which requires a refresh operation of a memory cell within a fixed pause time, a refresh address generation circuit for generating a refresh address at a fixed cycle and a pause time within the refresh address are the shortest. Means for classifying and storing the refresh address into two or more types according to the bit of, and for the refresh address belonging to the class in which the refresh time is twice or more longer than the shortest refresh address based on the classified and stored information. A dynamic semiconductor memory device comprising: means for omitting an unnecessary cycle refresh.