JP2002269981A - Semiconductor memory device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor memory device capable of appropriately performing a refresh operation on a required refresh target. A memory element includes a memory element and a control terminal that receives an external signal for inputting a control signal to the memory element, and a part of the memory element according to a combination of input signals from the control terminal. , A command signal for performing a refresh operation is generated, and the command signal causes the refresh operation to be performed on a part of the memory elements 4 to 7 to be refreshed among the memory elements.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic memory device comprising a DRAM having a self-refresh circuit.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a DRAM having a self-refresh circuit according to the prior art.
FIG. 8 is a timing chart showing the self-refresh timing in the prior art. In the figure, 1 is C
Command data for recognizing a command by taking in the state of each input pin at the rising edge of the LK signal, 2 is a self-refresh timer for generating an active signal for boosting the word line at a fixed period, and 3 is active (Ac
tive) A self-refresh counter that counts up a row address to be refreshed every time a signal is generated. 4 to 7 are memory cells for storing data, 4 is bank [1], 5 is bank [2], 6
Constitutes the bank [3], and 7 constitutes the bank [4].

The conventional self-refresh circuit shown in FIGS. 7 and 8 does not have a function of designating a region (address) for performing refresh. For this reason, unnecessary addresses are consumed because the refresh operation is also performed for unnecessary addresses.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of accurately performing a refresh operation on a required refresh target.

[0005]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a memory element; and a control terminal for receiving an external signal for inputting a control signal to the memory element. A command signal for performing a refresh operation on a part of the memory element is generated by a combination of signals, and the refresh operation is performed on a part of the memory element to be refreshed among the memory elements by the command signal. Things.

In the semiconductor memory device according to the second invention,
A memory element and a register integrated with the memory element, a command signal for performing a refresh operation on a part of the memory element is stored in the register, and a command signal of the memory element stores the command signal of the register. The refresh operation is performed on a part of the memory elements to be refreshed.

In a semiconductor memory device according to a third aspect,
A memory element, a control terminal for receiving an external signal for inputting a control signal to the memory element, and a register integrated with the memory element. A command signal for performing a refresh operation on a part is generated and stored in the register, and a refresh operation is performed on a part of the memory element to be refreshed among the memory elements by the command signal of the register. Things.

In a semiconductor memory device according to a fourth aspect,
A memory element, a control terminal for receiving an external signal for inputting a control signal to the memory element, and a register integrated with the memory element, wherein the register performs a refresh operation on a part of the memory element. An address designation signal to be performed is stored, and the refresh operation is performed only in a specific area to be refreshed among the memory elements by the address designation signal of the register.

In a semiconductor memory device according to a fifth aspect,
A memory element, a start address register and a stop address register integrated with the memory element, and a start address designation signal for performing a refresh operation on a part of the memory element in the start address register; Storing a stop address designating signal for performing a refresh operation on a part of the memory element in the stop address register, and using the start address register and the stop address register as the refresh target among the memory elements by the address designating signal. The refresh operation is performed only in a specific area.

In a semiconductor memory device according to a sixth aspect,
A memory element, a control terminal receiving an external signal for inputting a control signal to the memory element, an address terminal receiving an external address signal, and a register integrated with the memory element, An address designating signal for performing a refresh operation on a part of the memory element is generated by a combination of input signals by a terminal and an address terminal, and stored in the register, and the address designation signal of the register refreshes the memory element. The refresh operation is performed only for a specific area as a target.

In a semiconductor memory device according to a seventh aspect,
A memory element, a control terminal receiving an external signal for inputting a control signal to the memory element, an address terminal receiving an external address signal, a register integrated with the memory element, A self-refresh timer integrally incorporated, generating an address designation signal for performing a refresh operation on a part of the memory element by a combination of input signals from the control terminal and the address terminal, and storing the address designation signal in the register; The refresh operation is performed only in a specific area to be refreshed in the memory element by the address designation signal of the register and an active signal generated at a predetermined cycle by the self-refresh timer.

In a semiconductor memory device according to an eighth aspect,
A memory element having a plurality of banks; and a control terminal receiving an external signal for inputting a control signal to the memory element, wherein a refresh operation is performed for each bank of the memory element by a combination of input signals from the control terminal. A command signal for bank selection for selecting whether to perform or not to execute is generated, and the bank selection command signal causes the refresh operation to be performed only for a specific bank to be refreshed among the memory elements. is there.

In a semiconductor memory device according to a ninth aspect,
A memory element having a plurality of banks; and a register integrated with the memory element. A bank selection command signal for selecting whether to perform a refresh operation on each bank of the memory element. The memory element is stored in the register, and the refresh operation is performed only in a specific area to be refreshed among the memory elements by the bank selection command signal of the register.

In a semiconductor memory device according to a tenth aspect of the present invention, a memory element having a plurality of banks, a control terminal for receiving an external signal for inputting a control signal to the memory element, and integrated with the memory element are provided. A bank selection command signal for selecting whether or not to perform a refresh operation for each bank of the memory element according to a combination of input signals from the control terminal, and storing the command signal in the register. The refresh operation is performed only for a specific bank to be refreshed among the memory elements by a bank selection command signal of the register.

In a semiconductor memory device according to an eleventh aspect of the present invention, a memory element having a plurality of banks, a control terminal for receiving an external signal for inputting a control signal to the memory element, and integrated with the memory element Registers and
A self-refresh timer integrated with the memory element, and a bank selection command for selecting whether or not to perform a refresh operation on each bank of the memory element by a combination of input signals from the control terminal. A signal is generated and stored in the register, and a command signal for bank selection of the register and an active signal generated at a predetermined cycle by the self-refresh timer are used for only a specific bank to be refreshed among the memory elements. The refresh operation is performed.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 First Embodiment A first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a configuration of a DRAM employing an improved self-refresh circuit according to the first embodiment. FIG. 2 is a timing chart showing self-refresh timing in the first embodiment. FIG. 3 is an explanatory diagram showing a command signal according to the first embodiment.

Referring to FIG. 1 showing the structure of a DRAM employing the improved self-refresh circuit in the first embodiment, a description will be given in comparison with the conventional self-refresh circuit shown in FIG. The improvement is that an area for performing self-refresh can be specified. The means for refreshing only the area specified by the register will be described with reference to FIGS. In FIG. 1, 1 is CLK
Command data for recognizing a command by taking in the state of each input pin which constitutes a control terminal for receiving an external signal at a rising edge of a CLK signal which is a clock signal introduced to a terminal, 2 is an active signal for boosting a word line Self-refresh timer generated at regular intervals,
Reference numeral 3 denotes a self-refresh counter that counts up a row address to be refreshed every time an active signal is generated. Reference numerals 4 to 7 denote memory elements composed of memory cells for storing data, 4 denotes a bank [1], 5 denotes a bank [2], 6 denotes a bank [3], and 7 denotes a bank [4]. , Respectively. 1
Reference numeral 3 denotes a start / stop address register for storing an area for performing a self-refresh, and reference numeral 14 denotes a self-refresh execution determination circuit for determining whether an address output from the self-refresh counter is an area for performing a refresh. is there.

Each of the input pins of the command decoder 1 receives a CLK signal, a / CS signal, a / RAS signal, a / CAS signal, a / WE signal, a CKE signal, and a control signal for controlling the memory cells 4 to 7 from the outside. And address signal A
0 to A11 and a register set command signal B
A0 and BA1 are input. The command decoder 1, self-refresh timer 2, self-refresh counter 3, start / stop address register 1
3, and the self-refresh execution determination circuit 14 are integrated together with the memory cells 4 to 7 on a common semiconductor chip and are incorporated in the same package.
This package contains CLK signal, / CS signal, / RA
Each input pin of the command decoder 1 for externally inputting the S signal, the / CAS signal, the / WE signal, and the CKE signal is provided as a control terminal.
Each input pin of the command decoder 1 for externally inputting A11 is provided as an address terminal, and each input pin of the command decoder 1 for externally inputting the register set command signals BA0 and BA1 is provided as a control terminal. Have been.

FIG. 2 shows the self-refresh timing according to the present invention. According to the present invention, a self-refresh mode register set command for setting an area for performing self-refresh in a register before executing the self-refresh command is added.

At the rising edge of the CLK signal, / CS =
/ RAS = / CAS = / WE = "L", CKE = "H"
If so, the mode register set command is established. In this case, if BA0 = 1 and BA1 = 0, it is recognized as a self-refresh mode register set command shown in FIG. 3 instead of a normal mode register set command, and the address set on the address pin is replaced with the start address register 13 in FIG. To be stored. BA0 = 0, BA1
If = 1, the address set on the address pin is
In the stop address register 13. The self-refresh execution determination circuit 14 of FIG. 1 compares the address output from the self-refresh counter 3 with the address of the start / stop address register 13, and if the address is within the range in which the self-refresh is executed, it is activated for each bank. Since the signal is generated, only the specified area can be refreshed. According to the above configuration, refresh can be selectively performed, so that power consumption can be suppressed. The invention is based on D
Although the RAM has been described, the present invention can also be applied to a system LSI incorporating a DRAM.

According to the first embodiment of the present invention, memory elements 4 to 7 comprising memory cells constituting banks [1] to [4] and external signals for inputting control signals to the memory elements A control terminal for receiving an external address signal, a register 13 integrated with the memory element, and a self-refresh timer 2 integrated with the memory element. An address designating signal for performing a refresh operation on a part of the memory element is generated by a combination of the input signals from the address terminals and stored in the register 13. The address designating signal of the register 13 and the self-refresh timer 2 are used for a predetermined operation. Of the memory elements by the active signal generated in the cycle of Since the refresh operation is performed only for a specific area to be refreshed, the memory elements 4 to 4 are generated by an address designation signal generated by a combination of input signals from the control terminal and the address terminal and stored in the register 13. 7, a semiconductor memory device capable of appropriately performing a refresh operation on any necessary refresh target can be obtained.

Embodiment 2 FIG. Second Embodiment A second embodiment of the present invention will be described with reference to FIGS. FIG. 4 shows a configuration of a DRAM employing an improved self-refresh circuit according to the second embodiment. FIG. 5 is a timing chart showing the self-refresh timing in the first embodiment. FIG. 6 is an explanatory diagram showing the contents of the mode register according to the first embodiment. In the second embodiment, the configuration other than the specific configuration described here has the same configuration as the above-described first embodiment and has the same operation.

Referring to FIGS. 4 to 6, a description will be given of a bank in which self-refresh is performed by a command generated by a combination of a DRAM control pin and an address pin. In FIG. 4, 1 is a command decoder for recognizing a command by taking in the state of each input pin at the rising edge of the CLK signal, 2 is a self-refresh timer for generating an active signal for boosting a word line at a fixed period, and 3 is A self-refresh counter that counts up a row address to be refreshed every time an active signal is generated. 4 to 7 are memory elements composed of memory cells for storing data, 4 is a bank [1], 5 is a bank [2], 6 is a bank [3],
Numeral 7 constitutes the bank [4]. 8 to 11 are AND circuits, and 12 is a self-refresh mode register.

FIG. 5 shows the timing in the second embodiment, and FIG. 6 shows the contents of the mode register 12. In the present invention, a self-refresh mode register set command for setting a bank for performing self-refresh in a register in advance is added as shown in FIG. According to the present invention, a bank to execute refresh is selected according to the setting of self-refresh mode register 12 shown in FIG. The command data is in the state of each input pin (“H” or
"L") to identify the command. / CS = / RAS = / CAS = / W at rising edge of CLK signal
If E = "L" and CKE = "H", the mode register set command is established. In this case, if BA0 and BA1 are both "H", it is recognized as a self-refresh mode register set command instead of a normal mode register set command, and the bank for performing self-refresh set on the address pin is stored in the internal register 12. I do. Thereafter, a selective refresh is realized by executing a self-refresh command at the timing shown in FIG.

In FIG. 6, when a self-refresh command is input, the self-refresh timer 2 generates an active signal at a constant cycle. The command data outputs bank [1], [2], [3] and [4] select signals in accordance with the setting of the self-refresh mode register 12. Since an AND signal is input with the active signal and each bank select signal as an input, the active signal is input only to the selected bank and the refresh is executed.

Although the present invention has been described with respect to the case where a bank for performing self-refresh is specified, a mode setting for switching the logic of the bank [1], [2], [3], [4] select signal is added to the cell mode register. By doing so, it is possible to specify a bank in which self refresh is not performed.

According to the second embodiment of the present invention, memory elements 4 to 7 having a plurality of banks [1] to [4].
A control terminal for receiving an external signal for inputting a control signal to the memory element, a register integrated with the memory element, and a self-refresh timer 2 integrated with the memory element, A bank selection command signal for selecting whether or not to perform a refresh operation for each bank of the memory element according to a combination of input signals from the control terminal is generated and stored in the register. The refresh operation is performed only for a specific bank to be refreshed among the memory elements 4 to 7 by a command signal for use and an active signal generated at a predetermined cycle by the self-refresh timer 2. Command signal and active signal , It is possible to obtain a semiconductor memory device capable of performing an accurate refresh operation per need refreshed.

[0028]

According to the first invention, a memory element and a control terminal for receiving an external signal for inputting a control signal to the memory element are provided, and the memory element is provided by a combination of input signals from the control terminal. A command signal for performing a refresh operation on a part of the memory elements is generated, and the command signal causes the refresh operation to be performed on a part of the memory elements to be refreshed among the memory elements. With the command signal generated by the combination of the signals, it is possible to obtain a semiconductor memory device that can appropriately perform a refresh operation on a required refresh target.

According to the second aspect, a memory element and a register integrated with the memory element are provided, and a command signal for performing a refresh operation on a part of the memory element is stored in the register. Since a refresh operation is performed on a part of the memory elements to be refreshed among the memory elements by the command signal of the register, the necessary refresh target can be accurately refreshed by the command signal stored in the register. A semiconductor memory device that can operate can be obtained.

According to the third aspect of the present invention, the control device includes a memory element, a control terminal for receiving an external signal for inputting a control signal to the memory element, and a register integrated with the memory element. A command signal for performing a refresh operation on a part of the memory element is generated by a combination of input signals from terminals and stored in the register, and a command signal of the register is used to specify a memory element to be refreshed among the memory elements. Since the refresh operation is performed on a part of the semiconductor memory device, a refresh operation can be properly performed for a required refresh target by a command signal generated by a combination of input signals from the control terminal and stored in the register. be able to.

According to the fourth aspect, the memory element, a control terminal for receiving an external signal for inputting a control signal to the memory element, and a register integrated with the memory element are provided. An address designation signal for performing a refresh operation on a part of the memory element, and performing a refresh operation only on a specific area to be refreshed in the memory element by the address designation signal of the register. Therefore, it is possible to obtain a semiconductor memory device capable of appropriately performing a refresh operation on a required refresh target by the address designation signal stored in the register.

According to the fifth aspect of the present invention, the memory device includes a memory element, a start address register and a stop address register integrated with the memory element, and the start address register performs a refresh operation on a part of the memory element. Storing a start address specifying signal for performing a refresh operation on a part of the memory element in the stop address register, and storing a stop address specifying signal for performing a refresh operation on a part of the memory element in the start address register and the stop address register. Since the refresh operation is performed only in a specific area to be refreshed among the memory elements by the signal, the start address register and the stop address register are updated in the start address register and the stop address register. The preparative addressing signals and the stop address signal, it is possible to obtain a semiconductor memory device capable of performing an accurate refresh operation per need refreshed.

According to the sixth aspect, a memory element, a control terminal for receiving an external signal for inputting a control signal to the memory element, an address terminal for receiving an address signal from the outside, and an integrated part with the memory element And an address designation signal for performing a refresh operation on a part of the memory element by a combination of input signals from the control terminal and the address terminal, and stores the address designation signal in the register. Since the refresh operation is performed only for a specific area to be refreshed among the memory elements by the address designation signal, an address generated by a combination of input signals by the control terminal and the address terminal and stored in the register is stored. Refresh required by specified signal It is possible to obtain a semiconductor memory device capable of performing an accurate refresh operation per elephant.

According to the seventh aspect, the memory element, a control terminal for receiving an external signal for inputting a control signal to the memory element, an address terminal for receiving an address signal from the outside, and an integrated part with the memory element Addressing for performing a refresh operation on a part of the memory element by a combination of input signals from the control terminal and the address terminal. A signal is generated and stored in the register, and only a specific area to be refreshed in the memory element is refreshed by the addressing signal of the register and an active signal generated at a predetermined cycle by the self-refresh timer. To make it work. The by the addressing signal and the active signal, it is possible to obtain a semiconductor memory device capable of performing an accurate refresh operation per need refreshed.

According to the eighth aspect, the memory device includes a memory element having a plurality of banks, and a control terminal for receiving an external signal for inputting a control signal to the memory element. Generating a bank selection command signal for selecting whether or not to perform a refresh operation on each bank of the memory element, and by using the bank selection command signal, only a specific bank to be refreshed among the memory elements; , The refresh operation can be performed. Therefore, a semiconductor memory device capable of accurately performing a refresh operation on a required refresh target can be obtained by a bank selection command signal generated by a combination of input signals from the control terminal.

According to the ninth aspect, there is provided a memory element having a plurality of banks, and a register integrated with the memory element. Whether the refresh operation is performed or not for each bank of the memory element Is stored in the register, and the bank selection command signal of the register causes the refresh operation to be performed only in a specific area to be refreshed among the memory elements. According to the present invention, a semiconductor memory device capable of appropriately performing a refresh operation on a required refresh target by a bank selection command signal stored in the register can be obtained.

According to the tenth aspect, a memory element having a plurality of banks, a control terminal for receiving an external signal for inputting a control signal to the memory element, a register integrated with the memory element, Generating a bank selection command signal for selecting whether or not to perform a refresh operation on each bank of the memory element according to a combination of input signals by the control terminal, storing the command signal in the register, storing the command signal in the register, The refresh operation is performed only for the specific bank to be refreshed among the memory elements by the bank selection command signal of the above, so that the bank selection generated by the combination of the input signals by the control terminal and stored in the register is performed. Required refresh target Can it is possible to obtain a semiconductor memory device capable of performing an accurate refresh operation.

According to the eleventh aspect, a memory element having a plurality of banks, a control terminal for receiving an external signal for inputting a control signal to the memory element, a register integrated with the memory element, A self-refresh timer integrated with the memory element,
A bank selection command signal for selecting whether or not to perform a refresh operation for each bank of the memory element according to a combination of input signals from the control terminal is generated and stored in the register. And the active signal generated at a predetermined cycle by the self-refresh timer causes the refresh operation to be performed only on a specific bank to be refreshed among the memory elements. And the active signal, it is possible to obtain a semiconductor memory device capable of appropriately performing a refresh operation on a required refresh target.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a timing according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing contents of a register according to the first embodiment of the present invention;

FIG. 4 is a block diagram showing a configuration according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing a timing according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram showing contents of a register according to a second embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration according to a conventional technique.

FIG. 8 is a timing chart showing a timing in the related art.

[Explanation of symbols]

1 command data, 2 self-refresh timer, 3 self-refresh counter, memory element composed of 4 to 7 memory cells, 12 self-refresh mode register, 13 start / stop address register, 14 self-refresh execution determination circuit.

Claims (11)

[Claims] 1. A memory element, and a control terminal for receiving an external signal for inputting a control signal to the memory element, wherein a refresh operation is performed on a part of the memory element by a combination of input signals from the control terminal. A semiconductor memory device that generates a command signal for performing a refresh operation on a part of the memory element to be refreshed among the memory elements by the command signal. 2. A memory device comprising: a memory element; and a register integrated with the memory element. A command signal for performing a refresh operation on a part of the memory element is stored in the register. Wherein the refresh operation is performed on a part of the memory elements to be refreshed among the memory elements. 3. A combination of a memory element, a control terminal for receiving an external signal for inputting a control signal to the memory element, and a register integrated with the memory element. A command signal for performing a refresh operation on a part of the memory element is generated and stored in the register, and a refresh operation is performed on a part of the memory element to be refreshed among the memory elements by the command signal of the register. A semiconductor memory device characterized in that it is performed. 4. A memory element, a control terminal for receiving an external signal for inputting a control signal to the memory element, and a register integrated with the memory element, wherein the register includes one of the memory elements. An address designating signal for performing a refresh operation on the unit is stored, and the address designating signal of the register causes the refresh operation to be performed only in a specific area to be refreshed among the memory elements. The semiconductor memory device according to claim 1. 5. A start address designation for performing a refresh operation on a part of the memory element in the start address register, comprising: a memory element; and a start address register and a stop address register integrated with the memory element. A signal is stored, and a stop address designation signal for performing a refresh operation on a part of the memory element is stored in the stop address register, and the start address register and the stop address register use the address designation signal of the stop address register to store the memory element. 5. The semiconductor memory device according to claim 1, wherein a refresh operation is performed only in a specific area to be refreshed. 6. A memory element, a control terminal receiving an external signal for inputting a control signal to the memory element, an address terminal receiving an external address signal, and a register integrated with the memory element. And generating an address designating signal for performing a refresh operation on a part of the memory element by a combination of the input signals by the control terminal and the address terminal, and storing the generated address designating signal in the register. 6. The semiconductor memory device according to claim 1, wherein a refresh operation is performed only on a specific area to be refreshed among the memory elements. 7. A memory element, a control terminal receiving an external signal for inputting a control signal to the memory element, an address terminal receiving an external address signal, and a register integrated with the memory element. A self-refresh timer integrated with the memory element, and generating an address designation signal for performing a refresh operation on a part of the memory element by a combination of input signals from the control terminal and the address terminal. The memory element is stored in a register, and the refresh operation is performed only in a specific area to be refreshed in the memory element by the address designation signal of the register and an active signal generated at a predetermined cycle by the self-refresh timer. Claims characterized by the following: The semiconductor memory device according to claim 1. 8. A memory element having a plurality of banks, and a control terminal for receiving an external signal for inputting a control signal to the memory element, wherein each bank of the memory element is provided by a combination of input signals from the control terminal. A command signal for bank selection for selecting whether or not to perform a refresh operation on the memory element, and the refresh operation is performed only on a specific bank to be refreshed among the memory elements by the command signal for bank selection. A semiconductor memory device characterized by doing so. 9. A memory element having a plurality of banks and a register integrated with the memory element.
A bank selection command signal for selecting whether to perform or not perform a refresh operation on each bank of the memory element is stored in the register, and the bank element command signal of the register causes the memory element to be refreshed among the memory elements. A semiconductor memory device wherein a refresh operation is performed only in a specific region as described above. 10. A memory element having a plurality of banks;
A control terminal for receiving an external signal for inputting a control signal to the memory element; and a register integrated with the memory element, wherein each bank of the memory element is refreshed by a combination of input signals from the control terminal. A bank selection command signal for selecting whether to perform or not perform an operation is generated and stored in the register, and only a specific bank to be refreshed among the memory elements by the bank selection command signal of the register is generated. Wherein the refresh operation is performed for the semiconductor memory device. 11. A memory element having a plurality of banks,
A control terminal for receiving an external signal for inputting a control signal to the memory element; a register integrated with the memory element; and a self-refresh timer integrated with the memory element. A bank selection command signal for selecting whether to perform or not perform a refresh operation on each bank of the memory element according to a combination of input signals is generated and stored in the register. 11. The refresh operation for only a specific bank to be refreshed among the memory elements by an active signal generated at a predetermined cycle by the self-refresh timer. Semiconductor memo described in any of the above Apparatus.