JP2002203389A - Semiconductor memory - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To reduce power consumption during refresh without changing pause characteristics. An internal row address signal (refresh address signal) is generated by a refresh address counter and input to a row decoder. In a normal refresh operation, the refresh address counter 17 sequentially increments the internal row address signal based on the trigger signal, so that the data of all the memory cells is refreshed. In the low current consumption refresh operation according to the present invention, since the value of at least one bit of a plurality of bits forming the internal row address signal is fixed, the refresh operation is performed on memory cells in a predetermined refresh area. Only done.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a dynamic random access memory (hereinafter referred to as DRAM) which can hold data with low power consumption.

[0002]

2. Description of the Related Art In a DRAM, a refresh operation is always required to retain data for a long time due to the nature of a memory cell. The refresh operation of a DRAM generally includes a refresh operation (auto-refresh operation) performed in response to a trigger signal from outside the chip and a refresh operation (self-refresh operation) of generating a trigger signal inside the chip.

In the case of a 64-Mbit synchronous DRAM, for example, a trigger signal (auto-refresh command) of 4096 times is input into the chip within 64 ms, and during this period, all of the 64-Mbit memory cells are input. A refresh operation must be performed.

In other words, there is a maximum time interval (refresh interval) of 64 ms between the time when a specific memory cell is refreshed and the time when the specific memory cell is refreshed again.

That is, a characteristic (pause time characteristic) that the data can be surely held for at least the 64 ms period is indispensable for the memory cell.

[0006] Normally, refresh is performed for each row, and data of memory cells in one row is refreshed by a sense amplifier in one refresh operation. Here, the memory capacity of the memory cell array is n bits (constant), the number of memory cells refreshed by one refresh operation is m bits (constant),
Assuming that the refresh interval is tR seconds, the number N of refresh operations per unit time can be represented by N = n / (m · tR) (1).

That is, assuming that the current consumed for refreshing is the same for all memory cells and that the current consumed for one refresh operation is constant (m = constant), the current consumed for refresh operation is assumed. In order to reduce the total current consumption, the refresh interval tR may be lengthened and the number N of refresh operations per unit time may be reduced.

For example, in the self-refresh operation, the refresh interval tR can be freely selected inside the chip. Also, under the use condition of a DRAM having a self-refresh function, it is important to reduce current consumption during self-refresh. Therefore, in such a DRAM, the refresh interval tR
Is controlled to be as long as possible within the range allowed by the characteristics of the memory cells (pause time characteristics).

More specifically, assuming that the pause time characteristic of the memory cell is 64 ms, the refresh interval tR at the time of self-refresh is set to 64 ms, which is the maximum value in a settable range. Similarly, assuming that the pause time characteristic of the memory cell is 128 ms, the refresh interval tR at the time of self-refresh is set to 128 ms.

The pause time characteristic of the memory cell is 1
In the case of 28 ms, compared to the case of 64 ms,
The value of the number N of refresh operations per unit time can be halved, and as a result, the total current consumed in the refresh operation can be halved.

[0011]

The number N of refresh operations per unit time can be expressed by the above equation (1). In order to reduce the total current consumption consumed in the refresh operation, the refresh interval tR is made as long as possible and the number N of the refresh operations per unit time is reduced as long as the pause time characteristic of the memory cell allows. I just need.

However, the refresh interval tR is limited by the pause time characteristic of the memory cell. That is, in order to increase the refresh interval tR, the pause time characteristic of the memory cell must be improved. However, it is very difficult in terms of the device structure to significantly improve the pause time characteristics of the memory cell and significantly reduce the current consumption during refresh.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. An object of the present invention is to reduce the number N of refresh operations per unit time without changing the pause time characteristics of memory cells, and It is to reduce current consumption at the time.

[0014]

In order to achieve the above object, a semiconductor memory according to the present invention comprises a memory cell array, a signal generation circuit for generating an internal address signal for selecting a row of the memory cell array during a refresh operation, and At the time of the refresh operation, based on a first control signal, a value of at least one bit among a plurality of bits constituting the internal address signal is fixed, and a refresh area having a memory capacity smaller than the memory capacity of the memory cell array is set. And a control circuit for selecting one of the rows.

Further, the semiconductor memory of the present invention has a memory cell array, a signal generation circuit for generating an internal address signal for selecting a row of the memory cell array during a refresh operation, and a first control signal based on a first control signal during the refresh operation. A control circuit for selecting a row in a refresh area having a smaller memory capacity than the memory capacity of the memory cell array; and a refresh timer for determining a timing of performing refresh, and selecting a row in the refresh area. In such a case, the refresh timer changes the timing for performing the refresh, and changes the timing for selecting a row in the refresh area.

Further, the semiconductor memory according to the present invention has a memory cell array, a signal generation circuit for generating an internal address signal for selecting a row of the memory cell array during a refresh operation, and a first control signal based on a first control signal during the refresh operation. A control circuit for fixing a value of at least one bit of a plurality of bits constituting the internal address signal and selecting a row in a refresh area having a memory capacity smaller than the memory capacity of the memory cell array; A refresh timer for determining a timing for performing a refresh, wherein when selecting a row in the refresh area, the refresh timer changes the timing for performing the refresh and changes the timing for selecting a row in the refresh area. .

The memory capacity of the refresh area is
2 of the memory capacity of the memory cell array ⁿIf it is 1 /
Fixed the value of the upper n bits of the internal address signal.
You.

The memory capacity of the refresh area is
2 of the memory capacity of the memory cell array ⁿIf it is 1 /
The interval for selecting a row in the refresh area is set to 2
ⁿDouble it.

The refresh area is determined in advance by data stored in a memory element in the chip.

The function of selecting only the rows in the refresh area is enabled by the second control signal.

At the time of the refresh operation, one of a mode for selecting all rows of the memory cell array and a mode for selecting only rows in the refresh area is selected based on the first control signal.

The first control signal is generated outside the chip or is generated inside the chip.

The semiconductor memory is used for portable electronic equipment.

A memory system according to the present invention includes the above-described semiconductor memory, and a CPU that supplies the semiconductor memory with the first control signal.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory according to the present invention will be described in detail with reference to the drawings.

[Overview] First, an overview of the present invention will be described.

The number N of refresh operations per unit time is expressed by the above equation (1). In the above equation (1), both the memory capacity n of the memory cell array and the number m of memory cells refreshed in one refresh operation are fixed values (the memory capacity of the DRAM and the memory capacity consumed in one refresh operation). Current consumption is constant.), And the only way to reduce the number N of refresh operations per unit time is to increase the refresh interval tR.

However, as described above, the refresh interval tR is limited by the pause time characteristic of the memory cell, and it is extremely difficult to actually increase the refresh interval tR.

Therefore, the present invention focuses on the memory capacity n of the memory cell array. That is, if the memory capacity n of the memory cell is reduced, the number N of refresh operations per unit time is reduced, and current consumption during refresh can be reduced without changing the pause time characteristic of the memory cell.

However, reducing the memory capacity n of the memory cell array is not preferable because it means that the amount of data stored in the memory cell array decreases.

Therefore, in the present invention, the memory cell array is divided into a plurality of regions without changing the memory capacity n of the memory cell array, and the region to be refreshed can be selected from the plurality of regions of the memory cell array. .
That is, in the present invention, by performing the refresh operation only on at least one of the plurality of regions of the memory cell array, the same effect as when the memory capacity n in the above equation (1) is reduced is obtained. Thus, the total current consumed for the refresh operation can be reduced.

For simplicity, the above equation (1) can be rewritten as follows. N = nrefresh / (m · tR) (2) where nrefresh is the memory capacity in the area to be refreshed (refresh area) in the total memory capacity n of the memory cell array.

The semiconductor memory according to the present invention needs to store a large amount of data, and in a specific case, needs to store a small amount of data with low power consumption (for example, a cellular phone or the like). It is most suitable for portable electronic devices.

That is, usually, a large amount of data is stored by a large memory capacity (for example, the total memory capacity n), and in a specific case, a small memory capacity (for example, at least one of a plurality of areas of the memory cell array). (A memory capacity in one area) to store a small amount of data.

When a large amount of data is stored, for example, since the entire memory capacity n of the memory cell array is used, the refresh area is the entire memory cell array (nrefresh = n). become. On the other hand, when storing a small amount of data, for example,
Since the memory capacity n1 (<n) in at least one of the plurality of regions of the memory cell array is used, the refresh region is a part (nrefres) of the memory cell array.
h = n1), and a reduction in current consumption is realized.

[Overall View] FIG. 1 shows a main part of a semiconductor memory according to the present invention.

The row decoder 12 selects a row (word line) of the memory cell array 11 based on an external row address signal or an internal row address signal (refresh address signal). The column decoder 13 selects a column of the memory cell array 11 based on an external column address signal.

The external row address signal is input to the row decoder 12 via the address buffer 14 and the row address driver 15. The external column address signal is input to the column decoder 13 via the address buffer 14 and the column address driver 16.

The internal row address signal (refresh address signal) is generated by a refresh address counter 17. The internal row address signal is input to the row decoder 12 via the row address driver 15. The row address driver 15 has a function of applying a potential to a row (word line) selected by an external row address signal or an internal row address signal.

The refresh timer 18 defines a refresh interval. The refresh controller 19 controls a series of refresh operations so that data of each memory cell is refreshed at a refresh interval.

The control signal CS includes a normal refresh operation (refresh operation for all memory cells in the memory cell array 11) and a refresh operation according to the present invention (only a part of memory cells in the memory cell array 11). (A low-current-consumption refresh operation). The control signal CS is supplied, for example, from outside the chip.

The control signal CS is input to the control circuit 10. The control circuit 10 performs a normal refresh operation (normal refresh operation) or a refresh operation according to the present invention (partial refresh operation) based on the control signal CS.
And outputs a signal for executing. For example, a signal for determining the refresh area is supplied from the control circuit 10 to the refresh address counter 17, and a signal for determining the refresh interval is supplied from the control circuit 10 to the refresh timer 18.

In a normal refresh operation, the refresh address counter 17 sequentially outputs an internal row address signal (refresh address signal) based on a trigger signal supplied from outside or inside the chip.
In order to increment, all the rows (word lines) of the memory cell array 11 are sequentially selected, and as a result, the data of all the memory cells are refreshed.

On the other hand, in the low current consumption refresh operation according to the present invention, the internal row address signal (refresh address signal) is set so that the refresh operation is performed only on the memory cells in the preset refresh area. ) Is a fixed value (“0” or “1”)
Is set to

For example, when 8192 rows are selected by 13-bit internal row address signals A0 to A12, the refresh address counter 17 sets the internal address based on a trigger signal supplied from outside or inside the chip. The row address signals A0 to A12 are sequentially incremented. At this time, if the value of the most significant bit A12 is fixed to "0", only the row having the address of which the most significant bit A12 is "0" is selected, and the row having the address of which the most significant bit A12 is "1" is selected. Is not always selected.

Assuming that the pause time characteristic of the memory cell is constant, the refresh interval tR is set the same between the normal refresh operation and the low current consumption refresh operation of the present invention.

As described above, in the low current consumption refresh operation of the present invention, the refresh area is limited by fixing a part of the internal address signal, and the number of rows (word lines) selected during the refresh operation is reduced. As a result, the memory capacity nrefresh of the memory cell array to be refreshed is reduced, and the number N of refresh operations per unit time is also reduced.

As a result, current consumption during the refresh operation can be reduced.

Here, in the low current consumption refresh operation of the present invention, since the number of selected rows (word lines) (corresponding to the memory capacity nrefresh) is reduced, it is assumed that the interval for incrementing the internal row address signal does not change. , The refresh interval tR compared to the normal refresh operation
Becomes shorter.

However, the refresh interval tR can be extended up to a value determined by the pause time characteristic of the memory cell.

Therefore, in the present invention, when the low current consumption refresh mode is set, the interval for incrementing the internal row address signal by the control signal, specifically, the interval for generating the trigger signal is lengthened.

For example, when the most significant bit A12 is fixed, the memory capacity of the refresh area of the memory cell array is half of the total memory capacity of the memory cell array (the number of selected rows is also half). , Ie, the interval at which the trigger signal is generated, is doubled.

Further, the value of the upper n bits of the internal row address signal is fixed, and when the memory capacity of the refresh area becomes 1/2 ⁿ of the total memory capacity of the memory cell array, the internal row address signal is incremented. The interval is 2 ⁿ times.

In the above example, at least one of the internal address signals (refresh address signals) is fixed and the interval for generating the trigger signal is lengthened, so that each row in the preset refresh area is set. Are selected at the maximum refresh interval tR.

That is, in the normal refresh mode and the low current consumption refresh mode according to the present invention, the interval (increment) of the internal row address signal according to the memory capacity of the refresh area is set so that the refresh interval tR becomes the same. (Trigger signal generation interval) is also changed.

Note that only the memory capacity of the refresh area may be changed without changing the interval at which the trigger signal is generated. In this case, the refresh interval tR changes according to the memory capacity of the refresh area. However,
When refreshing the entire memory cell array of the DRAM, the refresh interval tR becomes the maximum, so that the refresh interval tR is always less than or equal to the value determined by the pause time characteristics of the memory cells.

As described above, according to the semiconductor memory of the present invention, the number N of refresh operations per unit time is reduced without changing the pause time characteristics of the memory cells, and the current consumption during refresh is reduced. can do.

[First Embodiment] A first example of a normal refresh operation and a low current consumption refresh operation according to the present invention will be described with reference to the logical address space diagrams shown in FIGS.

In this example, it is assumed that the memory capacity of the DRAM is 64 megabits, and that there are 8 kilo rows and 8 kilo columns. Eight kilo rows correspond to a 13-bit internal address signal (refresh address signal) A
It can be uniquely specified by 0 to A12.

In a normal refresh operation, as shown in FIG. 2, 13-bit internal address signals A0 to A12 are
It can be performed by sequentially incrementing. The method of incrementing the internal address signals A0 to A12, that is, the order in which rows (word lines) are selected, the number of rows (word lines) selected at a time, and the like can be freely set. Refresh interval t
All rows must be selected within a period corresponding to R.

In the low current consumption refresh operation according to the present invention, the 13-bit internal address signals A0 to A12 are sequentially incremented as shown in FIG.
At this time, the value of the most significant bit A12 is fixed to “0”. In this case, the refresh operation is performed with the most significant bit A1
Only memory cells having an address where 2 is "0" are targeted. Specifically, a refresh operation is performed on a memory cell in a refresh area having half the capacity (32 Mbit) of the memory capacity of the DRAM.

In the low current consumption refresh operation according to the present invention, the internal address signals A0 to A12
The increment method (however, A12 is fixed), that is, the order in which rows (word lines) are selected, the number of rows (word lines) selected at a time, and the like can be freely set. All rows in the refresh area must be selected at least within a period corresponding to the refresh interval tR.

In the present embodiment, two modes can be selected by the control signal. One is a normal refresh mode. The other is a low current consumption refresh mode according to the present invention. To switch between the two modes, the control signal must be at least 1
Bits are sufficient.

The normal refresh mode is selected when the entire memory capacity of the memory cell array is used. The low current consumption refresh mode according to the present invention has a small data capacity and is half the memory capacity of the memory cell array. It is selected when it is sufficient to use only.

In this embodiment, two modes can be selected by a control signal. In this case, the control signal is input from outside the chip. However, the control signal may be automatically generated inside the chip according to the data capacity. In the low-current-consumption refresh mode of the present invention, a case where A12 is fixed to “0” or a case where A12 is fixed to “1” may be further selectable. Further, the control signal may be fixed so that the control signal always selects the low current consumption refresh mode of the present invention.

As described above, according to the present embodiment, in the low-current-consumption refresh mode, the number N of refresh operations per unit time can be reduced without changing the pause time characteristic of the memory cell as compared with the normal refresh mode. Since the current consumption can be halved, the current consumption at the time of refresh can be halved.

[Second Embodiment] A second example of a normal refresh operation and a low current consumption refresh operation according to the present invention will be described with reference to the logical address space diagrams shown in FIGS.

Also in this example, it is assumed that the memory capacity of the DRAM is 64 megabits, that there are 8 kilo rows and 8 kilo columns. Eight kilo rows can be uniquely specified by 13-bit internal address signals (refresh address signals) A0 to A12.

The normal refresh operation is performed in the same manner as in the first embodiment (FIG. 2).

In the low current consumption refresh operation according to the present invention, as shown in FIG. 4, the 13-bit internal address signals A0 to A12 are sequentially incremented.
At this time, the value of the most significant two bits A12 and A11 is
Fixed to “0”. In this case, the refresh operation is
Only the memory cells in which the most significant two bits A12 and A11 have the address of “0” are targeted. In particular,
A refresh operation is performed on a memory cell in a refresh area having a capacity (1/4 Mbit) of the memory capacity of the DRAM.

Incidentally, also in the present embodiment, two modes can be selected by the control signal. One is a normal refresh mode. The other is a low current consumption refresh mode according to the present invention. In order to switch between these two modes, it is sufficient for the control signal to have at least one bit.

The normal refresh mode is selected when all of the memory capacity of the memory cell array is used, and the low current consumption refresh mode according to the present invention has a small data capacity and one of the memory capacity of the memory cell array. This is selected when it is sufficient to use only / 4.

In this embodiment, the most significant two bits A of the internal row address signal (refresh address signal) are used.
Although A11 and A11 are fixed, the bit for fixing the value may be at least one bit of the internal row address signal according to the memory capacity of the preset refresh area. At least one bit is set to “0” according to the position of the refresh area set in advance.
Alternatively, it may be fixed to “1”.

As described above, according to the present embodiment, in the low current consumption refresh mode, the number N of refresh operations per unit time can be reduced without changing the pause time characteristic of the memory cell as compared with the normal refresh mode. 1 /
4, the current consumption at the time of refresh can also be reduced to 1/4.

[Third Embodiment] In the first and second embodiments described above, the refresh mode is divided into the normal refresh mode and the low current consumption refresh mode according to the present invention.
It is composed of one. Therefore, the control signal must have at least one
Bits are sufficient.

However, a plurality of refresh areas having a memory capacity smaller than the memory capacity of the DRAM are set,
In the low-current-consumption refresh mode, one of a plurality of refresh areas is selected according to the data capacity.
It is also possible to be able to select one.

In this case, the control signal is composed of a plurality of bits. For example, if the control signal is composed of N bits, it is possible to select ^2N or less modes (one of them is a normal refresh mode, and the other is a low current consumption refresh mode).

Further, the refresh area can be made very small as compared with the memory capacity of the DRAM. In this case, the number of bits whose value is fixed among the plurality of bits constituting the internal row address signal may be increased.

The control signal may be provided with a dedicated external input terminal and supplied directly from the external input terminal, or generated from a combination of existing external input signals such as a mode register set. You may do so.

[Circuit Example] Next, a circuit example of a semiconductor memory according to the present invention will be described.

FIGS. 5 and 6 show circuit examples of the control circuit of FIG. FIG. 7 is a waveform diagram showing the operation of the circuits of FIGS.

The control signal CS is the clocked inverter C
After passing through I1, it is input to the first input terminal of the NAND circuit NA1. A control signal (Partial Refresh Enable Option signal) P is supplied to a second input terminal of the NAND circuit NA1.
REO is input.

The control signal PREO controls the normal refresh operation (normal refresh operation) and the refresh operation (partial refresh operation) according to the present invention.
This is to determine whether or not the chip has the function of switching by S.

For example, when the control signal PREO is at "L" level, only a normal refresh operation is performed regardless of the control signal CS, and the refresh operation according to the present invention is not performed. When the control signal PREO is at the “H” level, a normal refresh operation or a refresh operation according to the present invention is executed based on the control signal CS.

The level (“H” or “L”) of the control signal PREO is determined, for example, by the state of the fuse. That is, the level of the control signal PREO is determined by whether or not the fuse is cut at the time of chip manufacture. Therefore, the level of the control signal PREO is fixed to “H” or “L” in a product stage.

[0086] However, the level of the control signal PREO may be changed by an electric signal.

A clocked inverter CI2 is connected between the first input terminal and the output terminal of the NAND circuit NA1.
When the output signal of the NAND circuit NA1 passes through the clocked inverter CI3 and the inverter I1, the control signal b
PRE.

When latch signal LACH attains "H", clocked inverters CI1, CI2 and CI3 are activated. Therefore, the control signal CS is supplied to the NAND circuit NA1.
Is latched by a latch unit including a clocked inverter CI2 and a control signal b based on the control signal CS.
A PRE is generated.

The latch signals LACT and bLACT are generated based on the control signals ACUP and PREO. The control signal (Address Count Up Pulse signal) ACUP is
This is a pulse signal for counting up (or counting down) the count value of the refresh address counter 17 (see FIG. 1) that generates the refresh address signal.

The control signal (pulse signal) ACUP is output each time the refresh operation for the memory cell in one row address is completed.

When the control signal PREO is "H", when the control signal ACUP becomes "H", the latch signal LACH also becomes "H". When the control signal ACUP becomes "L", the latch signal LACH also becomes "L". "become. When the control signal PREO is "L", the latch signal LACH always remains "L" regardless of the level of the control signal ACUP.

Control signal (Partial Refresh Enable sign
al) bPRE is not completely synchronized with the control signal CS. As shown in FIG. 7, the level of control signal bPRE is determined by the level of control signal CS when control signal ACUP is at "H".

As described above, the control signal (pulse signal) AC
The level of the control signal bPRE (normal refresh mode) depends on the level of the control signal CS at the time when the UP is output.
The reason for determining the (partial refresh mode) is to prevent a malfunction in which the control signal bPRE is switched during the refresh operation.

The control signal bPRE is supplied to the NOR circuits NR1,
The signals are input to first input terminals of NR2. After passing through the inverter I3, the control signal (Quarter Refresh) QR is input to the second input terminal of the NOR circuit NR1 and is also input to the AND circuit AD. Control signal (Hal
f Refresh) After passing through the inverter I4, the HR
Input to the AND circuit AD. The output signal of the AND circuit AD is input to a second input terminal of the NOR circuit NR2.

The output signal of the NOR circuit NR1 becomes the control signal bRACC11, and after passing through the inverter I5,
This becomes the control signal RACC11. The output signal of the NOR circuit NR2 becomes the control signal bRACC12,
6, the control signal RACC12 is obtained.

In this circuit example, the most significant bit A12 of the 13-bit row address signal A12-A0 is determined based on the levels ("H" or "L") of the control signals QR and HR.
Is fixed, the level of the upper two bits A12 and A11 is fixed, or all the bits A12-A0
Determines whether to fix the level.

For example, assuming that control signal PREO is at "H" and control signal CS is at "L", control signal bPR
E becomes “L” (partial refresh mode). At this time, if the control signal HR is “H” and the control signal QR is “L”, the RACC 12 is “L” and the RACC 11 is
"H", bRACC12 becomes "H", bRACC
11 becomes "L". The result is the most significant bit A12 of the 13-bit row address signal A12-A0.
Level is fixed (half refresh
mode). This will be described later.

When the control signal bPRE is “L” and the control signal HR is “H” and the control signal QR is “H”,
RACC12 and RACC11 both become "L",
Both bRACC12 and bRACC11 become “L”. The result is a 13-bit row address signal A12.
−A0 means that the levels of the upper two bits A12 and A11 are fixed (quarter refresh mode
). This will be described later.

Even if the control signal bPRE is "L", if both the control signals HR and QR are "L", the RAC
C12 and RACC11 both become “H”, and bRA
CC12 and bRACC11 both become "L". In this case, the levels of all the bits A12-A0 of the 13-bit row address signal A12-A0 are not fixed.

Therefore, normally, the levels of the control signals HR and QR are as follows: control signal HR = “H”, control signal QR =
“L”, control signal HR = “H”, control signal QR =
It is set to one of “H”.

The levels ("H" or "L") of the control signals HR and QR are determined, for example, by the state of the fuse. That is, the levels of the control signals HR and QR are determined depending on whether or not the fuse is cut during chip manufacture.
Therefore, the levels of the control signals HR and QR are fixed to “H” or “L” in a product stage.

However, the levels of the control signals HR and QR may be changed by an electric signal.

When the control signal PREO is "L" or the control signal CS is "H", the control signal bPRE
Becomes “H”. At this time, regardless of the levels of the control signals HR and QR, RACC12 and RACC11 always become "H", and bRACC12 and bRACC11
Is always “L”. That is, the levels of all the bits A12-A0 of the 13-bit row address signal A12-A0 are not fixed.

FIG. 8 shows a circuit example of the refresh address counter of FIG.

Since this circuit example corresponds to the first to third embodiments, the refresh address counter 1
7 generated by the refresh address signal A12-
A0 has 13 bits. The number of bits of the refresh address signal A12-A0 and the number of units constituting the refresh address counter 17 correspond to each other.
7, the number of units is 13 (N = 1, 2, 3,
... 13).

In this circuit example, one memory cell array region is composed of four refresh regions, and a mode (Quarter Refresh mode) for refreshing only memory cells in one refresh region and a memory cell in all refresh regions are used. Refresh mode (Nor
mal Refresh mode) by the control signal CS, a mode in which one memory cell array area is composed of two refresh areas and only memory cells in one refresh area are refreshed (Half Refres
h mode) and a mode (Normal Refresh mode) for refreshing the memory cells in all the refresh areas.

Therefore, the refresh address signal A1
The control signals RACC12, bRACC12, R generated by the circuits of FIGS. 5 and 6 are applied to units (N = 1, 2) for generating the upper two bits A12, A11 of 2-A0
ACC11 and bRACC11 are input so that the levels of the refresh address signals A12 and A11 can be fixed.

FIG. 9 shows a unit N = 1 of the counter of FIG.
3 shows an example of the circuit. A control signal (Address Count Up Pulse signal) ACUP is input to the unit N = 1, and a refresh address signal A12 is output from the unit N = 1. RACC12 is "H", bRA
When CC12 = “L”, the refresh address signal A12 is a binary count output signal using the control signal ACUP as a basic clock. On the other hand, when RACC12 is "L" and bRACC12 = "H", the refresh address signal A12 outputs the control signal ACUP as it is.

The control signal ACUP is a pulse signal generated each time the refresh operation is completed, and always returns to the “L” level by the time the next refresh operation is started. Therefore, the refresh address signal A1
2 is ACUP, that is, a signal of always "L" level, which is taken into the address driver. As a result, in the row decoder circuit, the state is such that the refresh address signal A12 is fixed at "L".

FIG. 10 shows a unit N =
2 shows an example of a circuit. The output signal A12 of the unit N = 1 is input to the unit N = 2. That is, the unit N = 2 includes the control signals RACC12, bRACC12
, One of a binary count output signal using the control signal ACUP as a basic clock and the control signal ACUP is input.

A refresh address signal A11 is output from the unit N = 2. RACC11 is "H",
When bRACC11 = “L”, the refresh address signal A11 is a binary count output signal using the refresh address signal A12 as a basic clock. On the other hand, when RACC11 is "L" and bRACC11 = "H", the refresh address signal A11 outputs the control signal ACUP as it is.

The control signal ACUP is a pulse signal generated every time the refresh operation is completed, and always returns to the “L” level by the time the next refresh operation is started. Therefore, the refresh address signal A1
1 is an ACUP, that is, a signal of always "L" level, which is taken into the address driver. As a result, in the row decoder circuit, the state is such that the refresh address signal A11 is fixed at "L".

FIG. 11 shows a unit N =
13 shows circuit examples 3, 4,... The output signal Ax + 1 of the immediately preceding unit is input to each unit N = 3, 4,. Each unit N = 3,4,
.. 13 output a refresh address signal Ax.

In units N = 3, 4,... 13, since RACCx is fixed at “H” and bRACCx is fixed at “L”, refresh address signal Ax
Is always a binary-counted signal of the input signal Ax + 1.

8 to 11, the circuit example of the refresh address counter has been described. However, the units in the refresh address counter may have the same configuration or different configurations. Is also good.

For example, the unit N = 3, 4,.
Regarding 13, the logic circuit of the output unit may be simplified to be a unit as shown in FIG.

In this circuit example, at least the first
In order to realize the third to third embodiments, the upper two bits A1 of the 13-bit row address signal A12-A0 are
2, A11 can be fixed, but by applying this circuit example, it is also possible to easily fix the upper three bits or more of the row address signal.

[Operation] Next, the operation of the semiconductor memory according to the above-described first and second embodiments when the circuit examples of FIGS. 5 to 12 are used will be described.

In the case of the first embodiment i. Assumption First, the control signal PREO is set to “H” so that the chip has the function of the present invention. In the first embodiment, the 64 Mbit memory cell array area is divided into two 3
The control signal HR is set to "H" and the QR is set to "L" because the memory cell array is divided into 2 megabit memory cell array regions. Furthermore, RACC10-RACC0 is fixed at "H", and bRACC10-bRACC0 is fixed at "L".

Under this precondition, the normal refresh operation (nor) is selectively performed based on the level of control signal CS.
A mal refresh operation or a half refresh operation according to the present invention is performed.

Ii. NORMAL REFRESH OPERATION In the normal refresh operation, that is, when refreshing the memory cells in the 64-Mbit memory cell array area, the control signal CS becomes "H". When the control signal ACUP becomes “H” while the control signal CS is “H”, the control signal bPRE becomes “H”. When the control signal bPRE becomes “H”, the RACC 12
“H”, bRACC12 is “L”, RACC11 is
“H” and bRACC11 become “L”.

[0122]

[Table 1]

That is, for all the units (N = 1, 2,... 13) in the refresh address counter, RACCx (x is 12, 11,... 0) is
“H” and bRACCx become “L”.

Therefore, the pulse signal ACUP is input to the first unit (N = 1), and the second and subsequent units (N
= 2, 3, ... 13), the output signal of the preceding unit is input. As a result, in synchronization with the pulse signal ACUP, the 13-bit refresh row address signal A12-
A0 is sequentially incremented.

Iii. HALF REFRESH OPERATION In the refresh operation according to the present invention, that is, when refreshing the memory cells in the 32 Mbit memory cell array area which is half of the 64 Mbit memory cell array area, the control signal CS is set to “L”. Becomes When the control signal ACUP becomes “H” while the control signal CS is “L”, the control signal bPRE becomes “L”. Control signal bPR
When E becomes "L", as shown in Table 2, RACC12
Is "L", bRACC12 is "H", RACC11
Becomes "H" and bRACC11 becomes "L".

[0126]

[Table 2]

That is, for the first unit (N = 1) in the refresh address counter, RACC12
Becomes "L" and bRACC12 becomes "H". Also,
RACCx (x is 11, 10,... 0) for the second and subsequent units (N = 2, 3,... 13)
Becomes “H” and bRACCx becomes “L”.

Therefore, the output signal (row address signal) A12 of the first unit (N = 1) is the control signal ACU.
P is output as it is. The control signal ACUP is a pulse signal generated every time the refresh operation ends,
By the time the next refresh operation is started, the level always returns to the “L” level. Therefore, the refresh address signal A12 is ACUP, that is, a signal of always "L" level, which is taken into the address driver. As a result, in the row decoder circuit, the state is such that the refresh address signal A12 is fixed at "L".

The output signal A12 of the first stage unit (N = 1) input to the second stage unit (N = 2)
Is substantially equivalent to the control signal ACUP. As a result, in synchronization with the pulse signal ACUP, the remaining 12 bits of the refresh address signal excluding the most significant bit A12 are removed.
Bits A11-A0 are sequentially incremented.

In the Case of the Second Embodiment i. Assumption First, the control signal PREO is set to “H” in order to provide the chip with the function of the present invention. In the second embodiment, the 64-megabit memory cell array area is divided into four 1-bit memory cell arrays.
The control signal HR is set to “H” and the QR is set to “H” because the memory cell array is divided into 6-megabit memory cell array areas. Furthermore, RACC10-RACC0 is fixed at "H", and bRACC10-bRACC0 is fixed at "L".

Under this precondition, the normal refresh operation (nor) is selectively performed based on the level of control signal CS.
mal refresh operation) or a refresh operation (quarter refresh operation) according to the present invention is executed.

Ii. NORMAL REFRESH OPERATION In the normal refresh operation, that is, when refreshing the memory cells in the 64-Mbit memory cell array area, the control signal CS becomes "H". When the control signal ACUP becomes “H” while the control signal CS is “H”, the control signal bPRE becomes “H”. When the control signal bPRE becomes “H”, the RACC12
Is "H", bRACC12 is "L", RACC11
Becomes "H" and bRACC11 becomes "L".

That is, for all units (N = 1, 2,... 13) in the refresh address counter, RACCx (x is 12, 11,... 0) is
“H” and bRACCx become “L”.

Therefore, the pulse signal ACUP is input to the first unit (N = 1), and the second and subsequent units (N
= 2, 3, ... 13), the output signal of the preceding unit is input. As a result, in synchronization with the pulse signal ACUP, the 13-bit refresh row address signal A12-
A0 is sequentially incremented.

Iii. QUARTER REFRESH OPERATION In the refresh operation according to the present invention, that is, when refreshing a memory cell in a 16-megabit memory cell array area, which is a quarter of the 64-megabit memory cell array area, the control signal CS is output. It becomes “L”. When the control signal ACUP becomes “H” while the control signal CS is “L”, the control signal bPRE becomes “L”. Control signal b
When PRE goes to “L”, as shown in Table 3, RACC
12 is “L”, bRACC12 is “H”, RACC
11 is "L", bRACC11 is "H".

[0136]

[Table 3]

That is, for the first unit (N = 1) in the refresh address counter, RACC12
Is “L”, bRACC12 is “H”, and for the second stage unit (N = 2), RACC11 is
“L” and bRACC11 become “H”. For the third and subsequent units (N = 3, 4,..., 13), RACCx (x is 10, 9,... 0) is
“H” and bRACCx become “L”.

Therefore, the first-stage and second-stage units (N
= 1, 2) output signals (row address signals) A12, A
11 outputs the control signal ACUP as it is. The control signal ACUP is a pulse signal generated every time the refresh operation is completed, and always returns to the “L” level before the next refresh operation is started. Therefore, the refresh address signals A12, A11
UP, that is, a signal of always “L” level,
Captured by the address driver. As a result, in the row decoder circuit, the refresh address signals A12, A
11 is fixed at “L”.

The output signal A11 of the second-stage unit (N = 2) input to the third-stage unit (N = 3)
Is substantially equivalent to the control signal ACUP. As a result, the remaining 11 bits A10-A0 of the refresh address signal excluding the upper two bits A12 and A11 are sequentially incremented in synchronization with the pulse signal ACUP.

[System Example] FIG. 13 shows an example of a system using a memory chip having a refresh function according to the present invention. The memory chip 20 includes the circuit shown in FIG. In this example, the control signal C
S is generated, and the control signal CS is supplied to the memory chip 20.

[Others] The present invention normally requires a large memory capacity for large-capacity data, and stores small-capacity data with low power consumption at a specific time.
Applies to systems where small memory capacity is sufficient. In addition, the present invention is very effective especially for a portable electronic device such as a mobile phone in which reduction of power consumption is an important issue.

[0142]

As described above, the semiconductor memory according to the present invention has a mode in which the refresh operation is performed only on the refresh region having a smaller memory capacity than the memory capacity of the memory cell array. Without changing the pause time characteristics of the memory cells, the number of refresh operations per unit time can be reduced, and current consumption during refresh can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of a semiconductor memory of the present invention.

FIG. 2 is a diagram showing a refresh area in a normal refresh mode.

FIG. 3 is a diagram showing an example of a refresh area in a refresh mode according to the present invention.

FIG. 4 is a diagram showing another example of a refresh area in the refresh mode of the present invention.

FIG. 5 is a diagram showing a circuit example of a control circuit according to the present invention.

FIG. 6 is a diagram showing a circuit example of a control circuit according to the present invention.

FIG. 7 is a waveform chart showing the operation of the control circuit shown in FIGS. 5 and 6;

FIG. 8 is a diagram showing a circuit example of a refresh address counter according to the present invention.

FIG. 9 is a diagram showing a circuit example of a first-stage unit of the counter of FIG. 8;

FIG. 10 is a diagram illustrating a circuit example of a second-stage unit of the counter in FIG. 8;

FIG. 11 is a diagram showing a circuit example of a unit after the third stage of the counter of FIG. 8;

FIG. 12 is a diagram illustrating a circuit example of a unit at the third and subsequent stages of the counter in FIG. 8;

FIG. 13 is a diagram showing an example of a system using a memory chip having a refresh function of the present invention.

[Explanation of symbols]

11: memory cell array, 12: row decoder, 13: column decoder, 14: address buffer, 15: row address driver, 16: column address driver, 17: refresh address counter, 18: refresh timer, 19: refresh controller. 20: Memory chip, 21: CPU, I1, I2,... I6: Inverter, CI1, CI2, CI3: Clocked inverter, NA1, NA2: NAND circuit, AD: AND circuit, NR1, NR2: NOR circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5M024 AA15 BB22 BB23 BB39 CC50 DD62 DD92 EE10 EE29 KK30 PP01 PP02 PP07

Claims (11)

[Claims] 1. A memory cell array, a signal generation circuit for generating an internal address signal for selecting a row of the memory cell array during a refresh operation, and the internal address signal based on a first control signal during the refresh operation. A control circuit for fixing a value of at least one bit of a plurality of bits to be configured and selecting a row in a refresh region having a memory capacity smaller than the memory capacity of the memory cell array. Semiconductor memory. 2. A memory cell array, a signal generation circuit for generating an internal address signal for selecting a row of the memory cell array during a refresh operation, and a memory of the memory cell array based on a first control signal during the refresh operation. A control circuit for selecting a row in a refresh area having a memory capacity smaller than the capacity, and a refresh timer for determining a timing for performing refresh. A semiconductor memory, wherein a timer changes timing for performing the refresh, and changes timing for selecting a row in the refresh area. 3. A memory cell array, a signal generation circuit for generating an internal address signal for selecting a row of the memory cell array during a refresh operation, and the internal address signal based on a first control signal during the refresh operation. A control circuit for fixing a value of at least one bit of a plurality of bits to be configured and selecting a row in a refresh area having a memory capacity smaller than the memory capacity of the memory cell array, and determining a timing of performing refresh. A semiconductor device comprising a refresh timer, wherein, when selecting a row in the refresh area, the refresh timer changes the timing of performing the refresh and changes the timing of selecting a row in the refresh area. memory. 4. The method according to claim 1, wherein a value of upper n bits of said internal address signal is fixed when a memory capacity of said refresh area is 1 / ²ⁿ of a memory capacity of said memory cell array. Or the semiconductor memory according to 2 or 3. 5. The method according to claim 1, wherein when the memory capacity of the refresh area is 1 / ²ⁿ of the memory capacity of the memory cell array, an interval for selecting a row in the refresh area is made 2 ⁿ times. The semiconductor memory according to claim 1, 2, or 3. 6. The semiconductor memory according to claim 1, wherein the refresh area is determined in advance by data stored in a memory element in a chip. 7. The semiconductor memory according to claim 1, wherein the function of selecting only a row in the refresh area is enabled by a second control signal. 8. During the refresh operation, one of a mode for selecting all rows of the memory cell array and a mode for selecting only rows in the refresh area is selected based on the first control signal. The semiconductor memory according to claim 1, 2 or 3, wherein: 9. The semiconductor memory according to claim 1, wherein the first control signal is generated outside a chip. 10. The semiconductor memory according to claim 1, wherein the first control signal is generated inside a chip. 11. The semiconductor memory according to claim 1, wherein the semiconductor memory is used for a portable electronic device.