HK1119292B - Method of forming a semiconductor device having trench charge compensation regions - Google Patents

Description

Method of forming semiconductor device having trench charge compensation region

Technical Field

The present invention relates generally to semiconductor devices, and more particularly to power switching devices and methods of making the same.

Background

A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a common type of power switching device. The MOSFET device includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer.

When the MOSFET device is in an on-state, a voltage is applied to the gate structure to form a conducting channel region between the source and drain regions, which allows current to flow through the device. In the off state, any voltage applied to the gate structure is low enough that a conduction channel cannot form and thus no current flow occurs. During the off-state, the device must support a high voltage between the source and drain regions.

Today's market for high voltage power switches is driven mainly by two factors: breakdown voltage (BVdss) and on-resistance (Rdson). Minimum breakdown voltage is required for a particular application and in practice designers are often able to meet BVdss specifications. However, this is often at the cost of Rdson. This trade-off in performance is a major design challenge for manufacturers and users of high voltage power switching devices.

Recently, super junction (super junction) devices have gained popularity in improving the trade-off problem between BVdss and Rdson. In conventional n-channel superjunction devices, a plurality of heavily doped diffused n-type and p-type regions replace a lightly doped n-type epitaxial region. In the on state, current flows through the heavily doped n-type region, which reduces Rdson. In the off or blocking state, the heavily doped n-type and p-type regions deplete or compensate each other to provide a high BVdss. Although superjunction devices appear promising, there are still many challenges in their manufacture.

Accordingly, there is a need for a high voltage power switching device structure and method of fabrication that provides low Rdson and high BVdss.

Disclosure of Invention

According to an aspect of the present invention, there is provided a method of forming a semiconductor device, comprising the steps of: providing a region of semiconductor material having a first major surface, a dielectric region overlying the first major surface, and a trench formed within the region of semiconductor material; exposing the surface of the cell to a hydrogenolysis adsorption process at a temperature in the range from 1000 degrees Celsius to less than 1100 degrees Celsius; and forming a plurality of single crystal semiconductor layers overlying the surface of the trench after the step of exposing the surface of the trench to a hydrogenolysis adsorption process.

According to another aspect of the present invention, there is provided a method of forming a semiconductor device, comprising the steps of: providing a region of semiconductor material having a first major surface, a dielectric region overlying the first major surface, and a trench formed within the region of semiconductor material; at a temperature in the range from 1000 ℃ to less than 1100 ℃, at less than 540kgf/m²Exposing the surface of the cell to a hydrogenolysis adsorption process at a reduced pressure; and forming a plurality of single crystal semiconductor layers overlying the surface of the bath after the step of exposing the surface of the bath to a hydrogenolysis adsorption process wherein at least two layers comprise opposite conductivity types and wherein an intrinsic layer separates the at least two layers.

According to another aspect of the present invention, there is provided a method of forming a semiconductor device having a trench charge compensation structure, comprising the steps of: providing a body of semiconductor material having a first major surface; forming a trench within the body of semiconductor material, the trench extending from the first major surface, wherein the trench has an aspect ratio of from 10: 1 to 30: 1; in the presence of hydrogen, at less than 540kgf/m²Exposing the surface of the groove to a temperature range from 1000 degrees celsius to less than 1100 degrees celsius at a reduced pressure; forming a first single crystal semiconductor layer overlying a surface of the trench after the step of exposing the surface of the trench to a temperature range from 1000 degrees Celsius to less than 1100 degrees Celsius, wherein the first single crystal semiconductor layer has a first conductivity type; forming a first buffer layer overlying the first single crystal semiconductor layer, wherein the first buffer layer has a doping concentration greater than that of the first single crystal semiconductor layerThe doping concentration of the crystalline semiconductor layer is at least one order of magnitude smaller; exposing the body of semiconductor material to an elevated temperature to redistribute dopants from the first semiconductor layer into the body of semiconductor material; forming a second buffer layer overlying the first buffer layer; and forming a second single crystal semiconductor layer overlying the second buffer layer, wherein the second single crystal semiconductor layer includes a second conductivity type opposite the first conductivity type.

Drawings

FIG. 1 illustrates an enlarged partial cross-sectional view of a semiconductor device in accordance with the present invention;

FIGS. 2-8 illustrate enlarged partial cross-sectional views of the semiconductor device of FIG. 1 at various stages of fabrication; and

fig. 9 illustrates a highly enlarged partial cross-sectional view of a portion of a semiconductor device, in accordance with another embodiment of the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures refer to the same elements. In addition, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor or an emitter or collector of a bipolar transistor or a cathode or anode of a diode, and a control electrode means an element of the device through which control current passes, such as a gate of an MOS transistor or a base of a bipolar transistor.

Although the devices are explained herein as certain N-channel devices and P-channel devices, one of ordinary skill in the art will appreciate that complementary devices are also possible in accordance with the present invention. For clarity of the drawing, the doped regions of the device structure are illustrated as having generally straight edges and precisely angled corners. However, it will be appreciated by those skilled in the art that due to the diffusion and activation of the dopant, the edges of the doped regions are not generally straight and the corners are not precisely angled.

Furthermore, the devices of the present invention may comprise either a cellular design (in which the body region is a plurality of cellular regions) or a monolithic design (in which the body region comprises a single region formed by an elongated pattern, typically a serpentine pattern). However, for ease of understanding, the device of the present invention will be described in a cellular design throughout the specification. It should be understood that the present invention is intended to encompass both unitary and monomeric designs or single-base designs.

Detailed Description

Fig. 1 shows a partial cross-sectional view of an Insulated Gate Field Effect Transistor (IGFET), MOSFET, superjunction device, or switching device or cell 10, according to an embodiment of the present invention. By way of example, device 10 is one of many such devices that are integrated with logic and/or other components in a semiconductor chip as part of a power integrated circuit. Alternatively, device 10 is one of many such devices that are integrated together to form a split transistor device.

The device 10 includes a region or body 11 of semiconductor material, which comprises, for example, an n-type silicon substrate having a resistance in the range of about 0.001 to 0.005 ohm-centimeters (ohm-cm), and which may be doped with arsenic or other n-type dopants. In the embodiment shown, substrate 12 provides a drain region of device 10, which is coupled to conductive layer 13. Semiconductor layer 14 is formed within substrate 12 or on substrate 12 and semiconductor layer 14 is n-type or p-type and is doped lightly enough so as not to affect the charge balance of the trench compensation regions described below in accordance with the present invention. In one embodiment, layer 14 is formed using a conventional epitaxial growth process. In an embodiment suitable for a 600 volt (volt) device, layer 14 is either n-type doped or p-type doped, with a doping concentration of about 1.0 x 10¹³Atom/cm³(atoms/cm³) To about 1.0X 10¹⁴Atom/cm³And a thickness on the order of about 40 microns to about 60 microns. The thickness of layer 14 is increased or decreased depending on the desired BVdss rating of device 10. In an alternative embodiment, semiconductor layer 14 includes a graded doping profile, wherein semiconductor layer 14 has a higher doping concentration proximate to substrate 12 and gradually or abruptly transitions to a lower concentration to balance the thickness of semiconductor layer 14. Other materials may be used for the body of semiconductor material 11 or portions thereof, including silicon-germanium, silicon-germanium-carbon, carbon-doped silicon, III-V materials, or the like.

The device 10 further includes a gap-filled or partially filled trench, a trench containing a layer of semiconductor material, an epitaxially filled region or trench, a charge compensated trench region, a deep trench charge compensation region, a charge compensated trench structure, or a charge compensation region 22. The charge compensation trenches 22 comprise or contain multiple layers or layers of semiconductor material, including layers of opposite conductivity type, separated by one or more intrinsic or buffer semiconductor layers. The intrinsic layer serves, among other things, to prevent or reduce intermixing of the layers of opposite conductivity types (i.e., the two charge layers) which is believed to adversely affect the conduction efficiency of the device 10 in the on-state. As used herein, charge compensation generally means that all charges of layers of opposite conductivity types are substantially balanced or equal.

In one embodiment, filled trench 22 comprises multiple layers of semiconductor material or stacked layers of semiconductor material formed using a single crystal or single crystal (i.e., not polycrystalline) epitaxial growth process. For example, the compensated trench structure 22 includes a p-type layer 23, the p-type layer 23 being formed on a trench wall or adjacent surface of the body of semiconductor material 11, or formed overlying a trench wall or adjacent surface of the body of semiconductor material 11, or formed adjacent to a trench wall or adjacent surface of the body of semiconductor material 11. An intrinsic semiconductor or buffer layer 24 is formed on the p-type layer 23, or formed overlying the p-type layer 23, or formed adjacent to the p-type layer 23. In one embodiment, intrinsic layer 24 comprises two or more separate layers formed at different times during the fabrication of device 10, as will be explained further below. An N-type layer 26 is formed on the intrinsic semiconductor layer 24, or formed overlying the intrinsic semiconductor layer 24, or formed adjacent to the intrinsic semiconductor layer 24, and an intrinsic semiconductor layer or buffer layer 27 is formed on the N-type layer 26, or formed overlying the N-type layer 26, or formed adjacent to the N-type layer 26. Intrinsic layer 24 serves, among other things, to prevent or reduce mixing of dopants from layers 23 and 26, which helps control charge balance and charge separation. Which in turn increases the conduction efficiency of the device 10. Intrinsic layer 27 serves, among other things, to fill, seal, or partially fill the trench.

For an n-channel device and in accordance with the present invention, when device 10 is in the on-state, n-type layer 26 provides a predominantly vertical, low-resistance current path from the channel to the drain. When device 10 is in the off state, p-type layer 23 and n-type layer 26 compensate each other to provide increased BVdss characteristics in accordance with the present invention. It should be understood that additional n-type and p-type layers may be employed, and are preferably separated by additional intrinsic or buffer layers. In an alternative embodiment, and as shown in FIG. 1, dielectric layer 28 is formed overlying the outermost layers (e.g., layers 26 and 27). In one embodiment, dielectric layer 28 fills any remaining space within trench 22. In another embodiment, dielectric layer 28 only partially fills the remaining space within trench 22, leaving, for example, an air gap or void. By way of example, dielectric layer 28 comprises an oxide or nitride or a combination thereof. In another embodiment, dielectric layer 28 comprises a thin thermal oxide covered with a thin polysilicon layer, followed by deposition of a TEOS layer. In some applications, it has been observed that the thin oxide covered with polysilicon seal reduces the shear stress from the deposited oxide, thereby improving device performance. It should also be understood that during the thermal treatment, the n-type and p-type dopants from layers 26 and 23 diffuse into the buffer layers, and these individual buffer layers may or may not be present in the final device. However, when deposited or formed, buffer layers 24 and/or 27 have a lower doping concentration than layers 23 and 26. By way of example, buffer layers 24 and/or 27 may have a doping concentration of about 10 to 100 times or less than that of layers 23 and 26.

By way of example, the doping concentration of each of the p-type layer 23 and the n-type layer 26 is about 9.0 × 10¹⁶To about 3.0X 10¹⁵Atom/cm³On the order of magnitude, and each has a thickness of about 0.1 to about 0.3 microns. In one embodiment, the intrinsic semiconductor or buffer layers 24 and 27 are undoped or doped very lightly p-type doped with a doping concentration of less than about 1.0 x 10¹⁴Atom/cm³And each has a thickness of about 0.1 microns to about 1.0 microns.

Dopants from p-type layer 23 diffuse into semiconductor layer 14 to form a p-type region or lateral doped region or lateral diffusion region 231 (shown in dashed lines). P-type regions 231 laterally diffused from adjacent trenches 22 may or may not be fully merged together as shown in fig. 1 so that a portion of semiconductor 14 is still present in the finished device. That is, the actual diffusion distance between adjacent lateral diffusion regions 231 varies.

In one embodiment, diffusion region 231 comprises a conductivity type opposite to the conductivity type of semiconductor layer 14. This embodiment provides a unique structure in which both the active device structure and the edge termination structure (not shown) are formed in the same layer (i.e., layer 14), but the active device (i.e., device 10) is on the p-type layer due to the lateral diffusion regions 231, while the edge termination structure is formed in the n-type layer 14 laterally separated from the trenches 22.

Although not shown, it should be understood that during the fabrication of device 10, n-type dopants from heavily doped substrate 12 diffuse into the lower portions of filled trenches 22, causing those portions of filled trenches 22 located within substrate 12 to become more heavily doped n-type.

Device 10 also includes a body or doped region 31 formed within semiconductor layer 14 between filled trenches 22 and proximate or adjacent to filled trenches 22 and extending from major surface 18 of the body of semiconductor material 11. In one implementation, body region 31 terminates laterally within buffer layer 24 and does not extend laterally into or counter-dope n-type region 27. In one embodiment, body region 31 comprises p-type conductivity and the doping concentration is suitable for forming an inversion layer that operates as conduction channel 45 of device 10. Body region 31 extends to a depth of about 1.0 to about 5.0 microns from major surface 18. n-type source regions 33 are formed within or within body region 31 and extend from major surface 18 to a depth of about 0.2 microns to about 0.5 microns. One or more p-type body contact regions 36 are formed within body region 31, partially within source region 33 and/or under source region 33. The body contact region 36 is arranged to provide a lower contact resistance to the body region 31 and to reduce the sheet resistance of the body region 31 under the source region 33, which suppresses parasitic bipolar effects.

In one embodiment, device 10 further includes an n-type footprint, channel connect, or drain extension 32, which is formed in an upper portion of filled trench 22. In one implementation, channel connect region 32 is formed adjacent major surface 18 and has the same doping concentration and junction depth as source region 33, and may be conveniently formed simultaneously. Channel connection region 32 is provided to connect or electrically couple channel region 45 to filled trench 22. In one embodiment and as shown in fig. 1, device 10 further includes an n-type lightly doped source region 37 adjacent, near, or juxtaposed to source region 33 and a lightly doped drain region 39 adjacent, near, or juxtaposed to channel connect region 32. By way of example, the lightly doped source region 37 and the lightly doped drain region 39 have a doping concentration that is less than the source region 33 and the channel connection region 32, respectively, as will be further described in connection with fig. 2-8.

Gate dielectric layer 43 is formed on major surface 18 adjacent body region 31 or adjacent major surface 18. In one embodiment, gate dielectric layer 43 comprises silicon oxide and has a thickness of about 0.05 microns to about 0.1 microns. In alternative embodiments, gate dielectric layer 43 comprises silicon nitride, tantalum pentoxide, titanium dioxide, barium strontium titanate, or combinations thereof, including combinations with silicon oxide, and the like.

Conductive gate regions 57 are formed on gate dielectric layer 43. In one embodiment, each conductive gate region 57 is interposed between compensation trench structure 22 and source region 33. Conductive gate regions 57 comprise, for example, n-type polysilicon and are about 0.3 microns to about 0.5 microns thick. Conductive gate regions 57, along with gate dielectric layer 43, form a control electrode or gate structure 58 of device 10. Gate structure 58 is provided to control the formation of channel 45 and the conduction of current in device 10.

Interlayer dielectric region 48 is formed overlying major surface 18 and includes, for example, a first dielectric layer 51 formed overlying conductive gate region 57 and a second dielectric layer 61 formed overlying first dielectric layer 51 and other portions of major surface 18. By way of example, dielectric layer 51 comprises silicon oxide and has a thickness of from about 0.02 microns to about 0.05 microns. Dielectric layer 61 comprises, for example, a deposited oxide and has a thickness of about 0.4 microns to about 1.0 microns.

An opening is formed on interlayer dielectric region 48 to provide contact to device 10 for source contact layer 63. As shown, a portion of major surface 18 is etched such that source contact layer 63 contacts both source regions 33 and body regions 36. In one embodiment, source contact layer 63 comprises a titanium/titanium nitride barrier layer and an aluminum silicon alloy formed over and overlying the barrier layer, among others. Drain contact layer 13 is formed on the opposite surface of the region of semiconductor material 11 and comprises, for example, a solderable metal structure such as titanium-nickel-silver, chromium-nickel-gold, or the like.

Operation of device 10 proceeds as follows. Assume that the source terminal 63 is at a potential V of 0V_sDown operation, gate region 57 receives a control voltage V_G5.0V, the voltage is greater than the conduction threshold of device 10, and drain terminal 13 is at drain potential V_DWork at 5.0 v. V_GAnd V_SCauses body regions 31 to invert (invert) under gate regions 57 to form channels 45, which channels 45 electrically connect source regions 33 to channel connection regions 32. Device current I_DFlows out of drain terminal 13, through n-type layer 26, channel connection region 32, channel 45, source region 33 to source terminal 63. Thus, current I_DFlows vertically through the n-type layer 26 to produce a low on-resistance. In one embodiment, I_D1.0 a. To convert device 10 to the off state, it would be smaller than the deviceA conduction threshold of 10 (e.g., V)_G< 5.0v) is applied to the gate region 57. This removes the trench 45, I_DNo longer through device 10. In the off state, when the depletion region from the main barrier junction spreads, the n-type layer 26 and the p-type layer 23 compensate each other, which improves BVdss.

Turning now to fig. 2-9, a method of forming the trench compensation structure 22 is described in accordance with the present invention. Fig. 2 shows an enlarged partial cross-sectional view of device 10 at an early stage of manufacture. In the above, an example of material properties of a body of semiconductor material 11 is provided in connection with fig. 1. In an early stage, first dielectric layer 40 is formed overlying major surface 18 and comprises, for example, silicon oxide about 0.05 microns to about 0.1 microns thick. Openings are then formed for p-type body region 31 and edge termination structures (not shown) using standard photolithography steps. P-type body region 31 is selectively formed in semiconductor layer 14 through a dielectric layer. In an embodiment suitable for a 600v device, boron is present at about 1.0 x 10¹³Atom/cm²And an implant energy of about 160KeV to form region 31. Next, a second dielectric layer 44 is formed overlying first dielectric layer 40, second dielectric layer 44 comprising, for example, a different material than first dielectric layer 40. By way of example, when the first dielectric layer comprises silicon oxide, the second dielectric layer 44 comprises silicon nitride. In one embodiment, the second dielectric layer 44 comprises about 0.2 microns of silicon nitride and is formed using a conventional deposition process. Next, the implanted p-type dopants are heat treated to diffuse the dopants to a desired depth to form region 31. By way of example, body region 31 has a depth of about 3.0 to about 5.0 microns.

Fig. 3 shows an enlarged partial cross-sectional view of device 10 at a subsequent stage of manufacture. Hardmask layer 71 is formed overlying major surface 18 and patterned to form an opening 72 through hardmask layer 71, second dielectric layer 44, and first dielectric layer 40to expose a portion of major surface 18. By way of example, the hard mask layer 71 comprises about 1.0 micron of deposited oxide. By way of example, the width of the opening 72 is on the order of about 3.0 microns to about 5.0 microns.

Next, a trench 122 is formed through the semiconductor layer 14. In one embodiment, the trench 122 extends into at least a portion of the substrate 12. The depth of the trench 122 is determined by the thickness of the semiconductor layer 14, which varies with BVdss. The process of the present invention is suitable for high aspect ratio trenches from 10: 1 (depth to width) to about 30: 1. However, this method is also suitable for low aspect ratios. In one embodiment, the depth 75 of the grooves 122 is as deep as about 50 to 60 microns. In one embodiment, trench 122 is formed using Deep Reactive Ion Etching (DRIE) etching based on fluorine or chlorine chemistry. Several processes can be used for DRIE etching, including low temperature, high density plasma processes or BoschDRIE processes. In one embodiment, the slots 122 have substantially vertical sidewalls.

In an alternative embodiment, the grooves 122 have a tapered profile, wherein the depth of the grooves is less than the width 74 at the lower surface of the grooves. In one embodiment, the slot 122 has a wall taper of between about 0.5 degrees and about 1.0 degrees and has a substantially flat bottom or lower surface 123. It has been found that a slight taper is helpful in the epitaxial growth process as compared to a trench having a rounded lower surface, as is the case with the substantially flat lower surface 123. In particular, trenches with rounded or curved lower surfaces can lead to uneven epitaxial growth filling as a result of preferred growth of silicon on low index planes (low index planes), such as the 110, 111, and 100 planes.

Although the slot 122 is depicted as a plurality, it should be understood that the slot 122 may be a single continuous slot or an array of connected slots. Alternatively, trenches 122 may be a plurality of individual trenches having closed ends and separated by portions of the body of semiconductor material 11.

Fig. 4 shows an enlarged partial cross-sectional view of device 10 at yet another stage of manufacture. At this point, as a first stage in forming filled trenches 22, a layer of semiconductor material is formed, grown or deposited in trenches 122. In one embodiment, trenches 122 are filled or partially filled using single crystal semiconductor epitaxial growth techniques. That is, a single crystal or single crystal semiconductor layer is grown within the trenches 122. Monocrystalline semiconductor layers are preferred over polycrystalline layers because polycrystalline layers result in higher leakage currents, which adversely affect device performance.

In a first stage, the body of semiconductor material 11 is subjected to a conventional pre-diffusion clean, and then a thin thermal oxide (not shown) is formed on the sidewalls and lower surfaces of trenches 122 to remove any surface damage (e.g., dishing) caused by the DRIE stage. The thin thermal oxide is then removed using a conventional isotropic etch process (e.g., 10: 1 wet oxide removal). Next, a body of semiconductor material 11 is placed onto the epitaxial growth reactor and subjected to a precleaning as a first step of the epitaxial growth process. By way of example, an ASM E2000 epitaxial reactor was utilized. In conventional epitaxial growth processes, a precleaning step is typically performed at a temperature of from 1150 degrees celsius to 1200 degrees celsius for more than 10 minutes. However, it has been found that this conventional preclean temperature range can cause undercutting at the interface of surface 18 and dielectric layer 40, which can adversely affect subsequent growth of the epitaxial layers and the resulting structure. This effect has been thought to result from semiconductor atom (e.g., silicon) migration caused by interfacial stress. The undercut and migration effects cause expansion of these regions and further result in excessive growth of poly at the top portion of the structure during subsequent epitaxial growth. These problems, in turn, limit subsequent wafer fabrication and also affect the quality and reliability of the resulting devices.

In one embodiment, the body of semiconductor material 11 is pre-cleaned at a temperature of less than 1150 degrees celsius in a hydrogen atmosphere. In one embodiment, in a hydrogen atmosphere, at a temperature of from about 1040 degrees Celsius to about 1060 degrees Celsius, at less than about 540kgf/m²Pre-clean for 60 seconds at reduced pressure (less than about 40 Torr). In another embodiment, about 270kgf/m is employed²To about 540kgf/m²(between about 20Torr to about 40 Torr). This in-situ desorption precleaning step was found to minimize the undercut phenomenon of the interface and help ensure very clean surfaces (e.g., free of oxide and contaminant traces) along trenches 122 for single crystal epitaxyThis is desirable for growth.

The following description sets forth alternative epitaxial growth methods for forming layer 23 and first intrinsic layer 233 in accordance with the present invention. Following the pre-cleaning step described above, a p-type layer 23 is grown overlying the surface of the trenches 122. In one embodiment, a dichlorosilane (dichlorosilane) source gas is utilized at a growth temperature ranging from about 1050 ± 50 degrees celsius at less than about 540kgf/m²The p-type layer 23 is formed at a reduced pressure (less than about 40 Torr).

In one embodiment, the p-type layer 23 is selectively formed in an isothermal process using the following conditions: about 40 standard liters (slm) of hydrogen and about 250 to about 500 cubic meters (cc) of dichlorosilane. In one embodiment, the flow rate of HCl used is about 1.5 to about 3 times the flow rate of dichlorosilane. A suitable boron dopant source (e.g., diborane) is used to dope the p-type layer 23 at a concentration of about 3.0 x 10¹⁶To about 9.0X 10¹⁶Atom/cm²On the order of magnitude and about 0.1 to 0.3 microns thick.

Next, the boron dopant source is turned off, the reactor chamber is purged, and the first intrinsic layer 233 is formed overlying the p-type layer 23. In one embodiment, the intrinsic layer 233 has a thickness of about 0.1 microns to about 0.2 microns. A cap layer 234 is then formed overlying layer 233 and comprises, for example, thermal oxide of about 0.05 microns and nitride of about 0.1 microns. Device 10 is then primarily heated to laterally diffuse p-type dopants from layer 23 into semiconductor layer 14 to form laterally diffused p-type region 231. In one embodiment, an annealing step is performed at about 1100 degrees celsius for about 2 hours, which step and adjustments made to achieve the desired migration of dopants into layer 14.

During the heat treatment stage, layer 234 is disposed overlying p-type layer 23 and intrinsic layer 233 to prevent out-diffusion of dopants from layer 23. Also, during the heat treatment stage, n-type dopants from substrate 12 diffuse into portion 1200 of layer 23, converting portion 1200 to n-type. In addition, the p-type dopant in layer 23 diffuses into the intrinsic layer 233, converting the intrinsic layer 233 into a p-type layer 23, which is shown as a continuous layer in fig. 5-9. After the heat treatment stage, the capping layer 234 is removed using conventional etching techniques.

Turning now to fig. 5, an intrinsic or buffer layer 24 is grown overlying the p-type layer 23 and is either undoped or very lightly doped p-type with a doping concentration of less than about 2.0 x 10¹⁴Atom/cm³. Layer 24 has a thickness of about 0.5 microns to about 1.5 microns. In one embodiment, the intrinsic layer 24 is selectively formed in an isothermal process using the following flow conditions: about 40 liters (slm) of hydrogen and about 250 to about 500 cubic meters (cc) of dichlorosilane. In one embodiment, the flow rate of HCl used is about 1.5 to about 3 times the flow rate of dichlorosilane.

Next, an N-type layer 26 is selectively grown overlying layer 24 under the same growth conditions set for layer 24, except that an N-type dopant such as phosphorus, arsenic or antimony is added. In one embodiment, the doping concentration of the n-type layer 26 is about 1.5 x 10¹⁶To about 4.5X 10¹⁶Atom/cm³And a thickness of about 02 microns to about 04 microns. In one embodiment, a purge cycle is employed after the n-type layer 26 is grown, and before the intrinsic layer 27 is grown. It has been found that purging the dopant gas or gases after the n-type layer 26 is formed provides an n-type layer 26 with a steeper dopant profile, which improves the charge compensation effect of the device 10. By way of example, in high flow hydrogen, a purge cycle of 30 to 60 seconds is sufficient. However, a purge time that is too long can result in out-diffusion of dopants from layer 26.

Next, an intrinsic or buffer layer 27 is grown on the n-type layer 26. In one embodiment, layer 27 is formed using growth conditions similar to those used for layers 23, 24 and 26. Next, a thin wet oxide is grown on layer 27, followed by the formation of dielectric layer 28, which comprises, for example, a deposited oxide having a thickness suitable to fill trenches 122. In one embodiment, dielectric layer 28 is formed using multiple steps with an etch-back or planarization step between the deposition steps to ensure that trenches 122 are filled to a desired height. It should be understood that the thickness of layers 23, 24, 26, 27 and 28 is adjusted according to the width of slot 122.

Fig. 6 shows an enlarged partial cross-sectional view of device 10 at yet another step of fabrication after layer 28 is planarized down, planarized back, or otherwise proximate to major surface 18 to form filled trenches 122. By way of example, these layers are planarized using etch-back or chemical mechanical planarization techniques. In one embodiment, a polysilicon layer and a photoresist layer are formed overlying dielectric layer 28, and these layers are then etched back or planarized using second dielectric layer 44 as a stop layer. Layers 44 and 40 are then removed using conventional processes.

Next, gate dielectric layer 43 is formed overlying major surface 18. In one embodiment, gate dielectric layer 43 comprises silicon oxide and has a thickness of about 0.05 microns to about 0.1 microns. A conductive layer, such as a doped or undoped polysilicon layer, is deposited overlying gate dielectric layer 43 and patterned to form gate conductive regions 57. For example, the gate conductive region 57 comprises about 0.2 microns of doped or undoped polysilicon. If the gate conductive regions begin to be undoped, these regions will be subsequently doped during the formation of regions 32 and 33. Note that in one embodiment, gate conductive region 57 is separated from (i.e., does not overlap) filled trenches 22 by a distance 58 to allow for the use of spacer techniques to form regions 32, 33, 37, and 39 in accordance with the present invention.

Next, a passivation layer is formed overlying major surface 18 and patterned to form first dielectric layer 51. By way of example, the first dielectric layer includes about 0.02 to about 0.1 microns of oxide. Then, a spacer layer is formed overlying major surface 18 and etched to form spacers 116. By way of example, the spacers 116 comprise polysilicon that is about 0.2 microns thick. It should be understood that the thickness of the dividers 116 is adjusted according to the desired lateral width of the regions 37 and 39. Channel connection region 32 and source region 33 are subsequently formed, self-aligned to spacer 116. By way of example, 3.0 × 10¹⁵Atom/cm²The phosphorus implant dose and the implant energy of 80KeV were used for this doping step. Implanted dopants or desizing during this stepFire and diffusion, or annealing after forming other doped regions described below.

Fig. 7 shows an enlarged partial cross-sectional view of device 10 at another step in fabrication. Spacer 116 is removed and then lightly doped source region 37 and lightly doped drain region 39 are formed adjacent source region 33 and channel connection region 32, respectively. By way of example, about 1.0X 10¹⁴To about 3.0X 10¹⁴Atom/cm²The phosphorus implant dose and the implant energy of 60KeV were used for this doping step.

Fig. 8 shows an enlarged partial cross-sectional view of device 10 after additional processing. A passivation or dielectric layer 61 is formed overlying major surface 18. By way of example, layer 61 comprises a deposited oxide and has a thickness of about 0.5 microns to 1.0 microns. Opening 91 is formed using a contact photo-etching step to expose a portion of major surface 18 over source region 33. Next, an optional conformal spacer is formed overlying major surface 18 and etched to form spacers (not shown) on sidewalls of layer 61 within opening 91. The opening 91 near the outer surface of layer 61 as shown in fig. 9 is widened using an optional isothermal etch. Major surface 18 is then exposed to an etchant that removes material from semiconductor layer 14 to form recessed regions 99. Next, the body contact region 36 is formed through the opening 91 and the recess region 99. In one embodiment, a series or series of implants is employed such that the body contact region 36 includes a plurality of regions as shown in fig. 9. In one embodiment, three boron implants are employed with increasing implant energy to provide the pyramidal shape shown in fig. 9. That is, higher ion implant energies provide deeper and wider regions, while lower implant energies provide shallower and narrower regions. By way of example, from about 1.0X 10¹⁴Atom/cm²To about 1.0X 10¹⁵Atom/cm²And an implant energy of about 200KeV, using from about 1.0 x 10¹⁴Atom/cm²To about 1.0X 10¹⁵Atom/cm²A second boron implant with a dopant dose of about 100KeV, and then from about 1.0 x 10¹⁴Atom/cm²To about 1.0X 10¹⁵Atom/cm²A third boron implantation to form region 36 with an implant energy of 25-30 KeV. In an alternative method, body contact regions 36 are formed using conventional masking techniques prior to forming dielectric layer 61. A dielectric layer 61 and subsequent patterning are then formed.

After forming body contact regions 36, the spacers are removed from openings 91 and a source contact or conductive layer 63 is formed overlying major surface 18. By way of example, a barrier structure, such as titanium/titanium nitride, is formed, followed by a layer comprising aluminum or an aluminum alloy. The conductive layer is then patterned using conventional photolithography and etching processes to form the source contact layer 63 as shown in fig. 1. In one embodiment, a final passivation layer is utilized overlying the source contact layer 63, and the final passivation layer comprises deposited oxide, deposited nitride, or a combination thereof. The device 10 is then thinned to form a drain contact layer 13 that contacts the substrate 12, as shown in fig. 1 and described further in connection with fig. 1.

Fig. 9 shows an enlarged partial cross-sectional view of a charge compensation trench structure device 101 at an intermediate step in the fabrication, in accordance with an alternative embodiment of the present invention. Device 101 is similar to device 10 except that in device 101, a modified epitaxial growth method is used in growing layers 24, 26, and/or 27. For example, during the growth of one or more of these layers, a polycrystalline semiconductor layer or more than one polycrystalline semiconductor layer 114 overlying dielectric layers 71, 44, and 40 is formed using non-selective epitaxial growth. By way of example, polycrystalline semiconductor layer 113 comprises a layer of polysilicon and is used to provide conductive or resistive structures, such as gate feeds, resistors, capacitive plates, and the like, for other features of device 101. Layer 113 is formed at a suitable growth stage (i.e., during growth of layers 24, 26, and/or 27) depending on the desired thickness. That is, if a thicker polycrystalline layer is desired, then layer 113 of tape layer 24 is formed. If a thinner polycrystalline layer is desired, a layer 113 with layers 26 or 27 is formed.

By way of example, in forming layers 24, 26, and/or 27, layer 113 is formed using the following growth conditions. First, a non-selective thin epitaxial layer is grown using a silane source gas, which forms a polycrystalline seed layer overlying the dielectric material and a single crystal layer on the exposed single crystal semiconductor material within the trench 1200. In one embodiment, HCl is not used with the silane source gas. Next, the remaining single crystal semiconductor layer in the trench region is formed using dichlorodihydroalkane source gas using the process conditions described in connection with fig. 4 and 5. In this step, the thickness of the polycrystalline layer 113 is also increased.

The method of the present invention provides fully repeatable single crystal epitaxial growth with low thickness variation across the wafer of less than +/-5%, charge balance control of about 4-5%, and charge target accuracy (charge targeting accuracy) within about 1-2%. These features are critical in manufacturing cost-effective charge compensation devices.

In summary, a method of manufacturing a semiconductor device having a deep trench charge compensation structure has been described. The method includes forming a trench within a body of semiconductor material and then growing or depositing a plurality of single crystal semiconductor layers within the trench. A reduced temperature hydrogen purge step is employed prior to growing the first monocrystalline semiconductor layer to reduce undercut effects and improve growth characteristics of the structure. After forming one of the doped monocrystalline semiconductor layers, a short purge step is employed to improve control over the doping profile of the layer. In one embodiment, a mixture of source gases is utilized to selectively and non-selectively form portions of the trench structure.

While the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these exemplary embodiments. For example, the method may be used to form other semiconductors including silicon/carbon, silicon/germanium, silicon/carbon/germanium, gallium arsenide, indium phosphide, and other materials. Those skilled in the art will recognize that changes and modifications may be made without departing from the spirit of the invention. Accordingly, it is intended that the present invention cover all such modifications and variations as fall within the scope of the invention as defined by the appended claims.

Claims (10)

1. A method of forming a semiconductor device, comprising the steps of:

providing a region of semiconductor material having a first major surface, a dielectric region overlying the first major surface, and a trench formed within the region of semiconductor material;

exposing the surface of the cell to a hydrogenolysis adsorption process at a temperature in the range from 1000 degrees Celsius to less than 1100 degrees Celsius; and

after the step of exposing the surface of the tank to a hydrogenolysis adsorption process, a plurality of single crystal semiconductor layers are formed overlying the surface of the tank.

2. The method of claim 1, wherein the exposing comprises exposing at less than 540kgf/m²And wherein the step of exposing comprises exposing the surface to the hydrogenolysis adsorption process for a time less than 60 seconds.

3. The method of claim 1, wherein the step of forming a plurality of single crystal semiconductor layers comprises selectively forming at least one single crystal semiconductor layer using a dichlorodihydrosilicon source gas.

4. The method of claim 1, wherein the step of forming a plurality of single crystal semiconductor layers comprises forming a trench charge compensation structure.

5. The method of claim 4, further comprising the steps of:

forming a body region within the region of semiconductor material proximate the first major surface;

forming a source region in the body region and laterally spaced apart from the trench charge compensation structure;

forming a gate structure between the source region and the trench charge compensation structure, wherein the gate structure comprises a conductive gate region arranged to form a channel region within the body region when the device is in operation; and

a channel connection region formed at an upper portion of the trench charge compensation structure and configured to electrically connect the channel region to the trench charge compensation structure when the device is in operation.

6. The method of claim 1, wherein the step of forming a plurality of single crystal semiconductor layers comprises the steps of:

selectively forming a first single crystal semiconductor layer of a second conductivity type overlying sidewalls and a lower surface of the trench;

forming a first buffer layer overlying the first monocrystalline semiconductor layer, wherein the first buffer layer has a lower doping concentration than the first monocrystalline semiconductor layer when deposited; and

forming a second monocrystalline semiconductor layer of a first conductivity type overlying the first buffer layer, the first conductivity type being opposite the second conductivity type.

7. A method of forming a semiconductor device, comprising the steps of:

providing a region of semiconductor material having a first major surface, a dielectric region overlying the first major surface, and a trench formed within the region of semiconductor material;

at a temperature in the range from 1000 ℃ to less than 1100 ℃, at less than 540kgf/m²Exposing the surface of the cell to a hydrogenolysis adsorption process at a reduced pressure; and

after the step of exposing the surface of the bath to a hydrogenolysis adsorption process, a plurality of single crystal semiconductor layers are formed overlying the surface of the bath, wherein at least two layers comprise opposite conductivity types and wherein an intrinsic layer separates the at least two layers.

8. The method of claim 7, wherein the step of forming a plurality of single crystal semiconductor layers comprises selectively forming at least one of the at least two layers.

9. A method of forming a semiconductor device having a trench charge compensation structure, comprising the steps of:

providing a body of semiconductor material having a first major surface;

forming a trench within the body of semiconductor material, the trench extending from the first major surface, wherein the trench has an aspect ratio of from 10: 1 to 30: 1;

in the presence of hydrogen, at less than 540kgf/m²Exposing the surface of the groove to reduced pressureIn a temperature range from 1000 ℃ to less than 1100 ℃;

forming a first single crystal semiconductor layer overlying a surface of the trench after the step of exposing the surface of the trench to a temperature range from 1000 degrees Celsius to less than 1100 degrees Celsius, wherein the first single crystal semiconductor layer has a first conductivity type;

forming a first buffer layer overlying the first monocrystalline semiconductor layer, wherein a doping concentration of the first buffer layer is at least one order of magnitude less than a doping concentration of the first monocrystalline semiconductor layer;

exposing the body of semiconductor material to an elevated temperature to redistribute dopants from the first monocrystalline semiconductor layer into the body of semiconductor material;

forming a second buffer layer overlying the first buffer layer; and

forming a second single crystal semiconductor layer overlying the second buffer layer, wherein the second single crystal semiconductor layer comprises a second conductivity type opposite the first conductivity type.

10. The method of claim 9, wherein the step of exposing the surface comprises exposing the surface for a time of less than 60 seconds.