HK1093117B - Semiconductor device having deep trench charge compensation regions and method - Google Patents

Description

Semiconductor device with deep trench charge compensation region and method

Technical Field

The present invention relates generally to semiconductor devices, and more particularly, to power switching devices and methods of making the same.

Background

Metal-oxide semiconductor field effect transistors (MOSFETS) are a common type of power switching device. A MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure provided adjacent the channel region, the gate structure including a conductive gate electrode layer disposed adjacent the channel region but separated therefrom by a thin dielectric layer.

When a MOSFET device is in an on state, a voltage is applied to the gate structure to form a conductive channel region between the source and drain regions, thereby allowing current to flow through the device. In the off state, any voltage applied to the gate structure is sufficiently small that a conductive channel is not formed and current flow is not generated. In the off state, the device must withstand a high voltage between the source and drain regions.

The current market for high voltage power switches is driven by two main parameters: breakdown voltage (BVdss) and on-resistance (Rdson). For a particular application, a minimum breakdown voltage is required, and in practice, designers are often able to meet a breakdown voltage specification. However, this often comes at the expense of an increase in on-resistance. This compromise in performance is a major design challenge for manufacturers and users of high voltage power switching devices.

Recently, super junction deVices (superjunction deVices) have been widely used to improve the situation where it is not easy to compromise between breakdown voltage and on-resistance. In a scaled n-channel superjunction device, an counterdoped n-type epitaxial region is replaced with a plurality of highly doped diffused n-type and p-type regions. In the on state, current flows through the highly doped n-type region, which causes Rdson to become smaller. While in the off state, the highly doped n-type and p-type regions deplete or compensate each other to provide a high BVdss. Although superjunction devices appear promising, significant challenges remain in manufacturing.

Another problem with current high voltage power switch products is that they typically require a large input (e.g., gate or control electrode) charge to transition from one state to another. This requirement places an additional burden on the external control circuitry, among other effects.

Disclosure of Invention

Thus, there is a need for high voltage power switching device structures and methods of making the same that provide low Rdson, high BVdss, and small input charge.

Thus, in one aspect, the present invention provides a semiconductor device characterized by: a body of semiconductor material; and a charge compensation region comprising a trench formed in the body of semiconductor material, wherein the trench is characterized by at least two epitaxial semiconductor layers of opposite conductivity types, wherein one of the at least two epitaxial semiconductor layers is formed contiguous with a surface of the trench, and wherein the at least two epitaxial semiconductor layers are separated by an intrinsic layer.

In another aspect, the present invention provides a semiconductor device characterized in that: a body of semiconductor material having first and second opposed major surfaces; a first doped region formed in the body of semiconductor material adjacent the first major surface and characterized by a first conductivity type; a second doped region formed in the first doped region and characterized by a second conductivity type; a charge compensating trench region formed in the body of semiconductor material adjacent to the first doped region, wherein the charge compensating trench region is characterized by: a slot; a first epitaxial semiconductor layer of a second conductivity type formed in connection with a surface of the trench; an intrinsic layer formed on the first epitaxial semiconductor layer; and a second epitaxial semiconductor layer of the first conductivity type formed on the intrinsic layer, wherein the intrinsic layer is between the first and second epitaxial semiconductor layers to reduce intermixing of opposite conductivity dopants; and a control electrode formed adjacent to the first and second doped regions.

In another aspect, the present invention provides a method of forming a semiconductor device, characterized by the steps of: providing a body of semiconductor material having first and second opposed major surfaces; forming a trench in a body of semiconductor material; forming a first epitaxial semiconductor layer of the first conductivity type in contact with the surface of the trench; forming an intrinsic layer on the first epitaxial semiconductor layer; forming a second epitaxial semiconductor layer of a second conductivity type adjacent to said first epitaxial semiconductor layer to form a charge compensation trench region, wherein said intrinsic layer is between said first and second epitaxial semiconductor layers to reduce intermixing of opposite conductivity dopants; forming a first doped region in the body of semiconductor material adjacent the charge compensation trench region, wherein the first doped region has a second conductivity type; forming a second doped region in the first doped region, the second doped region having the first conductivity type; and forming a control electrode adjacent to the first and second doped regions.

Drawings

FIG. 1 is an enlarged partial cross-sectional view of a switching device according to the present invention;

FIGS. 2 through 7 provide enlarged partial cross-sectional views of the switching device of FIG. 1 at various stages of manufacture;

fig. 8 is a graph showing breakdown voltage characteristics of the switching device of fig. 1;

FIG. 9 is a graph showing the on-resistance characteristics of the switching device of FIG. 1;

fig. 10 shows an enlarged partial top view of a cell structure suitable for use in a switching device according to the present invention.

Fig. 11 is an enlarged partial cross-sectional view of a switching device and edge termination structure in accordance with the present invention.

Fig. 12 is an enlarged partial top view of another trench isolation structure in accordance with the present invention.

FIG. 13 shows an enlarged partial cross-sectional view of the trench isolation structure of FIG. 12 at an early stage of fabrication, taken along reference line 13-13.

FIG. 14 is an enlarged partial cross-sectional view of the structure of FIG. 13 after further processing; and

fig. 15 is an enlarged partial cross-sectional view of another trench isolation structure in accordance with the present invention.

Detailed Description

For ease of understanding, elements in the figures are not necessarily drawn to scale, and the same element numbers are used in the various figures, as appropriate. Although the following discussion describes an n-channel device, the invention is also applicable to p-channel devices, which may be formed by reversing the conductivity types of the layers and regions.

In addition, the device of the present invention may be embodied as a honeycomb design (where the bulk region is a plurality of honeycomb regions), or a monolithic design (where the bulk region is comprised of a single region formed in an elongated shape, typically in a serpentine pattern). However, throughout the description, for ease of understanding, the device of the present invention will be described as a honeycomb design. It should be understood that we claim the invention to include both mesh and single base designs.

Fig. 1 shows an enlarged partial cross-sectional view of an Insulated Gate Field Effect Transistor (IGFET), MOSFET, super junction device, or switching device, or honeycomb design cell 10 according to the present invention. By way of example, device 10 is one of many such devices that are integrated into a semiconductor chip as part of a power integrated circuit along with logic and/or other components. Device 10 may also be one of many such devices that are integrated together to form a discrete transistor device.

The device 10 includes a semiconductor material 11 comprising, for example, an n-type silicon substrate 12 having a resistivity in the range of about 0.001 to about 0.005 ohm-cm, and which may be doped with arsenic. In the embodiment shown, the substrate 12 provides a drain contact. A semiconductor layer 14 is formed in the substrate 12 or on the substrate 12 and, in accordance with the present invention, is lightly doped with an n-type or p-type impurity or contains a negligible amount of impurity (i.e., it is intrinsic). In an exemplary embodiment, layer 14 is formed using conventional epitaxial growth techniques. In one exemplary embodiment suitable for use in a 750-slave device, layer 14 is p-type with a doping concentration of about 1.0 x 10¹³Atom/cm³To about 5.0X 10¹³Atom/cm³. And a thickness of about 40 μm. The thickness of layer 14 increases or decreases depending on the desired BVdss rating of device 10. Of course, other materials, including silicon-germanium, silicon-germanium-carbon, silicon-doped carbon, or the like may be used for or as part of the body of semiconductor material 11.

Device 10 also includes an n-type region or cap 17 formed in or adjacent to the upper or major surface of semiconductor material 11. N-type region 17 provides a low resistance current path for device 10, as will be described in more detail below. In one exemplary embodiment, n-type region 17 has a thickness of about 6.0 x 10¹⁶Atom/cm³And a depth of about 0.4 microns. A P-type region or cladding layer 19 may also be formed in or adjacent to major surface 18 and below or adjacent to n-type region 17. P-type region 19 provides better control of the pn junction between n-type region 17 and semiconductor layer 14 and provides charge compensation for n-type region 17 under fully depleted conditions. In an exemplary embodiment, p-type region 19 has a thickness of about 5.0X 10¹⁵Atom/cm³And a depth of about 0.8 microns.

The device 10 according to the invention further comprises a filled trench, a semiconductor material filled trench, an epitaxial filled region or trench, a charge compensated trench region, a deep trench charge compensation region, a charge compensated filled trench or charge compensation region 22. The charge compensating filled trenches 22 comprise a plurality of layers or layers of semiconductor material, including layers of opposite conductivity type, preferably separated by one or n intrinsic or buffer semiconductor layers. The intrinsic layer, among other things, serves to prevent internal intermixing of the opposite conductivity type layers (i.e., the two charge layers) that would adversely affect the conduction efficiency of the device 10 in the on state.

In an exemplary embodiment, filled trenches 22 comprise a plurality of layers or stacks of semiconductor materials formed using epitaxial growth techniques. The filled trench 22 includes, for example, an n-type layer 23 formed on or adjacent to a wall of the trench or surface adjacent the body of semiconductor material 11. And an intrinsic semiconductor or buffer layer 24 is formed on or adjacent to the n-type layer 23, a p-type layer 26 is formed on or adjacent to the intrinsic semiconductor layer 24, and an intrinsic semiconductor or buffer layer 27 is formed on or adjacent to the p-type layer 26. Intrinsic layer 24, among other things, serves to prevent intermixing of layers 23 and 26, which, as previously described, improves the conduction efficiency of device 10. The intrinsic layer 27, among other things, serves to fill the remaining space of the trench. For an n-channel device, and in accordance with the present invention, n-type layer 23 provides a primary vertical low resistance current path from the channel to the drain when device 10 is in the on state. When device 10 is in the off state, n-type layer 23 and p-type layer 26 compensate each other to provide an improved BVdss characteristic in accordance with the present invention. Additional n-type and p-type layers may of course also be used, and they are preferably separated by additional intrinsic or buffer layers.

By way of example, n-type layer 23 and p-type layer 26 each have a thickness of about 2.0 x 10¹⁶To about 4.0X 10¹⁶Atom/cm³Have a thickness of about 0.1 μm to about 0.3 μm, respectively. In an exemplary embodiment, the intrinsic semiconductor or buffer layers 24 and 27, which are undoped or very lightly p-doped, have a doping concentration of less than about 2.0 x 10¹⁴Atom/cm³And each has a thickness of about 0.5 μm to about 1.0 μm. The thickness of layer 27 is adjusted, for example, to fill the remainder of the trench.

A body or doped region 31 is formed within semiconductor layer 14 between and adjacent to filled trenches 22 and extends downwardly from major surface 18. In an exemplary embodiment, body region 31 has p-type conductivity and, as described below, has a doping concentration suitable for forming an inversion layer that serves as a conduction channel 45 of device 10. Body region 31 extends downwardly from major surface 18 to a depth of about 1.0 to about 5.0 μm. An n-type source region 33 is formed within body region 31 and extends downwardly from major surface 18 to a depth of about 0.2 to about 0.5 μm. A p-type body contact or contact region 36 is also formed in body region 31 and provides a low contact resistance to body region 31 at major surface 18. In addition contact region 36 reduces the sheet resistance of body region 31 below source region 33, which suppresses parasitic bipolar effects.

A first dielectric layer 41 overlies or is adjacent to a portion of major surface 18. In one exemplary embodiment, dielectric layer 41 comprises a thermal oxide layer having a thickness of about 0.1 μm to about 0.2 μm. A second dielectric layer 42 is formed on dielectric layer 41. In one exemplary embodiment, the second dielectric layer comprises silicon nitride and has a thickness of about 0.1 μm.

A gate dielectric layer 43 is formed on or adjacent another portion of major surface 18 adjacent body region 31. In one exemplary embodiment, gate dielectric layer 43 comprises silicon dioxide having a thickness of about 0.05 μm to about 0.1 μm. In another embodiment, gate dielectric layer 43 comprises silicon nitride, tantalum pentoxide, titanium dioxide, molybdenum strontium titanate, or combinations thereof, including combinations with silicon dioxide or the like.

In accordance with one embodiment of the present invention, a doped polycrystalline semiconductor layer, conductive layer, or ground plane layer 46 is formed on dielectric layers 41 and 42 and contacts p-type layer 26 through openings formed in dielectric layers 41 and 42. In an exemplary embodiment, conductive layer 46 comprises a polysilicon layer having a thickness of about 0.1 μm and a p-type conductivity for an n-channel device, and upon thermal treatment, p-type impurities diffuse from conductive layer 46 into filled trenches 22 to form p-type doped regions 52, which enhance ohmic contact to p-type layer 26. In another embodiment, the conductive layer 46 comprises amorphous silicon, a metal, a silicide or combinations thereof, including combinations with polysilicon. If a metal is used for conductive layer 46, p-type impurities are first implanted or deposited through opening 47 to form p-type doped region 52, thereby enhancing ohmic contact to p-type layer 26. The conductive layer 46 is preferably directly or indirectly connected or coupled to a conductive contact or source contact layer 63 as shown in fig. 1.

In accordance with the present invention, the conductive layer 46 functions as a ground plane, among other things, to provide a path for minority carriers to be swept out of the device more quickly and efficiently, thereby reducing the input charge required to turn the switching device 10 from one state to another, and increasing switching speed. In addition, as will be explained in greater detail below, the conductive layer 46 is also used as part of an edge termination structure in accordance with the present invention.

A third dielectric layer 48 is formed overlying conductive layer 46 and a fourth dielectric layer 51 is formed overlying the third dielectric layer. In one exemplary embodiment, dielectric layer 48 comprises silicon nitride (e.g., about 0.05 μm thick) and dielectric layer 51 comprises a deposited silicon dioxide (e.g., about 0.7 μm thick). A conductive layer 53 comprising, for example, n-type polysilicon (e.g., 0.3 μm thick) is formed over dielectric layer 51.

A conductive spacer gate region, a vertical spacer gate region, or spacer-defined gate region 57 is formed on gate dielectric layer 43 and is separated from conductive layer 46 by dielectric spacer 59. The conductive spacer gate region 57 and the gate dielectric form a control electrode or gate structure 58. The conductive spacer gate region 57 comprises, for example, n-type polysilicon and is approximately 0.8 μm thick. In one exemplary embodiment, the dielectric spacers 59 comprise silicon nitride and are about 0.1 μm thick. Spacer gate region 57 is coupled to conductive layer 53 to provide a conductive gate structure that controls the formation of channel 45 and the conduction of current in device 10. In the embodiment shown, a conductive connection region 77 couples the spacer gate region 57 to the conductive layer 53. The conductive connection region 77 comprises, for example, n-type polysilicon. A spacer gate refers to a control electrode formed with a gate material deposited on one surface to control a channel formed on the other vertical surface. In the case of device 10, channel 45 is formed at surface 18, which is considered a horizontal surface. The control electrode film used to form the spacer gate regions 57 is deposited along a vertical surface 68 which is perpendicular to the surface 18.

The conductive spacer gate region 57 according to the present invention provides a minimum gate-to-drain overlap compared to conventional devices, thereby significantly reducing the gate charge. In addition, in device 10, the electrical path to the gate is provided by conductive layer 53, which is raised above major surface 18, thereby further reducing the gate charge. In addition, conductive layer 46, among other things, serves as a ground plane interposed between the gate and drain regions, thereby further reducing the gate to drain capacitance. These features of the present invention provide increased switching rates and reduced input charge requirements.

A fifth dielectric layer 61 comprising, for example, silicon nitride having a thickness of about 0.5 μm is formed over portions of device 10. An interlayer dielectric (ILD) layer 62 comprising, for example, deposited silicon dioxide having a thickness of about 0.8 um is formed over portions of the device 10. An opening is formed in each dielectric layer for source contact layer 63 to provide a contact to device 10. As shown, a portion of major surface 18 is etched to bring source contact layer 63 into contact with both source regions 33 and body regions 36. In an exemplary embodiment, the source contact layer 63 comprises an aluminum silicon alloy or the like. A drain contact layer 66 is formed on the opposite side of semiconductor material 11 and comprises, for example, a solderable metal structure such as titanium-nickel-silver, chromium-nickel-gold, or the like.

The operation of the device 10 proceeds as follows. Assume that the source terminal 63 is applied with a potential V of zero volts_s. And the spacer gate region 57 receives a control voltage V_G5.0 volts, which is greater than the turn-on threshold of device 10, drain terminal 66 is applied with a drain potential V_D5.0 volts. V_GAnd V_sCauses body region 31 to invert under spacer gate region 57 to form a channel 45 which electrically connects source region 33 to layer 17. A device current I_sFlows from source terminal 63, through source region 33, channel 45, layer 17, n-type layer 23, and to drain terminal 66. Thus the current I_sFlows vertically through the n-type layer 23 to create a small on-resistance. In one embodiment, I_s1.0 ampere. To turn device 10 to the off state, it applies a control voltage V that is less than the device turn-on threshold_GTo the spacer grid 57 (e.g. V)_G< 5.0V). This causes the channel to disappear, I_sNo longer flows through device 10 and conductive layer 46 sweeps minority carriers out of the device. In the off state, the n-type layer 23 and the p-type layer 26 compensate each other as a depletion region from the diffusion of the main barrier junction, thereby improving BVdss. In one embodiment, the main barrier junction is formed by body region 31 and semiconductor layer 14, where layer 14 is n-type. In another embodiment, the primary barrier junction is formed by semiconductor layer 14 and substrate 12, where layer 14 is p-type.

Turning now to fig. 2-7, the formation of a device 10 in accordance with the present invention is depicted. FIG. 2 shows a process inAn enlarged partial cross-sectional view of device 10 at an early stage of manufacture. In an early step, a dielectric layer 40 is formed on major surface 18, and an optional p-type region 19 is ion implanted through dielectric layer 40 into semiconductor layer 14. In one exemplary embodiment, boron is implanted at a dose of about 5.0 x 10¹¹Atom/cm²And the implantation energy is 600keV to form the p-type layer 19. Next, the n-type layer 17 is ion-implanted into the semiconductor layer 14 through the dielectric layer 40. In one exemplary embodiment, phosphorus is implanted at a dose of about 2.0X 10¹²Atom/cm²The implantation energy is 600keV to form the n-type layer 17.

Masking layer 71 is then formed on major surface 18 and patterned to form openings 72. Dielectric layer 40 is then etched in a conventional manner to expose portions of body of semiconductor material 11 through openings 72. By way of example, the width 74 of the opening 72 is on the order of about 3.0 μm to about 5.0 μm. Trenches 122 are then etched through layers 17, 19 and 14. In one exemplary embodiment, the slot 122 extends at least partially into the substrate 12. The depth of trench 122 is determined by the thickness of semiconductor layer 14, which in turn is a function of BVdss. In an exemplary embodiment, Deep Reactive Ion Etching (DRIE) is performed with a fluorine or chlorine based chemistry to form the trenches 122. Several processes may be used for DRIE etching, including low temperature, high density plasma, or Bosch DRIE etching processes. In an exemplary embodiment, the grooves 122 have substantially vertical sidewalls. In another embodiment, the slot 122 has a tapered profile wherein the width of the slot is less than the width 74 at the lower surface of the slot. After forming the trenches 122, the masking layer 71 is removed by conventional etching. Although the slots 122 are shown as two slots in the figures, it should be noted that the slots 122 may be a single continuous slot or an array of interconnected slots (e.g., slots such as those shown in FIG. 10 and described below). The trenches 122 may also be a plurality of individual trenches having closed ends that are separated by portions of the body of semiconductor material 11.

Fig. 3 shows an enlarged partial cross-sectional view of device 10 at a next stage of manufacture. At this stage, as a first stage in forming filled trenches 122, various layers of semiconductor material are formed, grown, or deposited within trenches 122. In an exemplary embodiment, a semiconductor epitaxial growth technique is used to fill the trenches 122.

In a first step, a thin layer of thermal oxide is formed on the sidewalls of the trenches 122 to remove surface damage caused by the DRIE step. The thin layer of thermal oxide is then removed by conventional isotropic etching. Thereafter, the body of semiconductor material 11 is placed in an epitaxial growth reactor and precleaned as a first step in the epitaxial growth process. When silicon is the semiconductor material of choice for the fill layers (e.g., layers 23, 24, 26, and 27), such as SiHCl₃，SiH₂Cl₂，SiH₄Or Si₂H₆The silicon source gas is adapted to form these layers. In the embodiment shown, a blanket layer is grown (i.e., the layer is grown not only on the surfaces of trenches 122, but also over the entire major surface 18). In another embodiment, layers 23, 24, 26 and 27 are formed using selective epitaxial growth techniques such that these layers are not formed on dielectric layer 40.

An N-type layer 23 is first grown along the surface of trench 122 with arsenic as a suitable dopant source. In one exemplary embodiment, the n-type layer 23 has a thickness of about 2.0 x 10¹⁶To about 4.0X 10¹⁶Atom/cm³And a thickness of about 0.1 μm to about 0.3 μm.

Next, an intrinsic or buffer layer 24 is grown on the n-type layer 23, which layer is either undoped (except through the presence of trace impurities in the silicon source material and/or residual dopant gases remaining in the reaction chamber after the previous growth step) or very lightly p-type doped to a dopant concentration of less than about 2.0 x 10¹⁴Atom/cm³. Layer 24 has a thickness of about 0.5 μm to about 1.0 μm. A p-type layer 26 is then grown on layer 24, which is suitable for use with a boron dopant source. In one exemplary embodiment, the p-type layer 26 has a thickness of about 2.0 x 10¹⁶To about 4.0X 10¹⁶Atom/cm³And a thickness of about 0.1 μm to about 0.3 μm. An intrinsic or buffer layer 27 is then grown on the p-type layer 26, either undoped (except for trace impurities typically present in the silicon source material and/or residual dopant gases remaining in the reaction chamber after the previous growth step) or very lightly p-type doped to a dopant concentration of less than about 2.0 x 10¹⁴Atom/cm³. Layer 27 has a thickness of about 0.5 μm to about 1.0 μm. It will be appreciated that the thickness of layers 23, 24, 26 and 27 is adjusted to the width of slot 122. In an exemplary embodiment, the layers are of such a thickness that the resulting epitaxial layers fill trenches 122. When using the blanket epitaxial growth method, layers 27, 26, 24 and 23 are then planarized using chemical mechanical polishing techniques, etch-back techniques, combinations thereof, and the like. During planarization, epitaxial layers 27, 26, 24, 23 are planarized down to, or back to, major surface 18 to form filled trenches 122. In an exemplary embodiment, the planarization process also removes dielectric layer 40. An additional etching step may also be used to further remove any dielectric material remaining from layer 40. If selective epitaxial growth or selective etch-back techniques are maintained, dielectric layer 40 may remain, which will replace layer 41, as described below.

Fig. 4 shows an enlarged partial cross-sectional view of device 10 after further processing. First, a first dielectric layer 41 comprising, for example, a layer of silicon dioxide about 0.1 μm to about 0.2 μm thick is formed on major surface 18. Thermal oxidation growth at about 750 deg.c is suitable. In an optional step, a sputter etch step is used to smooth the upper or exposed surface of first dielectric layer 41. Second dielectric layer 42, which comprises, for example, about 0.1 μm silicon nitride, is then formed on first dielectric layer 41. Photolithography and etching steps are then employed to form an opening 47 through second dielectric layer 42 and first dielectric layer 41. Thereby exposing a portion of major surface 18 above filled trench 22 as shown in fig. 4. In an exemplary embodiment, the width 49 of the opening 47 is about 0.5 μm to about 1.0 μm.

A conductive layer 46 is then formed over second dielectric layer 42 and contacts or couples to filled trenches 22 through openings 47. In an exemplary embodiment, conductive layer 46 comprises about 0.1 μm polysilicon, which may be a doped deposition or an undoped deposition. If conductive layer 46 is initially deposited as an undoped deposition, conductive layer 46 is then doped using, for example, ion implantation techniques. In this exemplary embodiment, conductive layer 46 is doped with boron to provide a contact to p-type layer 26. One having an implantation energy of about 60keV, about 5.0X 10¹⁵To about 1.0X 10¹⁶Atom/cm²The boron ion implant dose of (a) is sufficient to dope conductive layer 26. In a subsequent heat treatment step, impurities diffuse from conductive layer 46 into filled trenches 22 to form p-type regions 52.

A third dielectric layer 48 is then formed on conductive layer 46 and a fourth dielectric layer 51 is formed on third dielectric layer 48. Third dielectric 48 comprises, for example, silicon nitride (e.g., about 0.05 μm thick), while dielectric layer 51 comprises a deposited oxide (e.g., about 0.7 μm thick). A conductive layer 53, comprising, for example, n-type polysilicon (e.g., about 0.3 μm thick), is then formed over the fourth dielectric layer 51. Over the conductive layer 53 is formed a protective layer 54 comprising, for example, about 0.15 μm silicon nitride.

Photolithography and etching steps are used to etch through portions of layers 54, 53, 51, 48, 46 and 42 to provide openings 70. This also forms a step stack structure 56 that encompasses the area of each portion of layers 42, 46, 48, 51, 53 and 54. In an exemplary embodiment, the width 73 of the opening 70 is between about 5.0 μm and about 8.0 μm.

Fig. 5 provides an enlarged partial cross-sectional view of device 10 after yet another processing step to form dielectric spacers 59. In an exemplary embodiment, a silicon nitride film is deposited over the step-stack structure 56 and the first dielectric layer 41. By way of example, a thin layer of silicon nitride about 0.1 μm thick is deposited by a chemical vapor deposition process. A conventional anisotropic etch-back step is then used to remove portions of the silicon nitride layer on the step stack structure 56 and on the first dielectric layer 41 while leaving portions of the silicon nitride layer on the sidewalls or vertical surfaces 68 of the step stack structure 56 to form the dielectric spacers 59.

A silicon oxide wet etch process is then used to remove the portion of dielectric layer 41 within opening 70. By way of example, dielectric layer 41 is etched with an ethylene hydrofluoric acid (e.g., 50: 1). In an exemplary embodiment, the etch time is extended (e.g., by 8 to 15 minutes) to undercut or remove material of dielectric layer 41 from the lower portion of dielectric spacer 59 to form recessed portion 74. Recessed dielectric layer 41 in this manner ensures that channel 45 (shown in figure 1) formed in body region 31 extends into layer 17 to allow channel current to flow more efficiently. In one exemplary embodiment, region 74 is recessed a distance of about 0.1 μm below dielectric spacer 59. A layer (approximately 0.08 μm thick) of thermal silicon oxide is then grown on the major surface within opening 70 to form gate dielectric layer 43.

Fig. 6 shows an enlarged partial cross-sectional view of device 10 after further processing. A conformal layer of semiconductor material is deposited over device 10 to a thickness of about 0.1 μm to about 0.15 μm. Boron impurities are then introduced into major surface 18 through opening 70 and the conformal semiconductor material layer to provide p-type impurities to body region 31. In one exemplary embodiment, the conformal semiconductor material layer comprises undoped polysilicon, and boron is implanted through the undoped polysilicon implant layer 17. One is about 1.0X 10¹³Atom/cm²And an implant energy of about 160keV is suitable for a 650 volt device. After the implantation step, the surface of the conformal layer of semiconductor material is cleaned by a cleaning or etching process.

A second conformal semiconductor material layer is then deposited over the first conformal layer and the two layers are etched to provide spacer gates 57. In one exemplary embodiment, the second conformal semiconductor material layer comprises about 0.8 μm of n-type polysilicon, which may be doped during deposition or later doped using ion implantation or other doping techniques. After the spacer gate 57 is formed, a 0.015 um layer of gate dielectric (e.g., silicon dioxide) is applied over the surface of the spacer gate 57 and the exposed area of the gate oxide 43.

In an exemplary embodiment, the etching step exposes the dielectric layer 54 and the upper portions of the dielectric spacers 59. Next, the upper portions of the dielectric spacer 59 and the dielectric layer 54 are etched to remove the protective layer 54, and the upper portion of the dielectric spacer 59 between the spacer gate 57 and the conductive layer 53 is broken and removed.

In a next step, a conductive material such as polysilicon is deposited to provide the connective conductive regions 77. Connective conductive regions 77 couple or electrically connect spacer gates 57 to conductive layer 53. An n-type doping step is then performed to dope the connecting conductive region 77 and provide dopants to the source region 33. In an exemplary embodiment, a dose is 3.0 × 10¹⁵Atom/cm²An arsenic implant with an implant energy of 80keV is used for this doping step.

Fig. 7 provides an enlarged partial cross-sectional view of device 10 after a subsequent fabrication step. A fifth dielectric layer 61 is deposited comprising, for example, about 0.05 μm silicon nitride. An ILD layer 62 is then deposited on the fifth dielectric layer 61. In one exemplary embodiment, ILD layer 62 comprises a deposited silicon dioxide layer having a thickness of about 0.8 μm. An optional ILD bevel etch is used for tapered region 62a of ILD layer 62. This facilitates step coverage of later formed layers.

Next, a conventional photolithography and etching step is used to form contact opening 81, which exposes a portion of major surface 18. Contact region 36 is then formed by a p-type ion implantation step through opening 81. By way of example, use is made of 3.0X 10¹⁴Atom/cm²And an implant energy of 80 keV. A conformal spacer layer is then deposited and etched to form spacers 82. In an exemplary embodiment, a 0.3 μm layer of silicon nitride is deposited and etched to form spacers 82. At this point a rapid annealing step is used to activate and diffuse the various speciesAnd (4) ion implantation. For example, device 10 is exposed to a temperature of about 1030 degrees Celsius for about 45 seconds.

An etching step is then used to remove a portion of major surface 18 to form recessed region 84. This allows source contact layer 63 to contact both source region 33 and contact region 36, thereby shorting the two regions together. The spacers 82 are then removed. In subsequent processing, a source contact layer 63 is deposited and patterned, followed by optional thinning of the substrate 12 and deposition of a drain contact layer 66 to provide the structure shown in FIG. 1. Although not shown in fig. 2-7, in this stage of fabrication, photolithography and etching steps are used, for example, in fig. 4-6, portions of conductive layer 46 are exposed to provide openings where source contact regions 63 are coupled to conductive layer 46, as shown in fig. 1. It will be appreciated that other conductive layers, such as a silicide layer, may be formed prior to deposition of the source contact layer 63.

Fig. 8 is a graph depicting breakdown voltage (BVdss) characteristics of device 10 in accordance with the present invention, and in accordance with the process parameters set forth herein. As shown in fig. 8, device 10 exhibits a nominal breakdown voltage from drain to source of about 750V, and further as shown in fig. 8, the device also exhibits low leakage below breakdown.

Fig. 9 is a graph depicting the on-resistance (Rdson) characteristics of device 10 in accordance with the present invention, and in accordance with the process parameters set forth herein. Device 10 exhibits superior Rdson characteristics over conventional superjunction devices having the same BVdss, with typical Rdson values of about 36 milliohm cm²。

Fig. 10 shows an enlarged partial cross-sectional view of a honeycomb structure 300 suitable for the device 10 according to the present invention. A honeycomb structure according to one embodiment of the present invention is shown having a filled trench 322 surrounding a plurality of polygonal regions of semiconductor layer 14 where active devices or cells are formed. It will be appreciated that the polygonal area may have rounded corners, and other shapes, including round, square, rectangular or otherwise, may be suitable. One feature of the honeycomb structure 300 is that it provides a high packing density, thereby improving Rdson and current carrying capability. In accordance with the present invention, filled trench 322 includes n-type layer 23, intrinsic layers 24 and 27, and p-type layer 26.

Fig. 11 is an enlarged cross-sectional view of another portion of device 10 showing an alternative edge termination structure 100 in accordance with the present invention. One feature of termination structure 100 is that it incorporates the basic components of device 10, thereby saving processing costs. Terminal structure 100 includes a conductive contact or layer 146, with conductive contact or layer 146 being formed on and adjacent to major surface 18. In an exemplary embodiment, the conductive contact layer 146 and the conductive layer 46 comprise the same material and are formed at the same time. For example, the conductive contact layer 146 includes p-type polysilicon. After a heat treatment, the p-type impurities will diffuse from conductive contact layer 146 to form p-type doped layer 152, which is the result of counter-doping n-type layer 17, which couples to optional p-type layer 19. Fig. 11 also shows that conductive contact layer 146 is coupled to source contact layer 63 through opening 91.

An isolation trench 103 is formed in the periphery of device 10, which includes, for example, an etched trench 106 filled with a dielectric material 108. Optionally, a thermal oxide layer 110 is formed to line the sidewalls and/or bottom surface of the isolation trench 103.

In another embodiment and as shown in fig. 11, the isolation trenches 113 further comprise a layer of semiconductor material, which is formed simultaneously with the filling trenches 22. By way of example, the semiconductor material layers include an n-type layer 23, an intrinsic or buffer layer 24, a p-type layer 26, and an intrinsic or buffer layer 27, as already described in connection with fig. 1, and if these semiconductor material layers are not included, then the trenches 106 are formed separately from the filled trenches 22 during fabrication.

In one exemplary embodiment, dielectric material 108 comprises silicon dioxide formed using SOG (spin-on glass) BPSG, PSG, and/or TEOS deposition techniques. After the oxide is formed, the upper surface of the dielectric region is planarized using an etch-in or chemical mechanical planarization technique, a combination thereof, or other techniques. In an exemplary embodiment, the grooves 106 have a width of about 30 μm to about 100 μm and are formed in a manner similar to that used to form the grooves 122 described in connection with FIG. 2. The sidewalls of the slot 106 may be substantially vertical or tapered such that the width at the bottom of the slot 106 is less than the width at the top of the slot 106. By way of example, dielectric material 108 and/or dielectric layer 110 extend to a depth or distance below semiconductor layer 14, as shown in fig. 11.

In an alternative embodiment where layers 23, 24, 26, 27 are included in isolation trenches 103, an n-type region 109 is inserted within substrate 12 below trench 106 to reduce any leakage current problems associated with die (die) separation.

In accordance with the present invention, when semiconductor layer 14 has p-type conductivity, the primary method for BVdss is pn junction 114 formed by semiconductor layer 14 and n-type substrate 12. This feature simplifies the edge termination structure 100 and saves space. For example, conventional devices require a distance of 1 to 3 times the thickness of the epitaxial layer for the termination structure. Whereas in the present invention the distance is reduced to about 1/2 times the thickness of the epitaxial layer.

In this embodiment, junction 114 is flatter than in conventional devices because the junction is depleted up from substrate 12, rather than down and across from body region 31. In addition, because conductive contact layer 146 is coupled to semiconductor layer 14 through doped regions 152 and 19, junction 114 extends laterally to the edge of device 10. In this manner, an optimized planar junction with optimized BVdss is achieved. Isolation trenches 103, among other things, serve to passivate junctions 114.

Fig. 12 provides an enlarged top view of an alternative isolation trench 203 in accordance with the present invention, with region 131 representing such a region of device 10 that is used for the termination structure described in connection with fig. 11, and region 132 representing such a region of device 10 that is used for the active structure as described in fig. 1. The isolation trenches 203 comprise an array of a plurality of pillars or shapes 117 that are formed when the isolation trenches are etched. In one exemplary embodiment, adjacent rows of shapes 117 are offset from each other as shown in FIG. 12 such that shapes 117 are substantially equidistant from each other. In an exemplary embodiment posts 117 are spaced from each other about 5 μm to about 15 μm.

By way of example, shape 117 is a pillar or region of various portions of semiconductor material 11. In one exemplary embodiment, shape 117 comprises substrate 12, semiconductor layer 14, p-type layer 19, n-type layer 17, and dielectric layer 41, and has a width or diameter of about 0.8 μm to about 1.0 μm. This is more clearly shown in fig. 13, which is an enlarged cross-sectional view of a portion of the isolation trench 203 of fig. 12 taken along reference line 13-13. Fig. 13 shows the isolation trench 203 prior to the formation of the dielectric material 208. Conventional photolithography and etching techniques are used to form trench 206 and shape 117. For example DRIE with fluorine or chlorine based chemicals.

After trenches 206 and shapes 117 are formed, dielectric layer 210 is formed, as shown in fig. 14. By way of example, dielectric layer 210 comprises a thermally grown silicon dioxide. A dielectric layer 208 is then deposited and planarized. In an exemplary embodiment, the dielectric layer 208 comprises a spin-on glass. In accordance with the present invention, shape 117 reduces dishing effects when dielectric layer 208 is deposited, it provides a flatter surface, better passivation, and a more reliable device. Shape 117 may be round, square, rectangular, polygonal, trapezoidal, elliptical, triangular, combinations thereof or the like, and may include rounded corners.

Fig. 15 provides an enlarged partial cross-sectional view of adjacent or multiple isolation trenches 203a and 203b, which are drawn as corresponding portions of two devices separated by a scribe grid or region 461. In this embodiment, adjacent devices 10 on a piece of semiconductor wafer include scribe grid 461, which comprises semiconductor material 11, rather than dielectric materials 208 and 210 being continuous between adjacent dies. This allows a die separation device, such as a dicing saw, to separate the die along the centerline 463, thereby enabling a secure die separation.

In summary, a new switching device with deep trench charge compensation has been described, including a method of manufacture. In addition, a ground plane structure has been described which is suitable for the device of the present invention, as well as for other semiconductor devices. In addition, edge termination structures suitable for the devices of the present invention, as well as other semiconductor devices, have been described.

While the invention has been described and illustrated with reference to specific embodiments thereof, the invention is not limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications as fall within the scope of the appended claims.

Claims (10)

1. A semiconductor device, characterized in that:

a body of semiconductor material; and

a charge compensation region comprising a trench formed in the body of semiconductor material;

wherein the charge compensation region is characterized by: a first epitaxial semiconductor layer formed in contact with the surface of the trench;

an intrinsic layer formed on the first epitaxial semiconductor layer; and

a second epitaxial semiconductor layer formed on the intrinsic layer, wherein the first epitaxial semiconductor layer and the second epitaxial semiconductor layer have opposite conductivity types, and the intrinsic layer is between the first and second epitaxial semiconductor layers to reduce intermixing of opposite conductivity type dopants.

2. The device of claim 1, further characterized by a conductive layer in contact with said charge compensation region.

3. The device of claim 1, wherein the body of semiconductor material is characterized by:

a semiconductor substrate having a first conductivity type; and

an epitaxial layer is formed over the semiconductor substrate, the epitaxial layer having an upper surface.

4. The device of claim 3 wherein the epitaxial layer is characterized as having a second conductivity type opposite the first conductivity type.

5. A semiconductor device, characterized in that:

a body of semiconductor material having first and second opposed major surfaces;

a first doped region formed in the body of semiconductor material adjacent the first major surface and characterized by a first conductivity type;

a second doped region formed in the first doped region and characterized by a second conductivity type;

a charge compensating trench region formed in the body of semiconductor material adjacent to the first doped region, wherein the charge compensating trench region is characterized by:

a slot;

a first epitaxial semiconductor layer of a second conductivity type formed in connection with a surface of the trench;

an intrinsic layer formed on the first epitaxial semiconductor layer; and

a second epitaxial semiconductor layer of the first conductivity type formed on the intrinsic layer, wherein the intrinsic layer is between the first and second epitaxial semiconductor layers to reduce intermixing of opposite conductivity dopants; and

a control electrode formed adjacent to the first and second doped regions.

6. The device of claim 5, further characterized by a conductive layer contacting said charge compensation trench region.

7. The device of claim 5, further characterized by another intrinsic layer formed on said second epitaxial semiconductor layer.

8. A method of forming a semiconductor device, characterized by the steps of:

providing a body of semiconductor material having first and second opposed major surfaces;

forming a trench in a body of semiconductor material;

forming a first epitaxial semiconductor layer of the first conductivity type in contact with the surface of the trench;

forming an intrinsic layer on the first epitaxial semiconductor layer;

forming a second epitaxial semiconductor layer of a second conductivity type adjacent to said first epitaxial semiconductor layer to form a charge compensation trench region, wherein said intrinsic layer is between said first and second epitaxial semiconductor layers to reduce intermixing of opposite conductivity dopants;

forming a first doped region in the body of semiconductor material adjacent the charge compensation trench region, wherein the first doped region has a second conductivity type;

forming a second doped region in the first doped region, the second doped region having the first conductivity type; and

a control electrode is formed adjacent to the first and second doped regions.

9. The method of claim 8, further characterized by the step of forming a conductive layer in contact with the charge compensation trench region.

10. The method of claim 8 further characterized by the step of forming another intrinsic layer on said second epitaxial semiconductor layer.