HK1114946B - Semiconductor device having sub-surface trench charge compensation regions and method - Google Patents

Description

Semiconductor device having bottom surface trench charge compensation region and method

Technical Field

The present invention relates generally to semiconductor devices, and more particularly to power switching devices and methods of making the same.

Background

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are one common type of power switching device. The MOSFET device includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure disposed adjacent to the channel region. The gate structure includes a conductive gate electrode layer disposed adjacent to the channel region and separated therefrom by a thin dielectric layer.

When the MOSFET device is in an on state, a voltage is applied to the gate structure, forming a conductive channel region between the source and drain regions, which causes current to flow through the device. In the off state, any voltage applied to the gate structure is very low, so that no conductive channel is formed and no current flow occurs. During the off state, the device must support a high voltage between the source and drain regions.

The current market for high voltage power switches is driven by two main parameters: breakdown voltage (BVdss) and on-resistance (Rdson). For a particular application, a minimum breakdown voltage is required, and in practice, designers can often meet BVdss specifications. However, this often results in loss of Rdson. This trade-off in performance (trade off) is a major design challenge for users and manufacturers of high voltage power switching devices.

Super junction devices have recently gained promise in improving the trade-off between Rdson and BVdss. In conventional n-channel superjunction devices, a plurality of highly doped diffused n-type and p-type regions replace a lightly doped n-type epitaxial region. In the on state, current flows through the highly doped n-type region, which lowers Rdson. In the off or blocking state, the highly doped n-type and p-type regions deplete or compensate each other to provide a high BVdss. Although superjunction devices appear promising, significant challenges remain in their manufacture.

Another problem with current high voltage power switch products is that they typically require one greater input (e.g., gate or control electrode) charge for switching from one state to another. Such a requirement places an additional burden on the peripheral control circuitry, among other things.

Therefore, there is a need for a high voltage power switch device structure and method of fabrication that provides low Rdson, high BVdss, and reduced input charge.

Drawings

FIG. 1 illustrates an enlarged partial cross-sectional view of a semiconductor device in accordance with the present invention; 2-11 illustrate enlarged partial cross-sectional views of the semiconductor device of FIG. 1 at various stages of fabrication; FIG. 12 illustrates a highly enlarged partial cross-sectional view of a portion of a semiconductor device in accordance with another embodiment of the present invention; and FIG. 13 illustrates a highly enlarged partial cross-sectional view of a portion of a semiconductor device in accordance with yet another embodiment of the present invention.

For clarity and simplicity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein, current carrying electrode refers to a cell of a device that carries current through the device, e.g., a source or drain of an MOS transistor, or an emitter or collector of a bipolar transistor, or a cathode or anode of a diode, and a control electrode refers to a cell of a device that controls current through the device, e.g., a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, one of ordinary skill in the art will appreciate that complementary devices are possible in accordance with the present invention. For clarity of the drawing, the doped regions of the device structure are depicted as corners, typically having straight line edges and precise angles. However, those skilled in the art understand that the edges of the doped regions are not generally straight nor are the corners precisely angled because of the diffusion and movement of impurities.

Furthermore, the devices of the present invention may implement a single body design (where the body region is a plurality of single body regions) or a single body design (where the body region is composed of a single region in an elongated pattern, typically in a serpentine pattern). However, for ease of understanding throughout, the device of the present invention is described as a monolithic design. It should be understood that the present invention encompasses both monolithic designs and single body designs.

Detailed Description

Fig. 1 shows a partial cross-sectional view of an Insulated Gate Field Effect Transistor (IGFET), MOSFET, superjunction device, or switching device or cell 10 according to one embodiment of the invention. By way of example, in many such devices, device 10 is integrated with logic and/or other components in a semiconductor chip as part of a power integrated circuit. Alternatively, in many such devices, the device 10 is integrated together to form a discrete transistor device.

Device 10 includes a region of semiconductor material 11 comprising, for example, an n-type silicon substrate 12 having a resistivity in the range of about 0.001 to about 0.005 ohm/cm, andarsenic may be doped. In the illustrated embodiment, the substrate 12 provides a drain region for the device 10, which is connected to the conductive layer 13. Semiconductor layer 14 is formed in or on substrate 12 and, in accordance with the present invention, is either n-type or p-type and is lightly doped sufficiently so as not to affect the charge balance in the above-described trench compensation region. In one embodiment, layer 14 is formed using conventional epitaxial growth techniques. In an embodiment suitable for a 600 volt device, layer 14 is doped at a concentration of about 1.0 x 10¹³Atoms per cubic centimeter to about 1.0 x 10¹⁴The atoms/cubic centimeter doping is either n-type or p-type and has a thickness on the order of about 40 microns to about 60 microns. The thickness of layer 14 is increased or decreased depending on the desired BVdss rate of device 10. In an alternative embodiment, semiconductor layer 14 comprises a layered doping profile because semiconductor layer 14 has a higher doping concentration close to substrate 12 and the doping concentration transitions gradually or abruptly to a lower concentration for the balance of its thickness. Other materials may also be used for the body or portions thereof of the semiconductor material 11 including silicon-germanium, silicon-germanium-carbon, carbon-doped silicon, III-V materials, or the like.

In accordance with the present invention, device 10 also includes a filled trench structure or structure 510 formed in the region of semiconductor material 11. Filled trench structure 510 includes a superjunction portion, a lower surface charge compensation portion, or compensation portion 22, and a control portion, or gate control portion 511, overlying compensation portion 22. The compensation portion 22 includes spaced apart under-surface-filled trenches, semiconductor material-filled trenches, epitaxial filled regions or trenches, charge compensation trench regions, deep trench charge compensation regions, charge compensation filled trenches, charge compensation portions or charge compensation regions 22. Portion 22 comprises multiple layers or layers of semiconductor material (which includes layers of opposite conductivity types) preferably separated by an intrinsic or buffer semiconductor layer or layers. The intrinsic layer serves, among other things, to prevent or reduce intermixing of the opposite conductivity type layers (e.g., the two charge layers), which is believed to negatively impact the conduction efficiency of the device 10 in the on-state. As used herein, charge compensation generally refers to substantially balancing or equalizing the overall charge of the opposite conductivity type layers.

In one embodiment, compensation portion 22 comprises a plurality of layers or stacks (stackedlayer) of semiconductor material formed using single crystal (i.e., non-polycrystalline) epitaxial growth techniques, and these layers terminate or end a distance 181 below major surface 18. For example, the compensation portion 22 includes a p-type layer 23 formed on, or adjacent to a surface or trench wall adjacent to the body of semiconductor material 11. An intrinsic semiconductor or buffer layer 24 is formed on, over, or adjacent to the surface of the p-type layer 23, an n-type layer 26 is formed on, over, or adjacent to the surface of the intrinsic semiconductor layer 24, and an intrinsic semiconductor or buffer layer 27 is formed on, over, or adjacent to the surface of the n-type layer 26. Intrinsic layer 24 serves, among other things, to prevent or reduce intermixing of dopants from layers 23 and 26, which, as previously mentioned, improves the conduction efficiency of device 10. The intrinsic layer 27 serves, among other things, to fill or partially fill the trenches. For an n-channel device and in accordance with the present invention, when device 10 is in the on-state, n-type layer 26 provides the primary vertical low-resistance current path from the channel to the drain. When device 10 is in the off state, p-type layer 23 and n-type layer 26 compensate each other in accordance with the present invention to provide increased BVdss characteristics. It will be appreciated that additional n-type and p-type layers may be used and are preferably separated by additional intrinsic or buffer layers. In an alternative embodiment as shown in fig. 1, a dielectric layer 28 (e.g., layers 26 and 27) is formed overlying the outermost portion. In one embodiment, dielectric layer 28 fills all remaining space in compensation portion 22. In another embodiment, dielectric layer 28 only partially fills all remaining space remaining in portion 22, such as an air gap (air gap). By way of example, dielectric layer 28 comprises an oxide or nitride or a combination thereof. In another embodiment, dielectric layer 28 comprises a thin thermal oxide capped with a thin layer of polysilicon, followed by a deposited TEOS layer. It should be appreciated that in some applications, the thin oxide capped with polysilicon reduces the tangential stress from the deposited oxide, thereby improving device performance. It should also be understood that during the thermal treatment, the n-type and p-type doping from layers 26 and 23 diffuse into the buffer layers, which may or may not be present in the final device. However, when deposited or formed, buffer layers 24 and/or 27 have a lower doping concentration than layers 23 and 26.

By way of example, each of the p-type layer 23 and the n-type layer 26 has a thickness of about 9.0 × 10¹⁶To about 3.0X 10¹⁶Doping concentrations on the order of atoms per cubic centimeter, and each having a thickness of about 0.1 to about 0.2 microns, respectively. In one embodiment, the intrinsic semiconductor or buffer layers 24 and 27 are undoped or have a thickness of less than about 1.0 x 10¹⁴Very lightly doped p-type with atomic/cubic centimeter doping concentration and each having a thickness of about 0.5 microns to about 1.0 micron. If no dielectric layer 28 is employed, the thickness of layer 27 is adjusted, such as to satisfy trench balance between deposited layers.

According to the present invention, the doping from p-type layer 23 is diffused into semiconductor layer 14 to form a p-type region, or region 231 (shown in dashed lines) under body region 31 described below is doped or diffused laterally. The p-type regions 231 laterally diffused from the adjoining compensation portions 22 may be completely merged together, or may not be completely merged as shown in fig. 1, so that a portion of the semiconductor 14 is still present in the completed device. In other words, the actual diffusion distance between adjacent lateral diffusion regions 231 may vary.

In accordance with the present invention, in one embodiment, diffusion region 231 comprises a conductivity type opposite to the conductivity type of semiconductor layer 14. This embodiment provides a unique structure in which both the active device structure and the edge termination structure (not shown) are formed in the same layer (e.g., layer 14), but because of the lateral diffusion regions 231, the active device (e.g., device 10) is in the p-type layer and the edge termination structure is formed in the n-type layer 14 laterally separated from the compensation portions 22.

Although not shown, it should be understood that during the formation of device 10, the n-type doping from highly doped substrate 12 diffuses into lower portions of compensation region 22 such that those portions of compensation region 22 in substrate 12 become more highly doped n-type.

Trench gate structure or control portion 511 includes a control electrode or gate or conductive layer or region 57 separated on the vertical sidewalls of the trench region by a gate dielectric layer, region or material 43. In one embodiment, gate dielectric layer 43 comprises silicon dioxide and has a thickness of approximately 0.005 microns to 0.1 microns. In alternative embodiments, gate dielectric layer 43 comprises silicon nitride, tantalum pentoxide, titanium dioxide, barium strontium titanate, or compounds thereof including silicon, oxygen, or the like. Conductive gate regions 57 comprise, for example, n-type polysilicon and are about 0.3 microns to about 0.5 microns thick.

An optional thick dielectric layer 431 separates or isolates or insulates gate conductive region 57 from subsurface trench compensation region 22, according to one embodiment of the present invention. In this embodiment, dielectric layer 431 is thicker than dielectric layer 43. By way of example, dielectric layer 431 comprises about 0.1 microns to about 0.2 microns of thermal oxide. In an alternative embodiment, gate dielectric layer 43 is used to isolate gate conductive region 57 from lower surface trench compensation region 22.

A body or doped region 31 is formed in semiconductor layer 14 between trench gate structures 510 and adjacent to or near or adjacent to trench gate structures 510 and extends from a major surface 18 of the body of semiconductor material 11. In one embodiment, body region 31 comprises p-type conductivity and has a doping concentration suitable for forming an inversion layer that operates like conduction channel 45 of device 10 when gate structure 510 is properly biased as described below. Body region 31 extends from major surface 18 to a depth of about 1.0 to about 5.0 microns. An n-type source region 33 is formed in body region 31 proximate or adjacent, trench gate structure 510. In one embodiment, source region 33 extends from main surface 18 to a depth of about 0.2 to about 0.5 microns. One or more p-type body contact regions 36 are formed in body region 31 partially in source region 33 and/or below source region 33. The body contact regions 36 are arranged to provide a lower contact resistance to the body regions 31 and to reduce the sheet (sheet) resistance of the body regions 31 under the source regions 33, which suppresses parasitic bipolar effects.

In accordance with the present invention, device 10 also includes an n-type channel connect, or drain extension, region 32 that is configured to electrically connect channel region 45 to subsurface trench compensation region 22. In one embodiment and as shown in fig. 1, channel connect region 32 is formed under body region 31 and abuts body region 31. Channel connect region 32 also abuts the upper surfaces or portions of layers 23 and 26 to provide a conductive path between source region 33 and layer 26 when device 10 is in operation.

Interlayer dielectric region 48 is formed overlying major surface 18 and includes, for example, a first dielectric layer 51 formed overlying conductive gate region 57 and a second dielectric layer 61 formed overlying first dielectric layer 51. By way of example, dielectric layer 51 comprises silicon dioxide and has a thickness of about 0.02 microns to about 0.05 microns. Dielectric layer 61 comprises, for example, a deposited oxide and has a thickness of about 0.4 microns to about 1.0 microns.

An opening is formed in interlayer dielectric layer region 48 to provide contact to device 10 to source contact layer 63. As shown, a portion of major surface 18 is etched such that source contact layer 63 makes contact to both source region 33 and body region 36. In one embodiment, source contact layer 63 comprises a titanium/titanium nitride barrier layer and a silicon aluminum alloy or the like formed overlying the barrier layer. A drain contact layer 13 is formed on the opposite surface of the region of semiconductor material 11 and comprises, for example, a solderable metal structure such as a titanium-nickel-silver alloy, a chromium-nickel-gold alloy or the like.

The operation of device 10 proceeds as follows, assuming source terminal 63 is at a voltage V of 0 volts_SDown operation, gate region 57 receives a control voltage V_G5.0 volts, which is greater than the conduction threshold of device 10, and drain terminal 13 is at drain voltage V_DOperating at 5.0 volts. V_GAnd V_SCauses body region 31 to invert under gate region 57 to form channel 45, which electrically connects source region 33 to channel connection region 32. Device currentI_DFlows from the drain terminal 13 and reaches the source terminal 63 via the n-type layer 26, the channel connection region 32, the channel 45, the source region 33. Thus, current I_DFlows vertically through the n-type layer 26 to create low resistance. In one embodiment, I_D1.0 ampere. To switch the device 10 to the off state, a control voltage V less than the conduction threshold of the device is applied_GApplied to gate region 57 (e.g., V)_G< 5.0 volts). This removes the trench 45, I_DNo longer through device 10. In the off state, the depletion region from the main barrier junction spreads and the n-type layer 26 and p-type layer 23 compensate each other, thus enhancing BVdss.

Turning now to fig. 2-9, a process for forming device 10 in accordance with the present invention is described. Fig. 2 shows an enlarged partial cross-sectional view of device 10 at an early stage of fabrication. In connection with fig. 1 described above, an example of material properties of the body of semiconductor material 11 is provided. In an initial step, a first dielectric layer 40 is formed on major surface 18 and comprises silicon dioxide, such as about 0.05 microns to about 0.1 microns thick. Standard photolithography steps are then used to provide openings for p-type body region 31 and edge termination structures (not shown). p-type body region 31 is selectively formed in semiconductor layer 14 through dielectric layer 40. In an embodiment suitable for a 600 volt device, boron is applied at about 1.0 x 10¹³The atoms per cubic centimeter are implanted and form region 31 at an implant energy of about 160 kilo-electron volts. Next, a second dielectric layer 44 comprising, for example, a different material than the first dielectric layer 40 is formed overlying the first dielectric layer 40. By way of example, when first dielectric layer 40 comprises silicon dioxide, second dielectric layer 44 comprises silicon nitride. In one embodiment, second dielectric layer 44 comprises approximately 0.2 microns of silicon nitride and is formed using conventional deposition techniques. The implanted p-type doping is then heated to diffuse the doping to the desired depth to form region 31. By way of example, body region 31 has a depth of about 3.0 to about 5.0 microns.

Fig. 3 shows an enlarged partial cross-sectional view of device 10 at a subsequent stage of fabrication. A hard mask layer 71 is formed on major surface 18 and patterned to form an opening 72 through first dielectric layer 40, hard mask layer 71, and second dielectric layer 44 that serve to expose a portion of major surface 18. By way of example, the hard mask layer 71 comprises approximately 1.0 micron of deposited oxide. By way of example, the openings 72 have a width 74 on the order of about 3.0 microns to about 5.0 microns. Next, a trench 122 is formed through semiconductor layer 14. In one embodiment, the trench 122 extends at least partially into the substrate 12. The depth of trench 122 is determined by the thickness of semiconductor layer 14, which is a function of BVdss. In one embodiment, a Deep etch Deep wafer (DRIE) that etches with a fluorine or chlorine based chemistry is used to form the trenches 122. Several techniques may be utilized for DRIE etching, including: low temperature high density plasma, or Bosch DIRE process. In one embodiment, the trenches 122 have substantially vertical sidewalls. In an alternative embodiment, the trench 122 has a tapered shape, wherein the trench width at the lower surface of the trench is less than the width 74. Although the trenches 122 are described as being plural, it should be understood that the trenches 122 may be a single continuous trench or a connected array of trenches. Alternatively, trenches 122 may be a plurality of individual trenches having closed ends and separated from portions of the body of semiconductor material 11.

Fig. 4 shows an enlarged partial cross-sectional view of device 10 at a further stage of processing. At this point, a layer of semiconductor material is formed, grown, or deposited in the trenches 122 as in the first stage of forming the filled trenches or lower surface charge compensation regions 22. In one embodiment, a single crystal semiconductor epitaxial growth technique is used to fill trench 122. In other words, a single crystal semiconductor layer is grown in the trench 122.

In a first step, a thin thermal oxide (not shown) is formed on the sidewalls of the trench 122 to remove any surface damage caused by the DRIE step. The thin thermal oxide is then removed using conventional isotropic etch techniques (e.g., 10: 1 wet oxide strip). Next, the body of semiconductor material 11 is placed into an epitaxial growth reactor (epitaxial growth reactor) and pre-cleaned as in the first step of the epitaxial growth process. When silicon is used forFilling selected semiconductor materials of the layers (e.g., layers 23, 24, 26, and 27), such as SiHCl₃、SiH₂Cl₂、SiH₄Or Si₂H₆Is suitable for forming those layers. In the illustrated embodiment, a capping layer is grown (i.e., a layer is grown on major surface 18 in addition to trenches 122). In an alternative embodiment, a selective epitaxial growth technique is used to form layers 23, 24, 26, and 27 such that those layers are not formed overlying major surface 18, but are formed only in trenches 122.

A P-type layer 23 is first grown along the surface of the trenches 122 with boron as a suitable dopant source. By way of example, the p-type layer 23 has a thickness of about 3.0 × 10¹⁶To about 9.0X 10¹⁶A doping concentration on the order of atoms per cubic centimeter and a thickness of about 0.1 to about 0.3 microns. As shown in fig. 4, in an optional embodiment, an intrinsic layer 233 is formed overlying p-type layer 23 and has a thickness of about 0.1 to about 0.2 microns. Next, a capping layer 234 is formed on layer 233 and includes, for example, about 0.05 microns of thermal oxide and about 0.1 microns of nitride. Next, device 10 is first heated to laterally diffuse the p-type doping from layer 23 into semiconductor layer 14 to laterally form diffused p-type region 231. Layer 234 is provided to cover p-type layer 23 during the heating step to prevent out-diffusion of dopants from layer 23. Also during the heating step, n-type doping from substrate 12 diffuses into portion 1200 of layer 23, turning portion 1200 n-type. Further, the p-type doping in layer 23 diffuses into intrinsic layer 233, transforming intrinsic layer 233 into p-type layer 23, which is shown as continuous layer 23 in fig. 5-12. After the heat treatment step, the capping layer 234 is removed.

Turning now to fig. 5, an intrinsic or buffer layer 24 is grown overlying the p-type layer 23 and is undoped or at less than about 2.0 x 10¹⁴Doping concentration of atoms per cubic centimeter is lightly doped p-type. Layer 24 has a thickness of about 0.5 microns to about 1.5 microns. Next, an n-type layer 26 is grown overlying layer 24, with phosphorus, arsenic, and antimony dopant sources being suitable. In one embodiment, an n-type layer26 has a thickness of about 3.0X 10¹⁶To about 9.0X 10¹⁶A doping concentration on the order of atoms per cubic centimeter and a thickness of about 0.1 to about 0.3 microns. Next, an intrinsic or buffer layer 27 is grown overlying the n-type layer 26 and is undoped (excluding trace impurities (trace impurities) that typically occur in the residual dopant gas and/or silicon source material of the reactor after the preceding growth steps) or at less than about 2.0 x 10¹⁴Doping concentration of atoms per cubic centimeter is lightly doped n-type. Layer 27 has a thickness of about 0.1 microns to about 0.3 microns. Next, a thin wet oxide is grown on layer 27 of the structure followed by dielectric layer 28, which comprises, for example, a deposited oxide having a thickness suitable to fill trench 122. In one embodiment, dielectric layer 28 is formed in multiple steps, with an etch back or planarization step between deposition steps ensuring that trenches 122 are filled to a desired level. It should be understood that the thickness of layers 23, 24, 26, 27, and 28 may be adjusted according to the width of trench 122.

Fig. 6 shows an enlarged partial cross-sectional view of device 10 in a still further stage of fabrication after planarization of layers 28, 27, 26, 24, 23 and recessing of major surface 18 to form underfilling trench compensation region 18 or compensation portion 22. In one embodiment, layers 28, 27, 25, 24, and 23 are recessed by a distance 181 that is greater than the depth of body region 131. As an example, etchback is used to planarize and recess these layers. As an example, a dry etch technique with a fluorine and chlorine based chemistry may be employed to etch the layer. In one embodiment, a polysilicon layer and a photoresist layer are first formed overlying dielectric layer 28, and then these layers are etched back or planarized using second dielectric layer 44 as a stop layer to protect portions of major surface 18. In one embodiment, as shown in fig. 6, portions of sidewalls 228 are etched to laterally recess under portion 229 of dielectric layer 40 such that the upper portion of trench 122 is wider than the lower portion comprising layers 23, 24, 26, 27, and 28, which provide, among other things, an enhanced arrangement of channel connect regions 32 described below.

FIG. 7 showsAn enlarged partial cross-sectional view of device 10 after additional processing is shown. Dielectric layer 113 is formed on the exposed surfaces of trenches 122 including the upper surfaces of layers 23, 24, 26, and 27. By way of example, the dielectric layer comprises approximately 0.1 micron of thermal oxide. Next, channel connection region 32 is formed adjacent to layers 23 and 26 and body region 31. As an example, the channel connection region 32 is formed using ion implantation with n-type doping such as phosphorus. About 1.0X 10¹³Atoms per cubic centimeter to about 1.0 x 10¹⁴An implant dose of atoms per cubic centimeter and an implant energy of about 120 kilo-electron volts to about 150 kilo-electron volts is suitable for one embodiment of the invention. In one embodiment, the lateral penetration of the doping under the body region 31 is provided using a corner implant. After the implantation step, the dielectric layer 113 is removed using conventional techniques.

Fig. 8 shows an enlarged partial cross-sectional view of device 10 after further processing. A gate dielectric layer 43 is formed overlying the exposed surfaces of connection region 32 and trench 122. In one embodiment, gate dielectric layer 43 comprises silicon dioxide and has a thickness of approximately 0.05 microns to 0.1 microns. The following description, along with fig. 8, illustrates one approach when an optional thick dielectric layer 431 is employed. After forming gate dielectric layer 43, a polysilicon layer is formed overlying gate dielectric layer 43 to a thickness of approximately 0.05 microns. The polysilicon layer is then etched to form a dielectric layer 44 that is recessed along the polyethylene spacers 333 in the upper sidewalls of the trenches 122 and optionally downward. Next, a dielectric layer is formed overlying gate dielectric layer 43 and spacers 333. By way of example, the dielectric layer comprises approximately 0.05 microns of silicon nitride, which is then etched to form nitride spacers 334 abutting polyethylene 333 and dielectric layers 40 and 44. Next, a dielectric layer 431 (shown in fig. 9) is grown on channel connect region 32 between spacers 334. By way of example, dielectric layer 431 comprises about 0.1 to about 0.2 microns of thermal oxide. Next, the nitride spacers 334 and the polyethylene spacers 333 are removed.

Fig. 9 shows an enlarged cross-sectional view of device 10 after further processing. A conductive layer, such as a doped polysilicon layer, is deposited overlying gate dielectric layer 43 and patterned to form gate conductive region 57 in trench 122 overlying lower surface trench compensation region 22. For example, gate conductive region 57 comprises about 0.3 microns to about 0.5 microns of phosphorus doped polysilicon. In one embodiment, gate conductive region 57 is annealed prior to etching. Gate conductive region 57 and gate dielectric region 43 form a control portion 511 that fills trench structure 510. In one embodiment, dielectric layer 40 is removed at this point using conventional techniques.

Fig. 10 shows an enlarged partial cross-sectional view of device 10 at another stage of fabrication. A dielectric layer 51 is deposited overlying major surface 18. By way of example, layer 51 comprises a thin oxide layer having a thickness on the order of about 0.02 to 0.07 microns. Next, the source region 33 is provided with an opening using a conventional photolithography step. As an example, 3.0X 10 with an injection energy of 80 keV was used¹⁵The phosphorus implant dose of atoms per cubic centimeter forms source region 33. Next, a mask material such as photoresist for forming the source region 33 is removed.

Fig. 11 shows an enlarged partial cross-sectional view of device 10 after additional processing. A passivation or dielectric layer 61 is formed overlying major surface 18. By way of example, layer 61 comprises a deposited oxide and has a thickness of about 0.5 microns to about 1.0 microns. A contact lithography step is used to form opening 91 to expose a portion of major surface 18 above source region 33. An optional isotropic etch is used to widen the opening 91 near the outer surface of layer 61 as shown in fig. 11. Major surface 18 is then exposed to an etchant that removes material from semiconductor layer 14 to form recessed regions 99. Next, the body contact region 36 is formed through the opening 91 and the recessed region 99. In one embodiment, a series of implants or series of implants are used such that the body contact region 36 includes a plurality of regions as shown in FIG. 12. In one embodiment, three boron implants are used to increase the implant energy to set the taper as shown in fig. 12. In other words, a high ion implantation energy provides a deeper, wider region, while a low ion implantation energy provides a shallower, narrower region. By way of example, a dosage of about 1.0X 10 is used¹⁴Atoms per cubic centimeter to about 1.0 x 10¹⁵A first boron implant of atoms/cubic centimeter and energy of about 200 kilo-electron volts, followed by a dose of about 1.0 x 10¹⁴Atoms per cubic centimeter to about 1.0 x 10¹⁵A second boron implant of atoms/cubic centimeter and 100 kilo electron volts, then applied at a dose of about 1.0 x 10¹⁴Atoms per cubic centimeter to about 1.0 x 10¹⁵A third boron implant of atoms per cubic centimeter and at an energy of 25-30 kev, thereby forming region 36. In an alternative approach, body contact regions 36 are formed prior to formation of dielectric layer 61 using conventional masking techniques. A dielectric layer 61 is subsequently formed and patterned.

After body contact regions 36 are formed, a source contact or conductive layer 63 is formed overlying major surface 18. As an example, a barrier structure is formed, such as titanium/titanium nitride followed by a layer comprising aluminum or an aluminum alloy. The conductive layer is then patterned using conventional photolithography and etching techniques to form the source contact layer 63 as shown in fig. 1. In one embodiment, a final passivation layer is used overlying source contact layer 63, the final passivation layer further comprising a deposited oxide, a deposited nitride, or a compound thereof. Next, the device 10 is thinned, and a drain contact layer 13 is formed in contact with the substrate 12 as shown and further described in connection with fig. 1.

Fig. 12 illustrates a highly enlarged partial cross-sectional view of a semiconductor device 100 having a underfill compensation trench region 222 in accordance with another embodiment of the present invention. Device 100 is similar to device 10 except that the body of semiconductor material 11 includes an n-type substrate 12 and an n-type buffer layer 114, the n-type buffer layer 114 having a lower doping concentration than substrate 12 (e.g., about 20-34 ohms/cm) and a thickness of about 10 microns to about 20 microns. Also, in device 100, the under-surface-filled trench compensation region or portion 222 does not extend through the entire channel of buffer layer 114. In this embodiment, after etching the trenches 122, n-type doping is introduced through the lower surfaces of the trenches 122 to form n + regions 223 adjacent the lower surfaces of the trenches 122, which serve as counter-dopant-dope p-type layers 23 to electrically connect the filled trenches 222 to the buffer epitaxial layer 114. This embodiment is suitable for manufacturing various breakdown voltage devices using the same filled trench process. This embodiment is suitable for manufacturing devices of various breakdown voltages using the same filled trench technique. Various breakdown voltages are then obtained with different substrate doping concentrations and thicknesses, wherein the depth and thickness of the connection region 223 can be adjusted accordingly. Additionally, device 100 is shown without a thick dielectric layer or region 431. In this embodiment, gate dielectric layer 43 separates gate conductive layer 57 from channel connection region 32. It should be understood that thick dielectric layer 431 is preferably used with device 100.

Fig. 13 illustrates a highly enlarged partial cross-sectional view of a portion of a semiconductor device 110 having a filled compensation trench region in accordance with yet another embodiment of the present invention. Device 110 is similar to device 10 except that after p-type layer 23 is deposited, portions of p-type layer 23 along bottom portions 146 of trenches 122 are removed to provide an enhanced conductive path between substrate 12 and n-type layer 26.

In summary, a new switch structure has a filled trench structure that includes a bottom surface charge compensation region and a control region overlying the compensation region. In one embodiment, the channel connect region is used to electrically connect a source region or current carrying electrode of the device to the lower surface charge compensation region when the device is in operation.

While the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications as fall within the scope of the appended claims.

Claims (9)

1. A semiconductor device, comprising:

a region of semiconductor material having a first major surface;

a body region formed in the region of semiconductor material;

a source region formed in the body region;

a trench gate structure comprising a gate conductive layer separated from sidewalls of the trench gate structure by a gate dielectric layer, wherein the body region and source region are adjacent the trench gate structure, and wherein the trench gate structure is arranged to control a channel in the body region when the semiconductor device is in operation;

a lower surface trench compensation region formed in the region of semiconductor material and recessed below the first major surface, wherein the lower surface trench compensation region abuts a bottom surface of the trench gate structure, and wherein the lower surface trench compensation region includes a plurality of opposite conductivity type semiconductor layers, and wherein the lower surface trench compensation region connects the region of semiconductor material without an intervening dielectric layer; and

a channel connection region formed in the semiconductor material region interposed between the body region and the lower surface trench compensation region and arranged to electrically connect the channel to at least one of the plurality of opposite conductivity type semiconductor layers, wherein the channel connection region and the source region comprise a first conductivity type, and wherein the channel connection region connects the body region and the plurality of opposite conductivity type semiconductor layers.

2. The device of claim 1, wherein the lower surface trench compensation region is filled with a plurality of single crystal epitaxial layers, including:

a first layer of a first conductivity type formed overlying sidewalls and a bottom surface of the trench; and

a second layer of a second and conductivity type formed overlying the first layer.

3. The device of claim 2, further comprising a dielectric region overlying the second layer.

4. The device of claim 3, wherein the dielectric region comprises a thermal oxide layer overlying the second layer, a polysilicon layer overlying the thermal oxide layer, and a deposited oxide overlying the polysilicon layer.

5. A method of forming a semiconductor device, comprising:

providing a region of semiconductor material having a first major surface;

forming a trench in the region of semiconductor material extending from the first major surface;

forming a plurality of semiconductor layers in the trench, the semiconductor layers including at least two opposite conductivity type semiconductor layers and at least one buffer layer separating the at least two opposite conductivity type semiconductor layers to form a filled trench compensation region, wherein the buffer layer has a lower doping concentration than the at least two opposite conductivity type semiconductor layers in composition;

removing portions of the plurality of semiconductor layers such that remaining portions of the plurality of semiconductor layers are recessed below the first major surface to form a underfill trench compensation region on the bottom portion of the trench;

covering the compensation region of the lower surface filling groove, and forming a control electrode in the upper part of the groove;

forming a body region in said region of semiconductor material, wherein said control electrode is arranged to establish a channel in the body region when said device is in operation; and

a source region is formed in the body region.

6. The method of claim 5, wherein the step of forming a plurality of semiconductor layers comprises the steps of:

forming a first layer of a first conductivity type overlying sidewalls and a bottom surface of the trench;

forming a first buffer layer overlying the first layer;

forming a second layer of a second conductivity type overlying the first buffer layer;

forming a second buffer layer overlying the second layer, wherein the first and second buffer layers have compositionally lower doping concentrations than the first and second layers; and

the remainder of the trench is filled with a dielectric material.

7. The method of claim 6, further comprising the steps of:

forming a capping layer on the first layer before forming the first buffer layer;

diffusing a dopant from the first layer into the region of semiconductor material to form a second doped region of the first conductivity type; and

and removing the covering layer.

8. The method of claim 5, wherein the step of forming the control electrode comprises the steps of:

forming a gate dielectric layer covering the side wall of the trench and the upper surface of the lower surface filling trench compensation region; and

a conductive layer is formed overlying the gate dielectric layer.

9. A semiconductor device, comprising:

a region of semiconductor material having a first major surface;

a filled trench structure formed in the region of semiconductor material, comprising:

a charge compensation portion recessed below the first major surface, wherein the charge compensation portion includes a first layer of a first conductivity type and a second layer of a second conductivity type overlying the first layer, and wherein the charge compensation portion connects the region of semiconductor material without an intervening dielectric material; and

a control portion formed overlying the charge compensation portion;

a body region of the first conductivity type formed in the region of semiconductor material adjacent the filled trench structure, wherein the control portion is arranged to create a channel in the body region when the device is in operation;

a source region formed in the body region; and

a first doped region of the second conductivity type formed in the region of semiconductor material and arranged to electrically connect the channel to the charge compensation portion when the device is in operation, wherein the first doped region abuts the first layer and the second layer.