HK1141135B - Semiconductor trench structure having a sealing plug and method - Google Patents

Description

Semiconductor trench structure with seal plug and method

Technical Field

This document relates generally to semiconductor devices and, more particularly, to trench structures and methods of formation.

Background

Trench structures have many uses in semiconductor device technology. These applications include isolation structures, control electrode structures, capacitor structures, charge compensated superjunction structures, and buried layer contact structures, among others. The trench structures are often filled and/or lined with materials such as dielectrics, semiconductor materials, conductor materials, or combinations of such materials, which are common sources of problems in trench structures.

For example, the filler material often causes high levels of stress within the device structure, which in turn causes defects to form and ultimately the device to fail. In particular, these defects create undesirable parasitic current leakage paths. Also, in some structures, silicon or polysilicon/oxide fill materials create parasitic MOS devices that may impair device performance. Furthermore, the hot carrier (electrons and holes) generated in the semiconductor fill material may generate undesirable electric fields that may damage the breakdown or off-state voltage of the trench structure. In addition, the methods used to form the trench structures typically introduce contaminants into the core region of the trench during processing. Such contamination may also lead to defect formation and general impairment of device performance.

Accordingly, there is a need for structures and methods to effectively plug or seal groove structures while reducing pressure, defects, parasitic structures, and contaminants.

Drawings

Fig. 1 shows an enlarged partial cross-sectional view of a semiconductor device according to a first embodiment of the present invention;

FIGS. 2-6 show enlarged, partial cross-sectional views of the semiconductor device of FIG. 1 at various stages of fabrication;

fig. 7 is an enlarged partial cross-sectional view of a semiconductor apparatus according to a second embodiment of the present invention; and

fig. 8-20 show enlarged, partial cross-sectional views of the semiconductor device of fig. 7 at various stages of fabrication.

For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and elements are omitted to simplify the description. Current carrying electrode as used herein refers to a device element that carries current through the device, such as a source or drain of a MOS transistor, or an emitter or collector of a bipolar transistor, or a cathode or anode of a diode; control electrode refers to a device element that controls current flow through the device, such as the gate of a MOS transistor or the base of a bipolar transistor. Although the device is explained herein as a certain N-channel device, one of ordinary skill in the art will appreciate that P-channel devices and complementary devices are also possible in accordance with the present invention. To simplify the drawing, the doped regions of the device structure are shown as having generally straight edges and precisely angled corners. However, those skilled in the art understand that due to the diffusion and activation of dopants, the edges of doped regions may not typically be straight and the corners may not be precisely angled.

Furthermore, the inventive structure may be embodied as a honeycomb base design (where the body region is a plurality of distinct and separate honeycomb regions) or a single base design (where the body region is a single region formed in an elongated pattern, typically in a spiral pattern or with a central region connected to an appendage). However, one embodiment of the present invention is described throughout the specification as a cellular base design for ease of understanding. It should be understood that the present invention is intended to cover both a honeycomb base design and a single base design.

Detailed Description

The present invention relates generally to semiconductor devices having one or more trench structures with plugs that seal or partially seal the core region of the one or more trenches. Specifically, a single crystal epitaxial semiconductor layer or a substantially homogeneous semiconductor layer or plug is formed along the upper sidewall surface of the trench. The thickness of the single crystal epitaxial layer is selected to seal or partially seal the core region in the upper portion of the trench. The following detailed description uses two practical embodiments to illustrate the invention. The first embodiment includes a semiconductor device having trench isolation structures, and the second embodiment includes an Insulated Gate Field Effect Transistor (IGFET) device having charge compensated trenches. It will be understood that the invention is not limited to these two embodiments.

Fig. 1 shows a partial cross-sectional view of a semiconductor device 10 according to a first embodiment of the present invention, the semiconductor device 10 having one or more isolation trench structures 322. It is understood that the isolated trench structure 322 comprises a plurality of individual trench structures, cells, stripes, or a continuous trench matrix. The device 10 includes a body or semiconductor material region 110 that includes, for example, a p-type silicon substrate 121, and a semiconductor layer or well region 124 that includes n-type conductivity. In one embodiment, semiconductor layer 124 is formed using conventional epitaxial growth techniques. In another embodiment, well region 124 is formed using conventional doping and diffusion techniques. Other materials that may be used for semiconductor material 110 or portions thereof include silicon-germanium, silicon-germanium-carbon, carbon-doped silicon, III-V materials, dielectric materials, and the like. Furthermore, in one embodiment, the semiconductor material 110 includes a buried layer between the substrate 121 and the semiconductor layer 124.

In this embodiment, trench structure 322 includes a trench 422 extending from major surface 18 of semiconductor material 110. In one embodiment, trench 422 extends through semiconductor layer 124 to substrate 121. In another embodiment, the trench 422 extends partially into the semiconductor layer 124. Dielectric layer(s) 128 are formed covering the lower sidewalls and lower surface of trench 422, leaving the upper sidewall surfaces of trench 422 exposed or uncovered. For example, the dielectric layer 128 includes an oxide, a nitride, a combination thereof, or the like. In one example, dielectric layer 128 comprises about 0.15 microns to about 0.25 microns of silicon dioxide. In another embodiment, the blanket silicon dioxide layer forms a silicon nitride layer of about 0.05 microns to about 0.1 microns.

In accordance with the present invention, isolation trench structure 322 further comprises a plug, conformal plug, single crystal sealing structure, substantially homogeneous plug or epitaxial cap structure or layer 91. Preferably, plug 91 comprises an epitaxially grown single crystal semiconductor structure extending from upper exposed sidewall portions 423 of trench 422. By exposed, it is meant that layer 128 is absent from sidewall portions 423, which exposes portions of semiconductor material 110/124 to provide a substantially single crystal interface in which single crystal epitaxial material grows. In one embodiment, plug 91 comprises p-type conductivity when semiconductor layer 124 comprises n-type conductivity. That is, the conductive type of the plug 91 is opposite to that of the semiconductor layer 124. Plug 91 has a volume sufficient to be in region 1 of device 10Between 001 and 1002 to provide an isolated doping concentration. For example, plug 91 has a thickness of from about 1.0 x 10¹⁷Atom/cm³To about 1.0X 10¹⁹Atom/cm³Doping concentration within the range.

In one embodiment, plug 91 completely seals groove 422 to provide a sealed core or centrally located void region 29. That is, the core 29 is free of solid material. In one embodiment, the wick 29 comprises a sealed volume containing a gas such as hydrogen. In one embodiment, the core 29 is under a vacuum of less than about 20 torr, typically 5 to 10 torr. In another embodiment, plug 91 partially seals groove structure 322, leaving a substantially centrally located gap in plug 91. In one embodiment, plugs 91 are formed using a selective epitaxial growth technique, leaving exposed major surface 129 of dielectric layer 128 substantially free of semiconductor material (i.e., plugs 91 do not cover major surface 129), which simplifies processing and reduces stress, among other things. Moreover, this reduces problems associated with hot carrier generation, which can generate undesirable electric fields, including breakdown voltages or off-state voltages of the structure. Furthermore, this also eliminates any parasitic MOS transistor features, especially when the plug 91 is doped. In one embodiment, plug 91 is planarized so that its upper surface 191 is at about the same level or adjacent to major surface 18. This is not necessary, but is useful in space sensitive applications.

The plug 91 provides, among other things, a lower pressure sealing configuration that also reduces the contamination that is incorporated into the groove 422. For example, because plug 91 may be configured to provide a complete seal, it is not necessary to completely fill core region 29 with a compressive material such as polysilicon. Also, since the plug 91 may be configured to provide a complete seal covering the trench 422, contaminants are not incorporated into the core region during subsequent processing.

The apparatus 10 also includes an optional isolation region 17 to provide additional isolation, the optional isolation region 17 being, for example, p-type doped (i.e., of opposite conductivity type to the semiconductor layer 124). In this optional embodiment, plug 91 may be doped or undoped. Isolation regions 17 are formed using conventional techniques before or after forming plugs 91. Device 10 is further shown wherein dielectric layer 148 is formed overlying or adjacent major surface 18. For example, the dielectric layer 148 includes oxide, nitride, a combination of the two, and the like. As shown, isolation trench structure 322 provides isolation between regions 1001 and 1002. Furthermore, the isolation trench structure 322 provides an isolation region 1003 for forming a component 424 (e.g., a passive component). For example, component 424 is a capacitor, inductor, input/output pad, or any structure that requires isolation from semiconductor material 110 or a portion thereof.

Referring now to fig. 2-6, a method for forming the isolation trenches 322 of fig. 1 is described. Fig. 2 shows a partial cross-sectional view of the device 10 in an early manufacturing step. In an early step, the isolation regions 17 are formed using, for example, conventional masking and doping techniques. As previously mentioned, region 17 is optional and may be omitted. Next, a dielectric layer 40 is formed overlying major surface 18, and dielectric layer 40 comprises, for example, a thermal oxide about 0.03 microns thick. A dielectric layer 44 comprising a different material than the dielectric layer 40 is then formed overlying the dielectric layer 40. For example, when first dielectric layer 40 is silicon oxide, dielectric layer 44 is silicon nitride. In one embodiment, dielectric layer 44 is approximately 0.2 microns of silicon nitride and is formed using conventional deposition techniques. Next, a dielectric layer 46 is formed overlying dielectric layer 44, and dielectric layer 46 comprises approximately 0.6 microns of deposited silicon dioxide. These layers provide a hard mask structure 112 for subsequent processing. Openings 172 are then formed using conventional techniques to remove portions of layers 46, 44, and 40 to expose a portion of major surface 18.

Next, a trench 422 is formed that extends from the major surface 18 into the semiconductor layer 124 through the opening 172. In one embodiment, the trench 422 extends into at least a portion of the substrate 121. In one embodiment, the depth of the trench 422 is determined by the semiconductor layer 124.

In one embodiment, Deep Reactive Ion Etching (DRIE) etching with fluorine or chlorine based chemistry is used to form trenches 422. Some techniques that may be used for the DRIE etch bath 422 include low temperature, high density plasma, or Bosch DRIE processes. In one embodiment, the trench 422 has substantially vertical sidewalls. In an alternative embodiment, grooves 422 have a tapered profile, wherein the width of the grooves at the lower surface of the grooves is less than the width proximate major surface 18. In another embodiment where a larger gap is desired to further enhance isolation (both lateral and longitudinal), the grooves 422 have a flared profile in which the width of the grooves at the lower surface is greater than the groove width proximate the major surface 18. In one embodiment, the depth of the trench 422 is in a range from about 3.0 microns to about 100 microns. During the trench clean process, a short selective etch is typically used that can undercut the dielectric layer 40 as shown in fig. 2. To prevent any further undercutting of dielectric layer 40, polysilicon layer 47 is formed overlying major surface 18, including the sidewalls and lower surface of trench 422, and fills the undercut regions of dielectric layer 40.

Fig. 3 shows an enlarged partial cross-sectional view of the device 10 at a further stage of fabrication. First dielectric layer 28 is formed overlying major surface 18, including the sidewalls and lower surface of trench 422. For example, the first dielectric layer 28 comprises an oxide. In one embodiment, 0.04 microns of dry oxide is formed to consume polysilicon layer 47, but to retain that portion of polysilicon layer 47 in the undercut region of layer 40, followed by deposition of approximately 0.2 microns of oxide. Next, a second dielectric layer is formed overlying the first dielectric layer 28. In one embodiment, the second dielectric layer comprises about 0.1 micron of silicon nitride. The first and second dielectric layers are formed using conventional deposition techniques. The second dielectric layer is then etched back using conventional dry etch techniques, leaving dielectric spacers, spacer layers, or dielectric layer 62 within trenches 422, as shown in fig. 3. Depending on the etch process used and the aspect ratio of trench 422, dielectric layers 28 and 62 may be etched away from the lower surface of trench 422 or left in place, as shown in fig. 3. In lower aspect ratio trenches, conventional masking steps may be used to prevent dielectric layers 28 and 62 from being removed at the lower surfaces of trenches 422.

Next, as shown in fig. 4, which is an enlarged partial cross-sectional view of device 10 after further processing, dielectric layer 28 is subjected to an additional selective etching step to remove upper portions of the dielectric material so that dielectric layer 28 is recessed from the upper surface of dielectric layer 62. If the lower portions of dielectric layers 28 and 62 were removed in the step described in connection with fig. 2, the selective etch would also remove dielectric layer 28 from the open areas exposed at the bottom of trenches 422. For example, when dielectric layer 28 comprises an oxide, dielectric layer 28 is recessed below dielectric layer 62 by about 1.2 microns using an isotropic etch, such as a dilute HF wet etch (e.g., at 10: 1 for about 8-11 minutes). During these steps, the dielectric layer 46 may also be removed. Dielectric layers 62 and 64 are then removed as shown in fig. 5 using conventional material removal techniques to provide exposed portions 423 of semiconductor material 10 in the upper portions of trenches 422. This method provides a very controllable method for forming the exposed portion 423 compared to a method based on anisotropic etching.

Fig. 6 shows an enlarged partial cross-sectional view of the apparatus 10 after further processing. According to a preferred embodiment, an epitaxial plug, a single crystal plug, a plug of semiconductor material, or a homogeneous semiconductor plug region 91 is formed on dielectric layer 28 within the opening of trench 422 along exposed portion 423 of semiconductor layer 124. According to this embodiment, the plug 91 comprises an epitaxial semiconductor material having a conductivity type opposite to that of the semiconductor layer 124. In the embodiment shown, plug 91 is p-type. In this embodiment, the plug 91 has a thickness of between about 1.0 x 10¹⁷Atom/cm³And about 1.0X 10¹⁹Atom/cm³With the doping concentration in between. In an alternative embodiment, the plug 91 is undoped.

In one embodiment of forming plug 91, a dichlorosilane source gas is used with hydrogen gas and HCl, which allows growth to be selective only toward exposed portion 423. In alternative embodiments, silane, disilane, or trichlorosilane source gases are used. The epitaxial reactor pressure is set in the range of about 10 torr to atmospheric pressure depending on the growth temperature selected. In one embodiment, a single crystal reactor is used during the growth process, the reactor pressure being about 20 torr. Suitable growth temperatures for dichlorosilane range from about 950 ℃ to 1050 ℃. Suitable growth temperatures for silane or disilane are in the range of about 575 ℃ to about 700 ℃. Suitable growth temperatures for trichlorosilane are in the range of about 1000 ℃ to about 1200 ℃. In one embodiment, plug 91 has a thickness in a range from about 0.10 microns to about 0.60 microns. It will be appreciated that the thickness of the plug 91 is adjusted according to the width of the slot 422. For example, the thickness is adjusted depending on the desired configuration of the plug 91 (e.g., near closure, full closure, or overgrowth).

In one embodiment, when using selective epitaxial growth techniques and dichlorosilane, a growth rate of about 0.30 microns/minute is used. When using a non-selective epitaxial growth technique and dichlorosilane, a growth rate of about 1.0 micron/minute to about 2.0 microns/minute is used. The gas flow rate depends on the reactor configuration and is set by the desired growth conditions and structure. In one embodiment, in a closed configuration using dichlorosilane, the following gas flow ranges are used in a selective growth process to form plugs 91: 30-40 standard liters per minute (slm) of hydrogen, 0.70-0.80slm of HCl, and 0.20-0.25slm of dichlorosilane.

According to a preferred embodiment, plug 91 is configured to seal off trench 422 to form sealed core 29, and is also configured to seal off with minimal defects and non-negligible pressure compared to using dielectric/polysilicon or polysilicon fill techniques. By reducing defects and stress, the reliability and quality of the apparatus 10 is improved. In one embodiment, when plugs 91 are formed using a selective epitaxial growth technique, major surface 129 of dielectric layer 28 is substantially free of semiconductor material (i.e., plugs 91 do not cover major surface 129), which simplifies processing and reduces stress, among other things. Also, this reduces problems associated with hot carrier generation. Furthermore, this eliminates any parasitic MOS transistor features, especially when the plug 91 is doped. In one embodiment, sealed core 29 is under a vacuum of about 20 torr, with some hydrogen from the epitaxial growth process being present in sealed core 29.

Fig. 7 shows a partial cross-sectional view of an Insulated Gate Field Effect Transistor (IGFET), MOSFET, super junction device, super junction structure, charge compensation or switching device or battery 100 according to a second embodiment of the present invention. For example, in some such devices, apparatus 100 is integrated with logic components or other components, among others, in a semiconductor chip as part of a power integrated circuit. Alternatively, in some such devices, the apparatus 100 is integrated together to form, among other things, a discrete transistor apparatus.

The apparatus 100 includes a region of semiconductor material 11 that includes, for example, an n-type silicon substrate 12 having a resistivity in the range of about 0.001 to about 0.01 ohm-centimeters (ohm-cm), and which may be doped with arsenic or phosphorous. In the embodiment shown, the substrate 12 provides the device 100 with a drain region adjacent the conductor layer 13. Semiconductor layer 14 is formed in or on substrate 12 and is either n-type or p-type and is doped lightly enough so as not to affect the charge balance of the trench compensation region described below. In one embodiment, layer 14 is formed using conventional epitaxial growth techniques. In an embodiment suitable for 600 volt (BVdss) devices, layer 14 is n-type doped or p-type doped with a doping concentration of about 1.0 x 10¹³Atom/cm³To about 1.0X 10¹⁴Atom/cm³And has a thickness on the order of about 40 microns to about 60 microns. Note that although semiconductor layer 14 is shown in the figures as being thicker than substrate 12, in practice substrate 12 is thicker. Shown in this manner for ease of understanding in the figures.

In one embodiment, a portion of layer 14 is p-type doped in the active region portion of device 100, while another portion of layer 14 is n-type doped in the edge termination portion of device 10. The thickness of layer 14 increases or decreases depending on the desired BVdss rating of device 10. In an alternative embodiment, semiconductor layer 14 comprises a graded doping profile, wherein semiconductor layer 14 has a higher doping concentration proximate substrate 12 and gradually or abruptly transitions to a lower concentration for balancing its thickness proximate major surface 18.

Other materials that may be used for the body or portion of semiconductor material 11 include silicon-germanium, silicon-germanium-carbon, carbon-doped silicon, III-V materials, and the like. Furthermore, those skilled in the art will appreciate that an Insulated Gate Bipolar Transistor (IGBT) device is achieved in the present invention by, for example, changing the conductivity type of base 12 to p-type (i.e., opposite semiconductor layer 14).

The apparatus 100 further includes spaced apart filled trenches, compensation trenches, semiconductor material filled trenches, charge compensation trench regions, deep trench charge compensation regions, charge compensation filled trenches, compensation trenches, localized vertical charge compensation structures, or localized charge compensation regions 22. As used herein, charge compensation generally refers to the total charge of the opposite conductivity type layers being substantially or substantially balanced or equal. The charge compensating filled trench comprises a plurality of layers or composite layers of semiconductor material 220 comprising at least two layers of opposite conductivity type (i.e., at least one each of n-type and p-type) that may be separated by a self-structure, buffer, or lightly doped semiconductor layer. As shown in fig. 7, material 220 comprises a layer 221 of n-type semiconductor material that abuts semiconductor layer 14 along the trench sidewall surfaces.

According to a preferred embodiment, layer 221 has the same conductivity type as source region 33 and forms the main vertical low resistance current path from the channel to the drain when device 100 is in the on state. A blanket layer 221 of compensating p-type semiconductor material layer 222 is formed. For example, n-type layer 221 and p-type layer 222 have about 9.0 x 10¹⁵To about 5.0X 10¹⁶Atom/cm³And each has a thickness of about 0.1 microns to about 0.3 microns, respectively. When device 100 is in the off state, p-type layer 222 and n-type layer 221 compensate each other to provide increased BVdss characteristics. Although the buffer layers are not shown in the device of fig. 7, it should be understood that they may be present in an early step of fabrication. In a preferred embodiment, the layer of semiconductor material 220 comprises a single crystal semiconductor material. Additional details regarding charge-compensated trenches 22 and layers of semiconductor material 220 are described below in conjunction with fig. 4 and 5.

In a preferred embodiment, device 100 includes a semiconductor layer 28 formed overlying a portion of layer of semiconductor material 220. Preferably, dielectric layer 28 is formed overlying portions of the sidewall surfaces and the lower surface of the layer of semiconductor material 220, leaving the upper sidewall portions exposed. This is shown by way of example in fig. 7. In one embodiment, dielectric layer 28 is a deposited silicon oxide layer having a thickness of about 0.2 microns. In the illustrated embodiment, charge compensation slot 22 is partially configured or formed with a void or closed core 29 in a central location and is capped by a plug structure 91. In a preferred embodiment, plug 91 comprises a single crystal semiconductor material that is epitaxially grown along an upper portion of layer of semiconductor material 220 to block charge compensation trenches 22. In one embodiment, the single crystal semiconductor material is subsequently planarized so that the upper surface of plug 91 is proximate major surface 18. In an alternative embodiment, charge-compensated trenches 22 are void-free and filled with a material such as a dielectric, a polycrystalline semiconductor material, a single crystal semiconductor material, or a combination thereof.

Although not shown, it should be understood that during the formation of apparatus 100, n-type dopants diffuse from highly doped substrate 12 into the underlying portions of charge-compensated trenches 22 so that those portions of trenches 22 within substrate 12 become more highly n-type doped.

The apparatus 100 further includes a hole, base, body or doped region 31 formed in the semiconductor layer 14 between the charge compensation trenches 22, proximate, adjacent, or abutting the charge compensation trenches 22. Body region 31 extends from major surface 18 of semiconductor material 11. In one embodiment, body region 31 comprises p-type conductivity and has a doping concentration suitable for forming an inversion layer that operates as a conductive channel of device 100. The body region 31 extends from the major surface to a depth of about 1.0 to about 5.0 microns. As noted above, the body region 31 comprises a plurality of individually discrete regions or connected, single or generally discrete regions comprising selected shapes.

An N-type source region 33 is formed within, on, or in body region 31 and extends from main surface 18 to a depth of about 0.2 microns to about 0.5 microns. In the embodiment shown, a portion of major surface 18 extends downward and then outward from the edge of source region 33 to make contact with the horizontal and vertical surfaces of source region 33 through source contact layer 63. One or more p-type body contact regions 36 are formed in at least a portion of each body region 31. The body contact region 36 is configured to provide a lower contact resistance to the body region 31 and to reduce the sheet resistance of the body region 31 below the source region 33, which reduces parasitic bipolar transistor effects.

According to a preferred embodiment, as shown in fig. 7, the body contact region 36 and the body region 31 cover the charge compensation trenches 22 and are configured with the source contact layer 63 to provide ohmic connection and continuity with the p-type layer 222 in the charge compensation trenches 22. This ohmic connection is configured to provide a ground structure for p-type layer 222 that eliminates lateral electric fields at major surface 18 and improves breakdown voltage performance of device 100. This configuration also transmits to ground the effects of any defects present near major surface 18 and within or near charge-compensated trenches 22. The structure of device 100 greatly simplifies the ability to make contact with layer 222, which is necessary for optimal device performance. In particular, the apparatus 100 avoids the use of any complex surface features to cover the upper portion of the charge compensation trenches 22, simplifying the ohmic connection structure and method.

The device 100 further comprises a trenched gate or control structure 157 adjoining the body region 31 and the source region 33. Control structure 157 is laterally spaced from adjacent charge-compensated trenches 22. That is, control structure 157 does not cover charge-compensated trenches 22. The trench gate structure 157 includes a gate trench 158 and a gate dielectric layer 43 formed to cover a surface of the gate trench 158. In one embodiment, gate dielectric layer 43 comprises silicon oxide and has a thickness of about 0.05 microns to about 0.1 microns. In another embodiment, the thickness of gate dielectric layer 43 at the lower surface of gate trench 158 is greater than or thicker than the thickness of gate dielectric layer 43 along the sidewalls of gate trench 158. In alternative embodiments, gate dielectric layer 43 comprises silicon nitride, tantalum oxide-free, titanium dioxide, barium strontium titanate, combinations thereof (including combinations with silicon oxide), or the like.

Trench gate structure 157 also includes a conductive gate region 57 formed within control or gate trench 158 and overlying gate dielectric layer 43. In one embodiment, the source region 33 is interposed between the conductive gate region 57 and the charge compensation trench 22. Conductive gate region 57 comprises, for example, n-type polysilicon. Although conductive gate region 57 is shown recessed below major surface 18, conductive gate region 57 may extend higher or above major surface 18. The trench gate structure 157 is configured to control the formation of the channels 45 and the conduction of current within the device 100.

To facilitate the sub-surface current path, device 100 also includes an n-doped or sub-surface doped layer 26. In particular, doped layer 26 is configured to provide a sub-surface conductive path between the drain end of channel 45 and n-type layer 221, which is the main conductive layer or vertical conductive path in charge-compensated trench 22. That is, the current of the apparatus 100 flows as follows: vertically through channel 45, then horizontally through doped layer 26, then vertically through layer 221. Doped layer 26 is configured such that current is isolated from major surface 18 by body region 31 and body contact region 36 of opposite conductivity type (p-type) to doped layer 26 (n-type). Such isolation features keep the conductive path away from the defect area near the surface, thereby avoiding any problems associated with conduction. In addition, the grounded p-type layer 222 structure further isolates the effects of any high defect density regions from the main conductive path. In addition, by placing the body region 31 and the body contact region 36 such that they cover the doped region 26, a preferred concave bond is provided, which surrounds the n-type layer 221 and the doped layer 26. This can advantageously enhance BVdss.

Device 100 also includes an interlayer dielectric region 48 formed overlying major surface 18 and scribed to provide openings to primary contact region 36 and source region 33. A portion of the interlayer dielectric region 48 is maintained overlying the trench gate structure 57 to provide isolation for the conductive gate region 57. Interlayer dielectric region 48 comprises, for example, silicon oxide, such as a deposited oxide, and has a thickness of about 0.4 microns to about 1.0 microns.

A source contact layer 63 is formed overlying major surface 18 and makes contact with source regions 33 and body contact regions 36. In one embodiment, the source contact layer 63 includes a titanium/titanium nitride barrier layer and an aluminum silicon alloy or the like formed to cover the barrier layer. A drain contact layer 13 is formed overlying the opposite surface of the semiconductor material 11 and comprises, for example, a solderable metal structure such as titanium-nickel-silver, chromium-nickel-gold, or the like. Alternatively, the layer 13 contains a conductive epoxy resin or the like.

In summary, the structure and method of apparatus 100 places primary conductive layer 221 adjacent to the sidewall surface of charge-compensated trenches 22. Device 100 uses a trench gate control structure 157 that places the drain end of channel 45 spaced from, remote from, or below major surface 18. Device 100 incorporates a subsurface doped layer 26, which subsurface doped layer 26 electrically connects the subsurface drain end of channel 45 to a main conductive layer 221 in charge compensation trench 22. This approach keeps the primary current path away from the device surface, which makes it less susceptible to stress events and defects, thereby improving performance. Furthermore, since the main current path of the device 100 is configured in this way, an ohmic connection structure between the p-type compensation doping layers 222 is formed, so that the body region 31, the body connection region 36 and the source contact layer 63 are simplified.

The operation of the apparatus 100 proceeds as follows. Assume that source terminal 63 is at a voltage V of zero volts_SIn operation, the conductive gate region 157 receives a control voltage V of 5.0 volts_GThe control voltage being greater than the control threshold of the device 100 and the drain terminal 13 being at a drain voltage V of 5.0 volts_DAnd (5) operating. V_GAnd Vs have values such that body region 31 inverts the adjacent conductive gate region 157 to form vertical channel 45 electrically connecting source region 33 and doped layer 26. Device current I_DFlows from drain terminal 13 and through n-type layer 221, doped layer 26, channel 45, source region 33 to source terminal 63. Thus, current I_DFlows vertically through n-type layer 221 to create low resistance and flows horizontally through subsurface doped layer 26 to keep the current path isolated from major surface 18. In one embodiment, I_D1.0 ampere. Turning the device 100 to an off state, a control voltage less than the device conduction threshold is applied to the conductive gate regionField 157 (e.g., V)_G< 5.0 volts). This removes the channel 45 and I_DNo longer flows through the device 100. In the off state, n-type layer 221 and p-type layer 222 compensate each other as the depletion region extends from the main barrier junction, which enhances BVdss. Another advantage of device 100 is that the simplified ohmic contact between p-type compensating doped layer 222, body region 31, body contact region 36, and source contact layer 63 enhances the switching characteristics. For example, the ohmic contact may more efficiently pull electrons and holes from the structure when the device 100 is switched from an on state to an off state.

Turning now to fig. 8-20, a method of forming the apparatus 100 is depicted in accordance with a preferred embodiment. Fig. 8 shows an enlarged partial cross-sectional view of the apparatus 100 at an early stage of fabrication. Examples of material characteristics of the body of semiconductor material 11 are provided in connection with fig. 7 above. In an early step, dielectric layer 40 is formed overlying major surface 18 and comprises, for example, a thermal oxide about 0.2 microns thick. A dielectric layer 44 comprising a different material than dielectric layer 40 is then formed overlying dielectric layer 40. For example, dielectric layer 44 is silicon nitride when first dielectric layer 40 is silicon oxide. In one embodiment, dielectric layer 44 is approximately 0.2 microns of silicon nitride and is formed using conventional deposition techniques. Next, a dielectric layer 46 is formed overlying dielectric layer 44 and comprises about 0.6 microns of deposited silicon dioxide. These layers provide a hard mask structure 112 for subsequent processing.

Fig. 9 shows an enlarged partial cross-sectional view of apparatus 100 at a subsequent stage of fabrication. The hard mask structure 112 is scribed using conventional photolithography and material removal techniques to form an opening 72 that exposes a portion of the major surface 18. For example, the opening 72 has a width 74 of about 3.0 microns to about 4.0 microns. Next, trench 122 is formed through opening 72 extending from major surface 18 into semiconductor layer 14. In one embodiment, semiconductor layer 14 has a width 75 of about 2.0 microns to 3.0 microns between adjacent trenches 122. For ease of understanding this embodiment, width 75 is shown to be greater than width 74, it being understood that width 75 may be less than or equal to width 74. In one embodiment, the slot 122 extends into at least a portion of the substrate 12. The depth of trench 122 is determined by the thickness of semiconductor layer 14, which thickness of semiconductor layer 14 is a function of the desired BVdss.

In one embodiment, Deep Reactive Ion Etching (DRIE) etching with fluorine or chlorine based chemistry is used to form trenches 122. Some techniques that may be used for the DRIE etch bath 122 include low temperature, high density plasma, or Bosch (Bosch) DRIE processes. In one embodiment, the slots 122 have substantially vertical sidewalls. In an alternative embodiment, the groove 122 has a tapered profile, wherein the width of the groove at the lower surface of the groove is less than the width 74. Although the grooves 122 are described in plural numbers, it should be understood that the grooves 122 may be a single continuous groove or a connected groove matrix. Alternatively, trenches 122 may be a plurality of individual trenches having closed ends and separated by a body of partially semiconductor material 11. The width of the slots 122 is in the range of about 3.0 microns to about 100 microns.

Fig. 10 shows an enlarged partial cross-sectional view of the apparatus 100 at a later stage of fabrication. At this point, a layer of semiconductor material 220 is formed, grown, or deposited in trenches 122 as a first step in forming charge-compensated trenches 22. In one embodiment, the layer of semiconductor material 220 is formed using a single crystal semiconductor epitaxial growth technique.

In a first step, a thin oxide (not shown), such as a thermal oxide, is formed on the sidewalls of the trenches 122 to eliminate any surface damage caused by the material removal step. The thin oxide is then removed using conventional isotropic etch techniques (e.g., 10: 1 wet oxide strip). Next, the semiconductor material 11 is placed in an epitaxial growth reactor and pre-cleaned as a first step of the epitaxial growth process. When silicon is the semiconductor material of choice for forming semiconductor 220 layers, a silicon source gas is suitable for forming these layers, such as trichlorosilane (SiHCl)₃) Dichlorosilane (SiH)₂Cl₂) Silane (SiH)₄) Or disilane (Si)₂H₆)。

Referring now to fig. 11, which is a partial cross-sectional view of a portion 1011 of trench 122 of fig. 10, the formation of a preferred embodiment of a layer of semiconductor material 220 is depicted. In a preferred embodiment, all layers making up the layer of semiconductor material 220 are grown in a continuous manner inside the epitaxial reactor. In addition, it has been found that a lower pressure epitaxial reactor is preferred in forming the layer of semiconductor material 220. In particular, it is preferable to set the epitaxial growth conditions to provide a mean free path that is approximately equal to or greater than the depth of the trenches 122. It is also preferred that the aspect ratio of trenches 122 be in the range of about 1: 1 to about 30: 1 to provide good quality epitaxial layers.

It is also preferred to use a selective epitaxial growth method to avoid growing epitaxial silicon overlying dielectric layer 46 to produce polysilicon. Selectivity is controlled by adding an amount of HCl gas to the epitaxial growth chamber sufficient to inhibit silicon growth on the dielectric layer. Preferably, when dichlorosilane or silane is used as the silicon source gas, the flow rate of HCl is set in a range of greater than 0 to 4 to 5 times the flow rate of the silicon source gas. In an alternative embodiment, the cladding layer is grown (i.e., the layers are grown overlying major surface 18 in addition to trenches 122), and a planarization technique is used to remove the portion of the cladding layer overlying major surface 18.

In the embodiment shown, intrinsic layer 21 is first formed along the surface of trenches 122 and has a thickness of about 0.05 to about 0.1 microns. The intrinsic layer 21 is preferably undoped and functions, inter alia, to smooth irregularities on the sidewalls and lower surface of the trenches 122. The capping layer 21 then forms an n-type layer 23 where a phosphorus, arsenic or antimony dopant source is appropriate. In one embodiment, the n-type layer 23 is lightly doped and has a thickness of about 1.0 x 10¹⁵To about 1.0X 10¹⁷Atom/cm³Doping concentrations of the order of magnitude. The N-type layer 23 typically has a thickness of less than about 1.0 micron, with a thickness of about 0.1 micron to about 0.4 micron being one preferred range.

Next, an intrinsic layer 24 is formed overlying n-type layer 23 and has a thickness of about 0.1 to about 0.4 microns. Preferably, the intrinsic layer 24 is undoped. A p-type layer 25 is then formed overlying the second intrinsic layer 24, with boron being a suitable dopant source. For example, the p-type layer 25 has about 1.0 x 10¹⁵To about 1.0X 10¹⁷Atom/cm³Doping concentrations of the order of magnitude. The p-type layer 25 has a thickness that is typically less than about 1.0 micron, with a thickness of about 0.1 micron to about 0.3 micron being one preferred range. One purpose of intrinsic layer 24 is to improve conductivity by reducing the mutual consumption of layers 23 and 25 at low drain voltages, providing higher conductivity efficiency.

Next, an intrinsic layer 27 is formed overlying p-type layer 25 and has a thickness of about 0.1 to about 1.0 microns. During the subsequent heat treatment, as shown in fig. 7 and 10, the dopant in the n-type layer 23 diffuses into the intrinsic layers 21 and 24 to form an n-type layer 221; and as shown in fig. 7 and 10, the p-type layer 25 diffuses into the intrinsic layers 24 and 27 to form a p-type layer 222. The composite layers shown in fig. 11 are not shown in the other figures for ease of understanding. The doping concentrations and thicknesses of n-type layer 221 and p-type layer 222 are configured to provide a suitable balance charge when apparatus 100 is in operation. In a preferred embodiment, the central or central portion of the retaining groove 122 is open (i.e., the portion is not completely filled with solid material). Furthermore, in a preferred embodiment, after the layer of semiconductor material 220 is formed, the epitaxial reactor is purged with HCl, source gases, and dopant gases, and the apparatus 100 is exposed to hydrogen at a higher temperature. This smoothes the surface features of the outer surface of the layer of semiconductor material 220, thereby enhancing, among other things, subsequent processing, including the formation of plugs 91.

Fig. 12 shows an enlarged partial cross-sectional view of apparatus 100 at a further stage of fabrication. A first dielectric layer is formed overlying major surface 18 and semiconductor material 220 layer in trench 122. Such a first dielectric layer comprises, for example, an oxide. In one embodiment, 0.02 microns of dry oxide is formed, followed by about 0.2 microns of deposited oxide. Next, a second dielectric layer is formed overlying the first dielectric layer. In one embodiment, the second dielectric layer comprises about 0.1 micron of silicon nitride. The first and second dielectric layers are formed using conventional deposition techniques. Conventional dry etch techniques are then used to etch back the dielectric spacers, spacers or dielectric layers 28 and 62 of the respective materials within the first and second dielectric layer retention slots 122, as shown in fig. 12. In the illustrated embodiment, layer 28 comprises about 0.02 microns of dry oxide and about 0.2 microns of deposited oxide and layer 62 comprises about 0.1 microns of silicon nitride.

Next, as shown in fig. 13, which is an enlarged partial cross-sectional view of apparatus 100 after further processing, dielectric layer 28 is subjected to an additional selective etching step to remove an upper portion of the dielectric material so that dielectric layer 28 is recessed from an upper surface of dielectric layer 62. For example, when dielectric layer 28 comprises an oxide, dielectric layer 28 is recessed below dielectric layer 62 by about 1.2 microns using a dilute HF wet etch (e.g., 10: 1 for about 8-11 minutes). During these steps, the dielectric layer 46 may also be removed. Dielectric layers 62 and 44 are then removed as shown in fig. 14 using conventional material removal techniques.

Fig. 15 shows an enlarged partial cross-sectional view of the apparatus 100 after another process. According to a preferred embodiment, an epitaxial plug, a single crystal plug, a plug of semiconductor material, or a semiconductor plug region 91 is formed along the exposed portion of the layer of semiconductor material 220 within the opening remaining in trench 122 above dielectric layer 28. According to this embodiment, plug 91 comprises an epitaxial semiconductor material having a conductivity type opposite to that of semiconductor layer 14. In the embodiment shown, plug 91 is p-type. In one embodiment, the plug 91 has a thickness of between about 1.0 x 10¹⁷Atom/cm³And about 1.0X 10¹⁹Atom/cm³With the doping concentration in between. In an alternative embodiment, the plug 91 is undoped. Preferably, the plugs 91 are formed using a lower pressure and selective epitaxial growth technique.

In one embodiment for forming plugs 91, a dichlorosilane source gas is used with hydrogen and HCl, which allows growth to be selective only toward the upper portion of trenches 122. In alternative embodiments, silane, disilane, or trichlorosilane source gases are used. The epitaxial reactor pressure is set in the range of about 10 torr to atmospheric pressure depending on the growth temperature selected. In one embodiment, a single wafer reactor is used during the growth process, with a reactor pressure of about 20 torr. Suitable growth temperatures for dichlorosilane range from about 950 ℃ to 1050 ℃. Suitable growth temperatures for silane or disilane are in the range of about 575 ℃ to about 700 ℃. Growth temperatures suitable for trichlorosilane range from about 1050 ℃ to about 1175 ℃. Note that higher growth temperatures need to be used to avoid unwanted dopant mixing within the various epitaxial layers or doped regions of the device 100. In one embodiment, plug 91 has a thickness in a range from about 0.10 microns to about 0.60 microns. For example, the thickness is adjusted depending on the desired configuration of the plug 91 (e.g., near closure, full closure, or overgrowth).

In one embodiment, when using selective epitaxial growth techniques and dichlorosilane, a growth rate of about 0.30 microns/minute is used. When using non-selective epitaxial growth techniques and dichlorosilane, growth rates in the range of about 1.0 micron to about 2.0 microns are used. The gas flow rate depends on the reactor configuration and is set by the desired growth conditions and structure. In one embodiment, in a closed configuration using dichlorosilane, the following gas flow ranges are used in a selective growth process to form plugs 91: 30-40 standard liters per minute (slm) of hydrogen, 0.70-0.80slm of HCl, and 0.20-0.25slm of dichlorosilane.

According to a preferred embodiment, plug 91 is configured to seal off void 29 in trench 122 and is also configured to seal off with minimal defects and negligible pressure compared to using dielectric/polysilicon or polysilicon fill techniques. By reducing defects and stress, the reliability and quality of the apparatus 100 is improved. In one embodiment, sealed core 29 is under a vacuum of less than about 20 torr, with some hydrogen from the epitaxial growth process being present in sealed core 29.

After forming plugs 91, polycrystalline semiconductor layer 92 is formed overlying major surface 18. For example, layer 92 comprises a polysilicon layer about 0.6 microns to about 0.9 microns thick and is formed using conventional deposition techniques. A planarized photoresist layer 93 on the order of 1.0 to 2.0 microns is then formed overlying polycrystalline semiconductor layer 92.

Fig. 16 is an enlarged partial cross-sectional view of apparatus 100 after removing exposed or overlying portions of layer 93, layer 92, and plugs 91 using a planarization or bulk removal process. For example, conventional etch-back techniques are used for this removal step. Alternatively, chemical mechanical planarization techniques are used. Layer 40 (shown in fig. 15) is then removed using, for example, a wet chemical etch. Next, dielectric layer 94 is formed overlying major surface 18 and comprises, for example, an implanted oxide having a thickness of about 0.05 microns to about 0.09 microns. A scribed photoresist layer 96 is then formed overlying major surface 18 in preparation for forming doped layer 26.

Dopants for doping layer 26 are then introduced and supplied to semiconductor layer 14 below major surface 18, using scribed photoresist layer 96 as a mask. In one embodiment, high energy ion implantation is used to implant dopants for doped layer 26. For example, phosphorus implantation in the MeV range is used, and is about 1.0X 10¹²Atom/cm²The implantation dose of (a) is sufficient. In this embodiment, layer 26 has a doping concentration greater than that of semiconductor layer 14 to provide a path of lower resistance between channel 45 (shown in fig. 1) and n-type layer 221. In one embodiment, a high-power implant places doped layer 26 below major surface 18 (as shown in fig. 16) so that doped layer 26 is a sub-surface, and then patterned photoresist layer 96 is removed. The implanted dopant is then heat treated to diffuse the n-type dopant into semiconductor layer 14 to a selected depth. For example, doped layer 26 extends to a depth of about 2.0 microns to about 3.0 microns. According to one embodiment, in the final structure, doped layer 26 has a depth greater than body region 31 (shown in fig. 7). In an alternative embodiment, a combined heat treatment step is used after the introduction of dopants for the body regions 31 as described below in fig. 17. In an alternative embodiment, the doped layer 26 is formed before the trenches 122 are formed. For example, doped layer 26 is formed prior to the formation of hard mask 112 shown in FIG. 8.

Fig. 17 shows an enlarged partial cross-sectional view of the device 100 at a later fabrication step. A p-type dopant for the body region 31 is introduced or provided at the main surface 18. According to one embodiment, the main body region 31 extends laterally over all or part of the compensation groove 22. That is, body region 31 overlaps at least p-type layer 222. For example, about 1.0X 10 is used¹³Atom/cm²And ion implantation at a boron implant dose and an implant energy of about 160 KeV. In an alternative embodiment, a series of boron implants are used to form the body region 31, first a lower dose/higher energy implant followed by an increasing dose and decreasing energy implant. In yet another embodiment, this order is reversed. The implanted p-type dopant is heat treated to diffuse and/or activate the dopant that forms region 31. For example, the body region 31 has a depth of about 1.0 to about 2.0 microns.

Fig. 18 is an enlarged partial cross-sectional view of the device 100 after completion of a preliminary step of forming the control or gate trench 158. In an early step, a dielectric layer 98 is formed overlying dielectric layer 94. For example, dielectric layer 98 comprises a silicon nitride layer that is about 0.1 microns to about 0.2 microns thick and is formed using conventional techniques. Next, a photoresist layer (not shown) is deposited overlying dielectric layer 98 and openings are formed to control trenches 158. Portions of layers 98 and 94 are then removed to expose portions of major surface 18. The photoresist layer is then removed. Control trench 158 is then formed extending from major surface 18 generally centrally located between adjacent charge compensation trenches 22. Control trench 158 is formed using a conventional anisotropic dry etch, for example. For example, control trench 158 has a width of about 0.4 microns to about 0.7 microns and has a depth greater than body region 31. In a preferred embodiment, control trench 158 has a depth greater than doped region 26. In one embodiment, control trench 158 has a depth of about 1.0 micron to about 1.6 microns.

Fig. 19 is an enlarged cross-sectional view of the apparatus 100 after further processing. In one embodiment, a thin thermal oxide blanket is grown over the exposed surfaces of control trench 158. This oxide is then removed. Dielectric layer 98 is also removed. Next, a gate dielectric layer 43 is formed covering the surface of the control trench 158. In one embodiment, gate dielectric layer 43 comprises silicon oxide and has a thickness of about 0.05 microns to about 0.1 microns. In another embodiment, the gate dielectric layer 43 is thicker along the bottom and lower sidewall portions of the control trench 158. A conductive layer, such as a doped or undoped polysilicon layer, is then deposited overlying gate dielectric layer 43 and partially removed to form gate conductive region 57. For example, the gate conductive region 57 comprises about 0.2 microns of doped or undoped polysilicon. If gate conductive region 57 is initially undoped, then this region is doped later during the formation of source region 33. In one embodiment, gate conductive region 57 is recessed below major surface 18. Control trench 158, gate dielectric layer 43, and gate conductive region 57 collectively form a control structure 157. In an alternative embodiment, control structure 157 is formed prior to forming charge compensation trenches 22. This alternative approach is used when the effect of the thermal budget on the doping characteristics of layers 221 and 222 is of concern. The configuration of doped regions 26 is conveniently flexible enough to provide either method sequence.

A photoresist layer (not shown) is then deposited and patterned to provide openings for forming source regions 33 adjacent control structures 157. Source regions 33 are then formed using, for example, a phosphorus or arsenic ion implantation and an annealing step. For example, arsenic implantation is used, of which 1.0 x 10¹⁵Atom/cm²To about 5.0X 10¹⁵Atom/cm²The dosage of (c) is sufficient. This dopant was activated using, for example, a rapid anneal at 1030 ℃ for 45 seconds. In this embodiment, source regions 33 are formed on both sides of control structure 157.

Next, an interlayer dielectric region 48 is formed covering the main surface 18. For example, the interlayer dielectric 48 comprises a deposited oxide and has a thickness on the order of about 1.0 micron. Contact openings 116 are then formed to cover and expose major surface 18 using conventional contact photoresist and etching methods, as shown in fig. 20. In a preferred embodiment, semiconductor layer 14 is removed using an anisotropic etchAdjacent to the source region 33 and the body region 31 and the portion above the compensation trenches 22. For example, sufficient material is removed from semiconductor layer 14 to extend to a depth of source region 33 or deeper. Another dopant is then added to the portion of the body surface 18 above the body region 31 and the compensation trenches 22 to form the body contact region 36. For example, using boron ion implantation, 1.0 × 10¹⁵Atom/cm²To about 5.0X 10¹⁵Atom/cm²The implantation dose of (a) is sufficient. The implanted dopants are then activated using, for example, a rapid anneal process. Portions of the inter-layer dielectric layer 48 are then removed along the sides to expose upper surface portions of the source regions 33 (shown in fig. 7). A source contact layer 63 is then formed overlying major surface 18 and in contact with source regions 33 and body regions 36, as shown in fig. 7. In one embodiment, source contact layer 63 comprises a titanium/titanium nitride barrier layer and an aluminum silicon alloy or the like formed overlying the barrier layer. A drain contact layer 13 is formed overlying the opposite surface of the semiconductor material 11 as shown in fig. 7 and comprises, for example, a solderable metal structure such as titanium-nickel-silver, chromium-nickel-gold, or the like. Alternatively, the layer 13 contains a conductive epoxy resin or the like.

In summary, the present invention describes a semiconductor device having a trench structure with a single crystal sealing plug, including a method of manufacture. The sealing plug provides, among other things, a lower pressure sealing configuration that also reduces the incorporation of contaminants in the core region of the groove. This provides a more reliable device. Furthermore, the slot structure reduces the effect of parasitic devices near the slot. The trench structure is suitable for many applications including, but not limited to, trench isolation structures and superjunction structures.

While the invention has been described and illustrated in terms of specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that changes and variations may be made without departing from the spirit of the invention. Accordingly, the present invention is intended to embrace all such alterations and modifications as fall within the scope of the appended claims.

Claims (10)

1. A semiconductor device, the device comprising:

a region of semiconductor material having a major surface;

a trench extending from the major surface into the region of semiconductor material, wherein the trench has an upper sidewall surface, a lower sidewall surface, and a lower surface;

a dielectric layer covering the lower sidewall surface and the lower surface of the trench; and

a monocrystalline semiconductor plug extending from an upper sidewall surface of the trench, wherein the monocrystalline semiconductor plug at least partially seals the trench and does not overlie a major surface of the dielectric layer.

2. The apparatus of claim 1, wherein the single crystal semiconductor plug completely seals the trench to provide a sealed core.

3. The apparatus of claim 1, further comprising at least two single crystal semiconductor layers formed overlying a surface of the trench, wherein the at least two single crystal semiconductor layers are interposed between the surface of the trench and the dielectric layer, and wherein the single crystal semiconductor plug extends from a surface of an outermost single crystal semiconductor layer.

4. The apparatus of claim 3, wherein the at least two single crystalline semiconductor layers have opposite conductivity types to provide a vertical charge compensation structure.

5. The apparatus of claim 4, wherein the region of semiconductor material and the innermost single crystal semiconductor layer comprise a first conductivity type, and wherein the outermost single crystal semiconductor layer comprises a second conductivity type opposite the first conductivity type, and wherein the apparatus further comprises:

a body region of the second conductivity type formed within a region of semiconductor material adjacent to a vertical charge compensation structure;

a source region having the first conductivity type formed within the body region; and

a control structure formed adjacent to the source and body regions, wherein the source region is interposed between the control structure and the vertical charge compensation structure.

6. A semiconductor device, the device comprising:

a semiconductor region having a main surface;

a trench formed within the semiconductor region extending from the major surface;

a vertical charge compensation structure formed overlying a surface of the trench, wherein the vertical charge compensation structure includes a first semiconductor layer of a first conductivity type abutting the semiconductor region; and a second semiconductor layer of a second conductivity type opposite to the first conductivity type adjoining the first semiconductor layer of the first conductivity type;

a dielectric layer formed covering the lower sidewall surface and the lower surface of the second semiconductor layer while leaving the upper sidewall portion of the second semiconductor layer exposed;

a single crystal semiconductor plug formed at an upper portion of the trench and extending from an upper sidewall portion of the second semiconductor layer;

a control structure formed within the semiconductor region, laterally spaced apart from the vertical charge compensation structure;

a body region contiguous and between the control structure and the vertical charge compensation structure, wherein the body region has the second conductivity type; and

a source region overlying a portion of the body region and abutting the control structure.

7. The apparatus of claim 6, wherein the single-crystal semiconductor plug includes the second conductivity type.

8. A method for forming a semiconductor device, the method comprising the steps of:

providing a region of semiconductor material having a major surface;

forming a groove extending from the major surface;

forming a first dielectric layer covering the surface of the groove;

forming a second dielectric layer overlying the first dielectric layer, wherein the first and second dielectric layers comprise different materials;

removing portions of the first dielectric layer along the upper portions of the trenches while using the second dielectric layer as a mask layer to provide exposed sidewall portions;

removing the second dielectric layer; and

forming a semiconductor plug extending from the exposed sidewall portion.

9. The method of claim 8, wherein said step of forming said semiconductor plug comprises the step of selectively growing an epitaxial single crystal semiconductor plug extending from exposed sidewall portions.

10. The method of claim 8, wherein the step of forming the semiconductor plug comprises forming a semiconductor plug of a conductivity type opposite to a conductivity type of the region of semiconductor material.