HK1144729B - Electronic device including a trench and a conductive structure therein and a process of forming the same - Google Patents

Description

Electronic device including a trench and a conductive structure within the trench and method of forming the same

Technical Field

The present disclosure relates to electronic devices and methods of forming electronic devices, and more particularly, to electronic devices including trenches and conductive structures within the trenches and methods of forming the same.

Background

A quasi-vertical diffused metal oxide semiconductor field effect (VDMOS) transistor is a particular type of power transistor. The VDMOS transistor has a source electrode located above a buried doped region (buried doped region) which functions as a drain region. Typically, many VDMOS transistors within an electronic device are connected in parallel to provide an effective channel length designed to support the current designed for the electronic device. The power transistor may include contacts on both sides of the chip. The maximum operating voltage may be limited by practical constraints. Many power transistors operate at a voltage difference between contacts (e.g., between source and drain contacts) that is no greater than 40V to 50V. Higher voltage differences can be used but the lateral dimensions of the power transistor are typically increased to avoid electric fields reaching levels that would cause undesired junction breakdown. Furthermore, increasing the lateral dimensions will result in a larger area consumed by the power transistor and thus increase the manufacturing cost of the device comprising the power transistor.

Drawings

Embodiments are illustrated by way of example and are not limited by the accompanying figures.

Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece including a doped region, a gate dielectric layer, and a gate electrode.

FIG. 2 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 1 after forming an insulating layer on exposed surfaces thereof.

FIG. 3 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 2 after planarizing an insulating layer and forming another insulating layer on the planarized surface.

FIG. 4 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 3 after forming a patterned resist layer over the insulating layer and removing a portion of the insulating layer under the opening in the patterned resist layer.

Fig. 5 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 4 after forming a trench extending through the semiconductor layer to the buried doped region.

Fig. 6 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 5 during a tilt angle ion implantation process.

Fig. 7 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 6 after activating dopants from ion implantation to form sidewall doped regions within the semiconductor layer.

FIG. 8 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 7 after forming an insulating layer that partially fills the trench.

Fig. 9 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 8 after forming a sidewall spacer (side spacer) and exposing a portion of the buried doped region.

Fig. 10 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 9 after forming a conductive layer that substantially fills the remaining portion of the trench.

Fig. 11 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 10 after removing a portion of the conductive layer located outside of the trench.

Fig. 12 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 11 after forming contact openings (contacts).

Fig. 13 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 12 after forming a conductive layer within the contact opening.

Fig. 14 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 13 after forming a substantially complete electronic device in accordance with the present invention.

Fig. 15 includes a diagram illustrating a top view of various exemplary interconnect arrangements (interconnect layout) that may be used with an electronic device.

Fig. 16 includes an illustration of a cross-sectional view of a portion of a workpiece including an alternative embodiment of a field insulating region adjacent a trench in accordance with the present invention.

Fig. 17 through 19 include illustrations of cross-sectional views of a portion of the workpiece of fig. 4 during trench formation and sidewall doping in accordance with an alternative embodiment.

Fig. 20 through 22 include graphs illustrating the effect of manufacturing parameters on source to drain breakdown voltage.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to improve understanding of embodiments of the present invention.

Detailed Description

The following description, taken in conjunction with the accompanying drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other teachings may of course be utilized in this application.

As used herein, the terms "comprises," "comprising," "includes," "including," "has," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly stated to the contrary, "or" refers to an inclusive-or, rather than an exclusive-or. For example, the condition a or the condition B satisfies any one of the following conditions: a is true (or present) and B is spurious (or absent), a is spurious (or absent) and B is true (or present), and both a and B are true (or present).

Also, the use of "a" or "an" is used to describe various elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. This description should be read to include one or at least one and the singular also includes the plural or vice versa unless it is otherwise clear. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, when more than one item is described, a single item may replace the more than one item.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and process steps are conventional and may be found in textbooks and other sources within the semiconductor and electronic arts.

Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece 600. The workpiece includes a substrate 602, the substrate 602 being lightly or heavily doped, n-type or p-type. For the purposes of this specification, "heavily doped" is intended to mean at least 10¹⁹Atom/cm³While "lightly doped" is intended to mean less than 10¹⁹Atom/cm³The peak dopant concentration of (a). In a particular embodiment, the substrate 602 may include a lightly doped portion overlying a heavily doped portion. The buried doped region 601 overlies the substrate 602. In an embodiment, the buried doped region 601 is heavily doped with an n-type dopant, such as phosphorus, arsenic, antimony, or any combination thereof. In particular embodiments, the buried doped region 601 includes arsenic or antimony if the diffusion of the buried doped region 601 is to be kept low, and in particular embodiments, the buried doped region 601 includes antimony to reduce the degree of outgassing (compared to arsenic) during the formation of the semiconductor layer 603.

The semiconductor layer 603 covers the buried doped region 601. The semiconductor layer 603 has the same conductivity type as the buried doped region 601, but is lightly doped. The semiconductor layer 603 may include a group 14 element (i.e., carbon, silicon, or germanium) and any of the dopants described with respect to the buried doped region 603. In a specific embodiment, semiconductor layer 603 is a lightly doped n-type epitaxial silicon layer having a thickness in the range of about 2 microns to about 15 microns and about 10¹⁵Atom/cm³To about 10¹⁷Atom/cm³Peak doping concentration range of (a).

Spaced well regions 611 are adjacent to the major surface 604 of semiconductor layer 603. Well regions 611 may also be referred to as body regions. Portions of well region 611 will be channel regions of subsequently formed field effect transistors. The well region 611 has an opposite conductivity type to the buried doped region 601 and the semiconductor layer 603. In a particular embodiment, each well region 611 has a depth in the range of about 0.2 microns to about 3 microns,and is doped by about 10¹⁶Atom/cm³To about 10¹⁸Atom/cm³Boron in the peak dopant concentration range.

The source region 609 and the well contact region 610 are adjacent to the main surface 604 of the semiconductor layer 603. The well contact region 610 allows formation of an ohmic contact to a subsequently formed metal-containing interconnect (not illustrated in fig. 1). The source region 609 has an opposite conductivity type to the well region 611, while the well contact region 610 has the same conductivity type as the well region 611. In a particular embodiment, each of the source region 609 and the well contact region 610 has a depth range of about 0.05 microns to about 0.5 microns and is heavily doped. The source region 609 may comprise any of the dopants described with respect to the buried doped region 601 and the well contact region may comprise boron.

A gate dielectric layer 605 covers the major surface 604 of the semiconductor layer 603 and a gate electrode 606 covers the gate dielectric layer 605. More specifically, the gate electrode 606 covers portions of the semiconductor layer 603, the well region 611, and the source region 609. The portion of the well region 611 located below the gate electrode 606 is the channel region of the field effect transistor. The gate dielectric layer may comprise an oxide, nitride, oxynitride or any combination thereof, and the gate electrode 606 comprises a conductive layer. The conductive layer may comprise a heavily doped semiconductor material, a metal-containing material, or any combination thereof. In a specific embodiment, the gate dielectric layer comprises silicon dioxide and has a thickness in the range of about 5nm to about 100nm, and the gate electrode 606 comprises heavily doped polysilicon and an overlying metal silicide and has a thickness in the range of about 50nm to about 500 nm. Sidewall spacers 608 are adjacent the sides of the gate electrode 606 and the gate dielectric layer 605. The sidewall spacers 608 may comprise an oxide, nitride, oxynitride, or any combination thereof.

Although many details regarding specific dopants, depths, thicknesses, and concentrations have been given with respect to the embodiment illustrated in fig. 1, such details are intended to describe possible non-limiting embodiments and are not intended to limit the scope of the invention.

As shown in fig. 2, an insulating layer 607 is formed over the gate electrode 606 and other portions of the workpiece. The insulating layer 607 may include an oxide, a nitride, an oxynitride, or any combination thereof. In a specific embodiment, the insulating layer 607 is formed by depositing a silicon dioxide layer having a thickness in the range of about 500nm to about 1500 nm.

As shown in fig. 3, the insulating layer 607 is flat, and another insulating layer 622 is formed over the insulating layer 607 after the planarization. Planarization allows subsequent lithographic operations, such as patterning a resist layer, to be performed more easily. Planarization may be performed using chemical mechanical polishing, resist-etch back (resist-etch back), or other similar techniques. The insulating layer 622 may include an oxide, a nitride, an oxynitride, or any combination thereof. The insulating layer 622 can be of a different composition than the insulating layer 607 such that the insulating layer 622 can serve as a polish stop, etch stop, anti-reflective layer, serve other useful purposes, or any combination thereof. In a specific embodiment, insulating layer 622 is formed by depositing silicon nitride to a thickness in the range of about 20nm to about 600 nm. Planarization of the insulating layer 607 and formation of the insulating layer 622 are optional; however, they help make the process more repeatable.

As shown in fig. 4, a resist layer 623 is applied over the insulating layer 622 and patterned to define an opening, such as opening 621, over the well contact region 610. The insulating layer, such as insulating layers 607 and 622, underlying the openings in resist 623 are removed to expose well contact regions 610.

Referring to fig. 5, the portions of the well contact region 610, the well region 611, and the semiconductor layer 603 under the opening in the resist layer 623 are removed to form a trench, which extends from the main surface 604 toward the buried doped region 601, as shown in fig. 5. Although fig. 5 illustrates only one slot 619, other slots (not shown) are present and substantially similar to slot 619. The width of trench 619 is wide enough to allow the depth of the doped regions subsequently formed along sidewalls 614 of trench 619 to be deeper than well region 611. The width of the trench 619 is not wide enough so that a subsequently formed conductive layer cannot fill the trench 619 after an insertion process (interleaving) is performed. In a particular embodiment, the width of each slot 619 is at least about 0.5 microns, while in another embodiment, the width of each slot 619 is no greater than about 4 microns or about 2 microns. After reading this specification, skilled artisans will appreciate that narrower or wider widths outside the specified dimensions may be used. The trench 619 may extend to the buried doped region 601; however, the slots 619 may be shallower if needed or desired.

The grooves are formed using anisotropic etching. In an embodiment, a timed etch may be performed, while in another embodiment, a combination of endpoint detection (e.g., detecting a dopant species in the buried doped region, such as arsenic or antimony) and a timed overetch may be employed.

The doped regions are formed along the sidewalls of the trenches. Referring to fig. 6, a doped region 620 is formed from a portion of the semiconductor layer 603 along the sidewalls 614 of the trench 619. The doped region 620 is formed by ion implanting dopants using a tilt angle implantation technique, which is depicted by arrows 624 in the embodiment shown in fig. 6. As used herein, the angle of implantation is measured from a plane substantially perpendicular to the major surface 604 (i.e., the vertical plane as shown in fig. 6). This angle is large enough to allow a sufficient amount of dopant to be implanted along the sidewalls 614 of the trench 619, and is small enough so that the doped region 620 is formed deeper into the semiconductor layer 603 than the well region 611. In embodiments, the angle of tilt angle implantation is at least about 8 ° or about 15 °, while in another embodiment, the angle of tilt angle implantation is no greater than about 50 ° or about 40 °. In a specific embodiment, the angle of tilt angle implantation ranges from about 20 ° to about 35 °. In embodiments where the implant species is B', the energy is at least about 50keV or about 90keV, and in other embodiments the energy is no greater than about 500keV or about 400 keV. In a specific embodiment, the energy ranges from about 200keV to about 250 keV. In embodiments, the dose is at least about 5 x 10¹¹Ion/cm²Or about 1X 10¹²Ion/cm²And in yet another embodiment, the dose is not greater than about 5X 10¹³Ion/cm²Or about 1X 10¹³Ion(s)/cm². In a specific embodiment, the dosage range is about 2X 10¹²Ion/cm²To about 5X 10¹²Ion/cm²。

After reading this description, the skilled person will understand that the thickness of the layer covering the main surface 604 of the semiconductor layer 603 may also influence the depth of the ion implantation, in addition to the angle. If the resist 623 is removed prior to ion implantation, the depth of ion implantation into the semiconductor layer 603 will be lower than the depth of implantation into the trench 619. During the ion implantation, a lower energy may be employed to reduce the likelihood of ions passing through the gate electrode 606 and affecting the doping concentration of the well region 611 and those portions of the semiconductor layer 603 near the major surface 604. Because lower energy ion implantation may be employed, subsequent thermal cycling may or may not need to be adjusted to achieve the desired doping profile and meet electrical performance criteria (e.g., an electric field profile that reduces the likelihood of premature junction breakdown). The skilled person will understand that thermal budget (thermal budget) with respect to other doped regions (e.g. well regions 611, source regions 609, etc.) will also be considered to ensure suitable electrical performance of the electronic device to be formed.

Many details regarding implantation parameters and related considerations are described. After reading this specification, skilled artisans will appreciate that values less than or greater than those described may be used in other specific applications. Thus, implant parameters different from those disclosed may be employed without departing from the scope of the invention. Other doping techniques may be employed and are described in the later sections of this specification.

If the resist layer 623 was not previously removed, it is removed and the dopants of the doped regions are activated to form sidewall doped regions, such as sidewall doped region 613 shown in FIG. 7. The dopants can be driven deeper into the semiconductor layer 603 if needed or desired. Dopant activation and optional dopant drive may occur by thermal cycling during subsequent processing or may be performed using separate thermal cycles. As with the embodiment shown in fig. 7, the combination of well regions 611 and sidewall doped regions 613 extend along a substantial portion of the sidewalls of trenches 619. In another embodiment, the sidewall doped region 613 may extend to the buried doped region 601. The sidewall doped regions 613 have the same conductivity type as the well regions 611 and may have any of the dopant concentrations previously described with respect to the well regions 611. The sidewall doped regions 613 may have the same or different dopant concentration as the well regions 611.

Note that along the sidewalls 614 of the trench 619, the dopant concentration within the sidewall doping region 613 has a substantially uniform concentration at each location where ions are implanted into the semiconductor layer 603. Thus, the dopant concentration within sidewall doped region 613 decreases with distance from sidewall 614, while the dopant concentration within well region 611 decreases with distance from major surface 604. The relatively more uniform dopant concentration of sidewall doped region 613 along the depth of trench 619 helps to increase the breakdown voltage between the source and drain of the power transistor to be formed. This benefit will be described in more detail in later sections of this specification.

Sidewall spacers are formed along the sidewalls of the trenches, such as the embodiments shown in fig. 8 and 9. An insulating layer 618 is formed over major surface 604 and along sidewalls 614 and the bottom of trench 619. Insulating layer 618 is sufficiently thick to substantially prevent premature breakdown between subsequently formed conductive structures that will be located within trenches 619 and either or both of sidewall doped region 613 and well region 611. The insulating layer 618 partially, but not completely, fills the trench 619. In a specific embodiment, insulating layer 618 has a thickness in the range of about 500nm to about 1500 nm. Insulating layer 618 includes an oxide, nitride, oxynitride, or any combination thereof. The insulating layer 618 may have a different composition than the insulating layer 622. In a specific embodiment, insulating layer 618 is formed by depositing silicon dioxide in a thickness range of about 300nm to 1500 nm. Insulating layer 618 is anisotropically etched to form sidewall spacers, such as sidewall spacers 628 in fig. 9. The insulating layer 622 helps to reduce over-etch or other etch damage to underlying features (e.g., the gate electrode 606) during the etch that forms the sidewall spacers 628. A portion 629 of the buried doped region 601 is exposed along the bottom of the trench 619.

As shown in fig. 10, a conductive layer 625 is formed over the main surface 604, sidewall spacers 628, and buried doped regions 601. Conductive layer 625 substantially fills the remainder of trench 619. The conductive layer 625 can include a metal-containing material or a semiconductor-containing material. In an embodiment, the conductive layer 625 includes a plurality of films, such as an adhesive film, a barrier film, and a conductive filler material. In particular embodiments, the adhesive film may include a refractory metal such as titanium, tantalum, or the like; the barrier film may include a refractory metal nitride such as titanium nitride, tantalum nitride, or the like, or a refractory metal semiconductor nitride such as TaSiN; and the conductive fill material may comprise tungsten. In a more specific embodiment, conductive layer 625 may comprise Ti/TiN/W. Each of the titanium film and the titanium nitride film may be physically vapor deposited (e.g., sputtered) to a thickness in the range of about 20nm to about 90nm, and the tungsten film may be chemically vapor deposited to a thickness in the range of about 50nm to about 500 nm. In another embodiment, the conductive layer 625 can include a heavily doped semiconductor material. The number of films and the composition of those films are selected based on electrical properties, temperature of subsequent thermal cycling, other criteria, or any combination thereof. The refractory metals and refractory metal-containing compounds can withstand high temperatures (e.g., the melting point of these materials can be at least 1400 ℃), can be deposited conformally, and have a low bulk resistivity than heavily doped n-type silicon. After reading this description, skilled artisans will be able to determine the composition of conductive layer 625 to meet their needs and desires for a particular application.

A portion of conductive layer 625 overlying major surface 604 is removed to form a conductive structure within a trench, such as conductive structure 635 within trench 619 as illustrated in the embodiment of fig. 11. The removal may be performed using chemical mechanical polishing or blanket etching (blanket etching technique). The insulating layer 622 can serve as a polish stop layer or an etch stop layer. Polishing or etching may continue for a relatively short period of time after the insulating layer 622 has reached a thickness, polishing or etching operation, or any combination thereof, relative to the conductive layer 625 to cause non-uniformity across the workpiece.

As shown in fig. 12, the contact opening 632 is formed to extend to the source region 609 and the well contact region 610. Other contact openings (not shown) may be formed in other portions of the electronic device (e.g., gate electrode 606), but are not illustrated in fig. 12. As shown in fig. 13, a conductive layer 626 is formed along the exposed surface of the workpiece and within the contact opening 632. Similar to the conductive layer 625 of the conductive structure 635, the conductive layer 625 may comprise a single film or multiple films. Conductive layer 625 has a bulk resistivity significantly lower than heavily doped n-type silicon. Exemplary materials include aluminum, tungsten, copper, gold, or the like. As shown in fig. 14, the conductive layer 625 can be patterned to form interconnects 626. A subsequent passivation layer 642 is formed over the interconnect 626 and other exposed portions of the workpiece to form a substantially complete electronic device. Fig. 15 includes an illustration of a top view of some exemplary, non-limiting arrangements of interconnects to the conductive structures and proximate source and well contact regions. After reading this description, the skilled person will understand that other designs of interconnects may be employed.

In another embodiment, an electronic device may include a field splitting region for use in conjunction with a power transistor. Referring to fig. 16, field separating region 701 is formed adjacent to major surface 604 and trench 619. With respect to the process flow, the field separating region may be formed after the well region 611 is formed and before the gate dielectric layer 605, the gate electrode 606, the source region 609, the well contact region 609 and the trench 619 are formed. During the etching to form the trenches 619, some of the insulating material within the field isolation regions 701 is removed before the semiconductor layer 603 is etched. The field separation region 701 may help reduce an electric field between the conductive structure 635 and either or both of the well region 611 and the well contact region 610.

In other embodiments, the trenches may be of different depths, different doping techniques may be employed, or a combination thereof. After forming the workpiece as shown in fig. 4, the semiconductor layer 603 may be etched, as shown in fig. 17, such that the grooves 819 extend only partially, rather than completely, into the semiconductor layerWithin the bulk layer 603 to the buried doped region 601. Next, the resist layer 623 may be removed. As shown in fig. 18, a gaseous or solid dopant source is used to dope exposed portions of the semiconductor layer 603 to form doped regions 813. Similar to the previously described embodiments, the doped region 813 may be formed using a tilted angle implantation of a dopant gas or a solid dopant source. If a p-type dopant is employed, the dopant gas may comprise diborane, a boron halide, or the like, while if an n-type dopant is employed, the dopant gas may comprise phosphine, phosphorus oxychloride, arsine, or the like. In another embodiment, the dopant gas may be degassed from a solid source, such as boron nitride, aluminum arsenate, NH₄H₂PO₄Antimony oxide or the like. Alternatively, a doped glass or doped semiconductor layer (e.g., a doped silicon layer) may be formed along the exposed portions of the trenches 819. Subsequent cycles activate and drive dopants into the semiconductor layer 603 to form sidewall doped regions. Similar to the ion implantation embodiment, a relatively uniform doping concentration may be obtained along the sidewalls of the trench, wherein the doping concentration decreases with distance from the sidewalls of the trench. After the doping cycle, the doped glass or doped semiconductor layer may or may not be removed before subsequent processing continues.

As shown in fig. 19, a portion of the semiconductor layer 603 may be doped by ion implantation to form a doped region 890, the doped region 890 extending between the bottoms of the trenches 819 to the buried doped region 601. The doped region 890 has the same conductivity as the buried doped region 601 and may be heavily doped. In a further embodiment, similar to the workpiece illustrated in fig. 7, another etching operation may be performed to extend the trench 819 until the buried doped region 601 is exposed. Theoretically, the trench does not extend all the way to the buried doped region 601; however, if a portion of the semiconductor layer 603 is located between the bottom of the trench and the doped buried layer 601, the breakdown voltage or other electrical properties will be compromised.

In further embodiments, the conductivity types of the buried doped region 601, the semiconductor layer 603, the source region 609, the well contact region 610, and the sidewall doped region 613 may be reversed. Dopant concentration and other parameters (thickness, junction depth, etc.) may be adjusted to obtain the desired or expected electrical properties.

In the above embodiments, the electronic device comprises a power transistor, and more particularly a VDMOS transistor. The electronic device may include other VDMOS transistors (not illustrated) that are different from or substantially the same as the VDMOS transistors illustrated in fig. 14. The VDMOS transistors may be electrically connected or otherwise connected in parallel to achieve a desired current flow through the electronic device.

Referring to fig. 14, sidewall doped regions 613 help to form a more uniform electric field along the sidewalls of the trenches when the transistor is in operation. The more uniform electric field allows for a higher breakdown voltage between the source and drain of the transistor (also referred to as BV)_DSS). The higher breakdown voltage allows the power transistor to operate at higher voltages. For example, BV of the power transistor shown in FIG. 14_DSSMay be about 120V, but if sidewall doped region 613 is not present, then BV of the power transistor_DSSPossibly about 70V. As such, the power transistor shown in fig. 14 may have an operating voltage of at least about 100V because the power transistor may operate at a voltage difference of at least about 100V between the source region 609 and the interconnect of the conductive structure 635. If sidewall doped region 613 is not present, it is not possible to obtain such a high voltage difference without creating breakdown. For the purposes of this specification, the operating voltage of a transistor is the highest design potential between any terminals (e.g., source, drain, and gate) of the transistor during normal operation of the transistor.

By introducing dopants into the semiconductor layer 603 along the sidewalls 620 of the trenches 619, as opposed to introducing dopants along the major surface 604 of the semiconductor layer 603, a dopant concentration profile of the sidewall doped regions 613 is obtained. If the dopants for the sidewall doped regions diffuse from the major surface 604 (similar to forming a deep collector), the long dopant drive cycle required to diffuse the dopants to the appropriate depth may adversely affect the dopant profile of previously doped portions of the workpiece, such as the well region 611 or the buried doped region 601. Also, diffusion may require significantly more lateral space, since diffusion will occur in almost all directions (lateral and vertical) within the semiconductor layer 603.

Thus, sidewall doped region 613, sidewall spacer 628, and conductive structure 635 according to an embodiment of the present invention allow for the formation of a relatively small power transistor, and also allow for operation at source to drain voltage differences of greater than 50V, and in a specific embodiment greater than 100V.

Fig. 20-22 illustrate how the breakdown voltage varies as each of the implantation dose of the doped region 620, the tilt angle, and the thickness of the sidewall spacer 628 near the bottom of the trench 619 varies. In the embodiment described with respect to fig. 20-22, semiconductor layer 603 has a thickness of about 8.5 microns. In the figure, Tw refers to the width of the trench 619 and oxide thickness refers to the thickness of the sidewall spacer 628 near the bottom of the trench 619. In general, higher BV is obtained when the width of the slots 619 is 4 microns wide, rather than 3 microns wide, and the other parameters remain the same_DSS. With respect to implant dose, higher doses may be employed as the width of the slots 619 becomes wider; however too much dose will significantly reduce BV_DSS. Similarly, with respect to the implant angle (also referred to as the tilt angle), higher angles may be employed as the width of the slots 619 becomes wider; however too large an angle may significantly reduce BV_DSS. BV when the thickness of sidewall spacer 628 becomes thicker_DSSAnd is increased. The thickness generally corresponds to the thickness of the insulating layer 618 formed. A thicker insulating layer 618 and, consequently, thicker sidewall spacers 628 are obtained at the expense of a reduced width of the conductive structures 635 or a wider trench 619. The reduced width of conductive structure 635 may increase the parasitic resistance through the power transistor, and the wider slot causes the power transistor to occupy a larger area. After reading this specification, skilled artisans will be able to determine specific parameter values that meet the needs or desires of a circuit designer for a particular electronic device.

Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, skilled artisans will appreciate that those aspects and embodiments are exemplary only and do not limit the scope of the invention.

In a first aspect, a method of forming an electronic device may comprise: a workpiece is provided that includes a first layer having a major surface, a well region adjacent the major surface, and a buried doped region spaced apart from the major surface and the well region. The method may further comprise: forming a trench extending toward a buried doped region, wherein a portion of the first layer is along a sidewall of the trench. The method may further comprise: portions of the first layer are doped along sidewalls of the trench to form a sidewall doped region, wherein dopants for the sidewall doped region are introduced into the first layer along the sidewalls of the trench. The method may still further comprise: a conductive structure within the trench is formed, wherein the conductive structure is electrically connected to the buried doped region and electrically insulated from the sidewall doped region.

In an embodiment of the first aspect, doping the portion of the first layer comprises performing a tilt angle implant. In another embodiment, doping the portion of the first layer includes ion implanting a dopant at an angle of at least about 8 °. In yet another embodiment, a dopant having a conductivity type opposite to that of the first layer is used to dope portions of the first layer along sidewalls of the trench.

In yet another embodiment of the first aspect, the method further comprises: prior to forming the conductive structure, insulative sidewall spacers are formed along the sidewalls of the trenches. In a specific embodiment, forming the conductive structure includes depositing a refractory metal-containing material overlying the major surface and substantially filling the remainder of the trench, and polishing the refractory metal-containing material to remove a portion of the refractory metal-containing material overlying the major surface. In another specific embodiment, a first insulating layer is formed over the major surface before the formation of the trench, and a second insulating layer is formed over the first insulating layer before the formation of the trench, wherein the second insulating layer has a different composition from the first insulating layer. In a more specific embodiment, the method further comprises: the first insulating layer is planarized before forming the second insulating layer.

In a further embodiment of the first aspect, the method further comprises: forming a source region within the well region and adjacent to the major surface, and forming a well contact region within the well region and adjacent to the major surface, wherein the well contact region has a higher peak dopant concentration than the well region; and forming a gate electrode overlying the well region and the first layer at the major surface. In specific embodiments, the method further comprises: a first interconnect, a second interconnect, and a third interconnect are formed, wherein the first interconnect is electrically connected to the source region, the second interconnect is electrically connected to the conductive structure, and the third interconnect is electrically connected to the gate electrode. In yet another embodiment, an electronic device includes a transistor including a first layer, a well region, a buried doped region, a sidewall doped region, and a conductive structure, and the transistor has an operating voltage of at least about 100V.

In a second aspect, a method of forming an electronic device may comprise: a workpiece is provided that includes a first layer having a major surface, a well region adjacent the major surface, a well contact region adjacent the major surface and within the well region and having a higher peak doping concentration than the well region, a source region adjacent the major surface and within the well region and having a higher peak doping concentration than the well region, a buried doped region spaced apart from the major surface and the well region, a gate electrode overlying the first layer and the well region, the first layer, the source region and the buried doped region having a first conductivity type, and the well region and the well contact region having a second conductivity type opposite the first conductivity type. The method may further comprise: a trench extending to the buried doped region is etched, wherein the well region and portions of the first layer are along sidewalls of the trench, and dopants are implanted into the first layer along the sidewalls of the trench. The method may further comprise: the method includes depositing an insulating layer into the trench, anisotropically etching the insulating layer to form sidewall spacers along sidewalls of the trench, depositing a conductive layer to fill remaining portions of the trench, and polishing the conductive layer to form a conductive structure, wherein the polishing removes a portion of the conductive layer overlying the source region and the gate electrode, and the sidewall spacers are located between the conductive structure and the sidewalls of the trench. The method may still further comprise: a first interconnect, a second interconnect, and a third interconnect are formed, wherein the first interconnect is electrically connected to the conductive structure, the second interconnect is electrically connected to the well contact region and the source region, and the third interconnect is electrically connected to the gate electrode.

In an embodiment of the second aspect, the electronic device includes a transistor including a first layer, a well region, a well contact region, a source region, a buried doped region, a gate electrode, a doped region along a sidewall of the trench and including a dopant, a sidewall spacer, a conductive structure, and first, second, and third interconnects, and the transistor is capable of operating at a voltage difference of at least about 100V between the first interconnect and the second interconnect. In another embodiment, the conductive structure comprises a refractory metal-containing composition.

In a third aspect, an electronic device can include a first layer having a major surface, a well region adjacent the major surface, and a buried doped region spaced apart from the major surface and the well region. The electronic device can further include a trench extending toward the buried doped region, wherein the trench has sidewalls, sidewall doped regions along the sidewalls of the trench, and a conductive structure within the trench, wherein the sidewall doped regions extend to a depth deeper than the well region, and wherein the conductive structure is electrically connected to the buried doped regions and electrically insulated from the sidewall doped regions. The first layer and the buried doped region have a first conductivity type, and the well region has a second conductivity type opposite the first conductivity type.

In an embodiment of the third aspect, the electronic device further comprises a well contact region adjacent to the main surface and located within the well region and having a higher peak doping concentration than the well region, a source region adjacent to the main surface and located within the well region and having a conductivity type opposite to the conductivity type of the well region and the well contact region, and a gate electrode overlying the well region and the first layer at the main surface. In a particular embodiment, the electronic device further includes a first interconnect, a second interconnect, and a third interconnect, wherein the first interconnect is electrically connected to the conductive structure, the second interconnect is electrically connected to the source region, and the third interconnect is electrically connected to the gate electrode.

In another embodiment of the third aspect, the electronic device includes a transistor, the transistor including the first layer, the well region, the buried doped region, the sidewall doped region, and the conductive structure, and the transistor having an operating voltage of at least about 100V. In yet another embodiment, wherein the sidewall doped region has a substantially uniform doping concentration and doping profile along the sidewalls of the trench for a majority of the sidewall doped region, wherein the doping concentration of the sidewall doped region decreases with distance from the sidewalls of the trench. In a further embodiment, the combination of well region and sidewall doped region extends along a majority of the sidewalls of the trench. In yet a further embodiment, the electronic device further comprises a sidewall spacer comprising an insulating material, wherein the sidewall spacer is located between the conductive structure and each of the well region and the sidewall doped region.

It is noted that not all of the activities described in the foregoing summary or embodiments are required, that a portion of a particular activity may not be required, and that one or more additional activities may be performed in addition to those described. Further, the order in which activities are listed are not necessarily the order in which they are performed.

Certain features that are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Moreover, reference to values expressed as ranges includes each and every value within that range.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. The benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced, however, are not to be construed as a critical, required, or essential feature or feature of any or all the claims.

It is to be understood that certain features that are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Moreover, reference to values expressed as ranges includes each and every value within that range.

The illustrations and descriptions of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. This description and illustration is not intended to be an exhaustive or comprehensive description of all the elements and features of apparatus and systems that utilize the structures or methods described herein. Different embodiments may also be provided in combination in a single embodiment, but rather, different features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Moreover, reference to values expressed as ranges includes each and every value within that range. Many other embodiments will be apparent to the skilled person only after reading this specification. Other embodiments may be utilized and derived from the disclosure, such that structural substitutions, logical substitutions, or other changes may be made without departing from the scope of the disclosure. Accordingly, this disclosure is to be considered as illustrative and not restrictive.

Claims (10)

1. A method of forming an electronic device comprising the steps of:

providing a workpiece comprising a first layer, a well region, a gate electrode, and a buried doped region, wherein:

the first layer has a major surface;

the well region is adjacent to the major surface;

the gate electrode is disposed on the main surface, and

the buried doped region is spaced apart from the major surface and the well region;

forming a trench extending toward the buried doped region, wherein a portion of the first layer is located along a sidewall of the trench;

doping the portion of the first layer along the sidewalls of the trench to form a sidewall doped region, wherein dopants for the sidewall doped region are introduced into the first layer along the sidewalls of the trench; and

forming a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and electrically insulated from the sidewall doped region.

2. The method of claim 1, wherein the step of doping the portion of the first layer comprises: a tilt angle implant is performed.

3. The method of claim 1, further comprising the steps of: forming insulating sidewall spacers along the sidewalls of the trench prior to forming the conductive structure.

4. The method of claim 3, wherein the step of forming a conductive structure comprises:

depositing a refractory metal-containing material overlying the major surface and filling the remainder of the trench; and

polishing the refractory metal-containing material to remove a portion of the refractory metal-containing material overlying the major surface.

5. A method of forming an electronic device, comprising:

providing a workpiece comprising a first layer, a well region, a well contact region, a source region, a buried doped region, and a gate electrode, wherein:

the first layer has a major surface;

the well region is adjacent to the major surface;

the well contact region is adjacent to the major surface and within the well region and has a higher peak doping concentration than the well region;

the source region is adjacent to the major surface and within the well region and has a higher peak doping concentration than the well region;

the buried doped region is spaced apart from the major surface and the well region;

the gate electrode covers the first layer and the well region;

the first layer, the source region and the buried doped region have a first conductivity type; and is

The well region and the well contact region have a second conductivity type opposite the first conductivity type;

etching a trench extending to the buried doped region, wherein the well region and portions of the first layer are located along sidewalls of the trench;

implanting dopants into the first layer along the sidewalls of the trench;

depositing an insulating layer into the trench;

anisotropically etching the insulating layer to form sidewall spacers along the sidewalls of the trench;

depositing a conductive layer to fill the remaining portion of the trench;

polishing the conductive layer to form a conductive structure, wherein:

the step of polishing removes a portion of the conductive layer that covers the source region and the gate electrode; and is

The sidewall spacer is located between the conductive structure and the sidewall of the trench; and

forming a first interconnect, a second interconnect, and a third interconnect, wherein:

the first interconnect is electrically connected to the conductive structure;

the second interconnect is electrically connected to the well contact region and the source region; and is

The third interconnect is electrically connected to the gate electrode.

6. A transistor, comprising:

a first layer having a major surface;

a well region adjacent to the major surface;

a gate electrode disposed on the major surface;

a buried doped region spaced apart from the major surface and the well region;

a trench extending toward the buried doped region, wherein the trench has sidewalls;

a sidewall doped region along the sidewalls of the trench, wherein the sidewall doped region extends to a depth deeper than the well region; and

a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and electrically insulated from the sidewall doped region, wherein:

the first layer and the buried doped region have a first conductivity type; and is

The well region has a second conductivity type opposite the first conductivity type.

7. The transistor of claim 6, further comprising:

a well contact region adjacent the major surface and within the well region and having a higher peak doping concentration than the well region;

a source region adjacent the major surface and within the well region and having an opposite conductivity type from the well region and the well contact region; and

a gate electrode overlying the well region and the first layer at the major surface.

8. The transistor of claim 6, wherein:

the transistor comprises the first layer, the well region, the buried doped region, the sidewall doped region and the conductive structure; and is

The transistor has an operating voltage of at least 100V.

9. The transistor of claim 6, wherein the sidewall doped region has a uniform doping concentration along the sidewalls of the trench and has a doping profile in which the doping concentration of the sidewall doped region decreases with increasing distance from the sidewalls of the trench.

10. The transistor of claim 6 wherein a combination of the well region and the sidewall doped region extend along the sidewalls of the trench.