HK1144731B - Electronic device including a trench and a conductive structure therein - Google Patents

Description

Electronic device comprising a trench and a conductive structure within the trench

Technical Field

The present disclosure relates to electronic devices and methods of forming electronic devices, and more particularly, to electronic devices including trenches and conductive structures within the trenches and methods of forming the same.

Background

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are one common type of power conversion device. A MOSFET includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure disposed adjacent to the channel region. The gate structure includes a gate electrode layer disposed adjacent to the channel region and separated from the channel region by a thin dielectric layer.

When the MOSFET is in an on-state, a voltage is applied to the gate structure to form a conductive channel region between the source and drain regions, which allows current to flow through the device. In the closed state, any voltage applied to the gate structure is low enough that a conductive channel cannot form and thus current cannot occur. During the closed state, the device must support a high voltage between the source and drain regions.

In optimizing the performance of a MOSFET, designers are often faced with tradeoffs in device parametric performance. Specifically, the selection of available device structures or fabrication methods may increase one device parameter, but at the same time, such selection may decrease one or more other device parameters. For example, increasing the resistance (R) of a MOSFET_DSON) Can be usedCan reduce the Breakdown Voltage (BV)_DSS) And increases the parasitic capacitance between regions within the MOSFET.

Drawings

The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings.

Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece including an underlying doped region (underlying doped region), a semiconductor layer, a pad layer (pad layer), and a stopping layer (stopping layer).

FIG. 2 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 1 after forming a trench extending through the semiconductor layer to an underlying doped region.

FIG. 3 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 2 after forming a conductive layer that substantially fills the trench.

Fig. 4 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 3 after removing a portion of the conductive layer located outside of the trench, and after forming sidewall doped regions.

FIG. 5 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 4 after removal of the stop layer.

FIG. 6 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 5 after forming a plurality of layers over a semiconductor layer.

FIG. 7 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 6 after forming surface doped regions and openings extending through the plurality of layers.

FIG. 8 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 7 after forming insulating sidewall spacers (sidespacers).

Fig. 9 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 8 after forming a conductive layer overlying an exposed surface of the workpiece and forming a well region within a semiconductor layer.

FIG. 10 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 9 after forming a remaining portion of the conductive layer over an exposed surface of the workpiece.

FIG. 11 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 10 after forming a gate electrode.

FIG. 12 includes an illustration of a cross-sectional view of a portion of the workpiece of FIG. 11 after removal of the uppermost insulating layer, truncation of the insulating sidewall spacers, and filling of the gap between the gate electrode and the conductive layer with a conductive fill material.

Fig. 13 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 12 after forming openings through an interlayer dielectric layer (interlayer dielectric layer) and source regions, and after forming well contact regions.

Fig. 14 includes an illustration of a cross-sectional view of a portion of the workpiece of fig. 13 after forming a substantially complete electronic device in accordance with an embodiment of the invention.

Fig. 15-17 include illustrations of cross-sectional views of a portion of the workpiece of fig. 1 in which a conductive structure is formed within the trench, wherein the conductive structure includes an elevated portion overlying the major surface of the semiconductor substrate.

Fig. 18 includes an illustration of a cross-sectional view of a portion of a workpiece in which an electronic device includes a power transistor having a compensation region located below a horizontally-oriented doped region.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.

Detailed Description

The following description, taken in conjunction with the accompanying drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings and should not be construed as limiting the scope or applicability of the teachings. However, other teachings may of course be utilized in this application.

As used herein, the terms "horizontally oriented" and "vertically oriented" with respect to a region or structure refer to the primary direction in which current passes through such region or structure. More specifically, current may flow through a region or structure in a vertical direction, a horizontal direction, or a combination of a vertical direction and a horizontal direction. If current flows through a region or structure in a vertical direction or a combination of directions in which the vertical component is greater than the horizontal component, such region or structure will be referred to as vertically oriented. Similarly, if current flows through a region or structure in a horizontal direction or a combination of directions in which the horizontal component is greater than the vertical component, such region or structure will be referred to as being horizontally oriented.

The terms "normal operation" and "normal operating state" refer to conditions under which an electronic component or device is designed to operate. The conditions may be derived from a spreadsheet or other data sheet relating to voltage, current, capacitance, resistance, or other electrical conditions. Thus, normal operation does not include operating an electronic component or device beyond its design limits.

The terms "comprising," "including," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly stated to the contrary, "or" refers to an inclusive-or, rather than an exclusive-or. For example, the condition a or the condition B satisfies any one of the following conditions: a is true (or present) and B is spurious (or absent), a is spurious (or absent) and B is true (or present), and both a and B are true (or present).

Also, the use of "a" or "an" is used to describe various elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. This description should be read to include one or at least one and the singular also includes the plural or vice versa unless clearly indicated otherwise. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, when more than one item is described herein, a single item may replace the more than one item.

The family numbers corresponding to columns in the periodic Table of elements use a "New notation" protocol, such as CRCHandbook of Chemistry and Physics, 81^stEdition (2000-.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and process steps are conventional and may be found in textbooks and other sources within the semiconductor and electronic arts.

Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece 100. The workpiece 100 includes an underlying doped region 102, the doped region 102 being lightly or heavily doped, n-type or p-type. For the purposes of this specification, heavily doped is intended to mean at least 10¹⁹Atom/cm³While the expectation of light doping means less than 10¹⁹Atom/cm³The peak dopant concentration of (a). The underlying doped region 102 may be a portion of a heavily doped substrate (e.g., a heavily n-doped sheet) or may be an embedded doped region overlying a substrate of the opposite conductivity type or an embedded insulating layer (not shown) located between the substrate and the embedded doped region. In the concrete examplesIn an embodiment, the underlying doped region 102 may include a lightly doped portion overlying a heavily doped portion, for example, when the overlying semiconductor layer 104 is of an opposite conductivity type, to help increase junction breakdown voltage (junction breakdown). In an embodiment, the underlying doped region 102 is heavily doped with an n-type dopant, such as phosphorus, arsenic, antimony, or any combination thereof. In a particular embodiment, the underlying doped region 102 includes arsenic or antimony if the diffusion of the underlying doped region 102 is to be kept low, and in a particular embodiment, the underlying doped region 102 includes antimony to reduce the degree of outgassing (compared to arsenic) during formation of the semiconductor layer 104.

In the embodiment illustrated in fig. 1, the semiconductor layer 104 overlies the underlying doped region 102. The semiconductor layer 104 has a major surface 105. The semiconductor layer 104 may include a group 14 element (i.e., carbon, silicon, germanium, or any combination thereof) and any of the dopants described with respect to the doped region 102 below or dopants of the opposite conductivity type. In an embodiment, the semiconductor layer 104 is a lightly doped n-type or p-type epitaxial silicon layer having a thickness ranging from about 0.5 microns to about 5.0 microns with a doping concentration no greater than about 10¹⁶Atom/cm³And, in another embodiment, the doping concentration is at least about 10¹⁴Atom/cm³。

The pad layer 106 and the stop layer 108 (e.g., a polish stop layer or an etch stop layer) are formed on the semiconductor layer 104 using thermal growth techniques, deposition techniques, or a combination thereof. Each of the pad layer 106 and the stop layer 108 may comprise an oxide, a nitride, an oxynitride, or any combination thereof. In an embodiment, the pad layer 106 has a different composition than the stop layer 108. In a specific embodiment, the pad layer 106 comprises an oxide and the stop layer 108 comprises a nitride.

Referring to fig. 2, portions of the semiconductor layer 104, the pad layer 106, and the stop layer 108 are removed to form a trench, such as trench 202, that extends from the major surface 105 toward the underlying doped region 102. The slot 202 may be a single slot with different portions as shown in fig. 2, or the slot 202 may include a plurality of different slots. The width of the groove 202 is not so wide that a subsequently formed conductive layer cannot fill the groove 202. In particular embodiments, the width of each groove 202 is at least about 0.3 microns or about 0.5 microns, and in another particular embodiment, the width of each groove 202 is no greater than about 4 microns or about 2 microns. After reading this specification, skilled artisans will appreciate that narrower or wider widths outside the specified dimensions may be used. The trench 202 may extend to the underlying doped region 102; however, the groove 202 may be shallower if needed or desired.

The grooves are formed using anisotropic etching. In an embodiment, a timed etch may be performed, while in another embodiment, a combination of endpoint detection (e.g., detection of a dopant species, such as arsenic or antimony, in the underlying doped region 102) and a timed over-etch may be employed.

If needed or desired, dopants can be introduced into a portion of the semiconductor layer 104 along the sidewalls 204 of the trench 202 to form heavily doped sidewall doping regions (not illustrated in fig. 2). Tilt angle implantation techniques, dopant gases, or solid dopant sources may be used.

As shown in fig. 3, a conductive layer 302 is formed on the stop layer 108 and within the trench 202. The conductive layer 302 substantially fills the slot 202. The conductive layer 302 may include a metal-containing or semiconductor-containing material. In an embodiment, the conductive layer 302 may include a heavily doped semiconductor material, such as amorphous silicon or polysilicon. In another embodiment, the conductive layer 302 includes a plurality of films, such as an adhesive film, a barrier film, and a conductive filler material. In particular embodiments, the tacking film may include a high temperature resistant metal, such as titanium, tantalum, or the like; the barrier film may include a high temperature resistant metal nitride such as titanium nitride, tantalum nitride, or the like, or a high temperature resistant metal semiconductor nitride such as TaSiN; and the conductive fill material may comprise tungsten. In a more specific embodiment, conductive layer 302 may comprise Ti/TiN/W. The number of films and the composition of those films are selected based on electrical properties, temperature of subsequent thermal cycling, other criteria, or any combination thereof. Refractory metals and refractory metal-containing compounds can withstand high temperatures (e.g., these materials may have a melting point of at least 1400C), can be conformally deposited, and have a low bulk resistivity compared to heavily doped n-type silicon. After reading this specification, skilled artisans will be able to determine the composition of the conductive layer 302 to meet their needs or desires for a particular application.

The portion of the conductive layer 302 overlying the stop layer 108 is removed to form a conductive structure within the trench, such as conductive structure 402 within the trench 202, as shown in the embodiment of fig. 4. The removal may be performed using chemical mechanical polishing or blanket etching (blanket etchingtechnique). The stop layer 108 may function as a polish stop layer or an etch stop layer. Polishing or etching may continue for a relatively short period of time after the stop layer 108 reaches a thickness relative to the conductive layer 302, a polishing or etching operation, or any combination thereof to cause non-uniformity across the workpiece.

Before, during, or after forming the conductive structure, a sidewall doped region, such as sidewall doped region 404, may be formed from a portion of semiconductor layer 104 and extend from sidewall 204. Dopants may be introduced in the doping operation described above and become activated when the conductive layer 302 is formed. Alternatively, when the conductive layer 302 includes a doped semiconductor material, the dopant can diffuse from the conductive structure 402 or from the conductive layer 302 (before the conductive structure 402 is completely formed). The conductive structure 402 and the sidewall doped region 404, if present, form a vertically oriented conductive region. When in the form of a fabricated electronic device, the primary charge carriers (e.g., electrons) or current flow through conductive structure 402 is primarily in a vertical direction (substantially perpendicular to major surface 105), as opposed to a horizontal direction (substantially parallel to major surface 105).

In fig. 5, the stop layer 108 is removed and portions of the semiconductor layer 104 proximate the major surface 105 and the sidewall doped regions, such as sidewall doped region 404, are doped to form horizontally oriented doped regions, such as surface doped region 504, which are spaced apart from the underlying doped region 102. The surface doped regions 504 have the same conductivity type as the sidewall doped regions 404 and the underlying doped region 102. Under normal operating conditions, a primary load is applied through the surface doped region 504The daughter (e.g., electrons) or current will be in the horizontal direction. Thus, the surface doped region 504 may be a horizontally-oriented doped region. The surface doped regions 504 have a depth in the range of about 0.1 microns to about 0.5 microns and extend from the sidewall doped regions 404 of the vertically oriented conductive structures in the range of about 0.2 microns to about 2.0 microns. The lateral dimension (from the vertically oriented conductive structure) may depend on the voltage difference between the source and drain of the formed power transistor. As the voltage difference between the source and drain of the transistor increases, the lateral dimensions may also increase. In an embodiment, the voltage difference is no greater than about 30V, and in another embodiment, the voltage difference is no greater than about 20V. The peak doping concentration in the horizontally oriented doped region may be about 2 x 10¹⁷Atom/cm³To about 2X 10¹⁸Atom/cm³And, in particular embodiments, at about 4 × 10¹⁷Atom/cm³To about 7X 10¹⁷Atom/cm³The range of (1). The pad layer 106 may remain on the semiconductor layer 104 after the surface doped region 504 is formed or may be removed after the surface doped region 504 is formed.

In fig. 6, a set of layers is formed over the semiconductor layer 104 and the conductive structure 402. In an embodiment, insulating layer 602, conductive layer 604, insulating layer 606, insulating layer 622, conductive layer 624, and insulating layer 626 may be deposited sequentially. Each of the insulating layers 602, 606, 622, and 626 can include an oxide, a nitride, an oxynitride, or any combination thereof.

Each conductive layer 604 and 624 comprises a conductive material, or can be made conductive, for example by doping. Each conductive layer 604 and 624 can comprise a doped semiconductor material (e.g., heavily doped amorphous silicon, polysilicon, etc.), a metal-containing material (refractory metal, refractory metal nitride, refractory metal silicide, etc.), or any combination thereof. The thickness of conductive layer 604 ranges from about 0.05 to 0.5 microns, while the thickness of conductive layer 624 ranges from about 0.1 to 0.9 microns. In a specific embodiment, conductive layer 604 is a conductive electrode layer used to form a conductive electrode, and conductive layer 624 is a gate signal layer. The importance of such a layer is described later in this specification. The conductive layer 624 may be etched or otherwise patterned at this time to form gate signal lines, or may be etched or otherwise patterned at a later time in the process flow. Similarly, the conductive layer 624 may be etched or otherwise patterned at this point to form conductive electrodes, or may be patterned at a later time in the process flow.

In another specific embodiment, insulating layers 602 and 606 comprise nitride, each of which may have a thickness in the range of about 0.05 microns to about 0.2 microns. The insulating layers 622 and 626 comprise an oxide, the thickness of the insulating layer 622 can range from about 0.2 microns to about 0.9 microns, and the thickness of the insulating layer 626 can range from about 0.05 microns to about 0.2 microns. An anti-reflective layer may be incorporated into either the insulating layer or the conductive layer, or an anti-reflective layer (not shown) may be separately used. In other embodiments, more or fewer layers may be used, and the thicknesses described herein are merely exemplary and are not meant to limit the scope of the invention.

As shown in fig. 7, openings, such as opening 702, are formed through layers 602, 604, 606, 622, 624, and 626. The opening is formed such that a portion of the surface doped region 504 is located below the opening 702. This portion allows portions of the surface doped region 504 to underlie portions of subsequently formed gate electrodes. Insulative spacers, such as insulative spacer 802, are formed along the sides of an opening, such as opening 702 of fig. 8. The insulating spacers electrically insulate the conductive layer 604 from subsequently formed gate electrodes. The insulating spacers 802 may comprise an oxide, a nitride, an oxynitride, or any combination thereof, and the bottom of the insulating spacers 802 have a width in the range of about 50nm to about 200 nm.

Fig. 9 includes an illustration of the workpiece after forming a gate dielectric layer 902, a conductive layer 906, and a well region 904. The pad layer 106 is removed by etching, and a gate dielectric layer 902 is formed on the semiconductor layer 104. In a specific embodiment, the gate dielectric layer 902 comprises an oxide, a nitride, an oxynitride, or any combination thereof, and has a thickness ranging from about 5nm to about 100nm, and the conductive layer 906 overlies the gate dielectric layer 902. Conductive layer 906 may be part of a subsequently formed gate electrode. The conductive layer 906 may be conductive when deposited, or may be deposited as a high resistance layer (e.g., undoped polysilicon) and subsequently made conductive. The conductive layer 906 may include a metal-containing material or a semiconductor-containing material. The thickness of conductive layer 906 is selected such that, from a top view, the generally vertical edge of conductive layer 906 exposed within opening 702 is proximate to the edge of surface doped region 504. In an embodiment, conductive layer 906 is deposited to a thickness of about 0.1 microns to about 0.15 microns.

After forming conductive layer 906, semiconductor layer 104 can be doped to form a well region, such as well region 904 of fig. 9. The conductivity type of the well region 904 is opposite to the conductivity type of the surface doped region 504 and the underlying doped region 102. In an embodiment, boron dopants are introduced into semiconductor layer 104 through opening 702, conductive layer 906, and gate dielectric layer 902 to provide p-type dopants to well region 904. In one embodiment, the depth of well region 904 is deeper than the depth of the subsequently formed source regions, and in another embodiment, the depth of well region 904 is at least about 0.5 microns. In a further embodiment, the depth of the well region 904 is no greater than about 2.0 microns, and in yet another embodiment, the depth of the well region 904 is no greater than about 1.5 microns. By way of example, the well region 904 may be formed using two or more ion implantations. In a specific example, about 1.0X 10 is used¹³Atom/cm³Each ion implantation is performed with two implants having energies of about 25KeV and 50 KeV. In another embodiment, more or less ion implantations are performed in forming the well region. Different doses may be used at different energies, higher or lower doses may be used, higher or lower energies, or combinations thereof to meet the needs or desires of a particular application.

As shown in fig. 10, additional conductive material is deposited onto conductive layer 906 to form conductive layer 1006. The gate electrode will be formed of conductive layer 1006 and, thus, in the illustrated embodiment, the conductive layer is a gate dielectric layer. Conductive layer 1006 may comprise any of the materials previously described with respect to conductive layer 906. Similar to conductive layer 906, the additional conductive material can be conductive as deposited, or can be deposited as a high impedance layer (e.g., undoped polysilicon) and subsequently made conductive. Between the conductive layer 906 and the additional conductive material, they may have the same composition or different compositions. The thickness of conductive layer 1006, including conductive layer 906 and the additional conductive material, has a thickness in the range of about 0.2 microns to 0.5 microns. In particular embodiments, the additional conductive material comprises polysilicon and may be doped with an n-type dopant during deposition or subsequent doping using ion implantation or other doping techniques.

Conductive layer 1006 is anisotropically etched to form a gate electrode, such as gate electrode 1106 of fig. 11. In the illustrated embodiment, the gate electrode 1106 is formed without using a mask and has the shape of a sidewall spacer. Etching of the gate electrode 1106 may be performed such that the insulating layer 626 and the gate dielectric layer 902 may be exposed. The etch may extend to expose a portion of the insulating sidewall spacers 802. In the embodiment shown in fig. 11, a portion of the conductive electrode 604 is adjacent to the gate electrode 1106, with the insulating sidewall spacer 802 located between the conductive electrode 604 and the gate electrode 1106. The conductive electrode 604 has a pair of opposing surfaces, one of which is closer to the major surface 105 and the other opposing surface is farther from the major surface 105. Each of the opposing surfaces of the conductive electrode 604 is located at a height between the lowermost and uppermost points of the gate electrode 1106 within the area occupied by the transistor. An insulating layer (not shown) may be thermally grown from the gate electrode 1106 or may be deposited over the workpiece. The thickness of the insulating layer may be in the range of about 10nm to about 30 nm.

Fig. 12 includes an illustration of the workpiece after forming a conductive electrode 1262, a gate signal line 1264, truncated insulating sidewall spacers 1202, a source region 1204, and a conductive fill material 1206 between the gate signal line 1264 and a gate electrode 1106. Although the operations performed to form the workpiece are described in a particular order, upon reading this specification, the skilled artisan will understand that the order can be altered, if needed or desired. In order to complete the workpiece according to the embodiment shown in fig. 12, a mask or a plurality of masks (not shown) may be used.

If conductive layers 604 and 624 are not already patterned, they can be patterned to form conductive electrodes and gate signal lines, such as conductive electrode 1262 and gate signal line 1264. Conductive electrode 1262 may be used to help reduce capacitive coupling between the vertically oriented conductive region (the combination of conductive structure 402 and sidewall doped region 404) and any one or more of gate signal line 1264, gate electrode 1106, or gate signal line 1264 and gate electrode 1106. Gate signal lines 1264 may be used to provide signals from control electronics (not shown) to the gate electrodes 1106. Within the area occupied by the transistors, gate signal lines 1264 overlie conductive electrodes 1262. In an embodiment, gate signal line 1264 overlies substantially all of conductive electrode 1262 within a transistor, while in another embodiment, gate signal line 1264 overlies only a portion, but not all, of conductive electrode 1262 within a transistor.

Source regions, such as source region 1204, can be formed using ion implantation. The source regions 1204 are heavily doped and of opposite conductivity type compared to the well region 904, and of the same conductivity type as the surface doped region 504 and the underlying doped region 102. The portion of well region 904 between source region 1204 and surface doped region 504 and under gate electrode 1106 is a channel region 1222 for the power transistor being formed.

The insulating sidewall spacers 802 may be truncated by etching an upper portion of the sidewall spacers 802 to remove a portion of the insulating sidewall spacers 802 between the conductive layer 624 (gate signal layer) and the gate electrode 1106 to form truncated insulating sidewall spacers 1202. The amount of insulating spacers 802 removed is at least sufficient to allow the conductive fill material 1206, when formed, to electrically connect the conductive layer 624 and the gate electrode 1106, but not etch as much of the insulating sidewall spacers 802 to expose the conductive layer 604 (conductive electrode layer) because the gate electrode 1106 and the conductive layer 624 would be electrically connected to the conductive layer 604, which is undesirable. As in the illustrated embodiment, the etching is performed such that the uppermost surface of truncated insulating sidewall spacer 1202 is located near the interface between insulating layer 622 and conductive layer 624.

A conductive fill material 1206 is formed over the truncated insulating spacers 1202 to electrically connect the gate electrode 1106 to the conductive layer 624. Conductive fill material 1206 may be selectively grown or deposited over substantially all of the workpiece and subsequently removed from areas outside the gap between gate electrode 1106 and gate signal line 1264. The exposed portions of insulating layer 626 and gate dielectric layer 902 are removed if needed or desired.

Fig. 13 includes an illustration of the workpiece after formation and patterning of an interlayer dielectric (ILD) layer 1302 to define contact openings, and after doping to form well contact regions. The ILD layer 1302 may comprise an oxide, a nitride, an oxynitride, or any combination thereof. The ILD layer 1302 may comprise a single film or a plurality of discrete films having a substantially constant or variable composition (e.g., high phosphorous content farther from the semiconductor layer 104). An etch stop layer, antireflective layer, or combination may be used in or on the ILD interlayer 1302 to aid in processing. The ILD layer 1302 may be planarized to improve process margins during subsequent processing operations (e.g., lithography, subsequent polishing, or the like). A resistive layer 1304 is formed on the ILD layer 1302 and patterned to define resistive layer openings. An anisotropic etch is performed to define contact openings, such as contact openings 1322, that extend through ILD layer 1302. Unlike many conventional contact etch operations, the etch continues to extend through the source region 1204 and end within the well region 904. The etching may be performed as a timed etch or as an end point detection etch with a timed over etch. In a specific embodiment, the first endpoint may be detected when the source region 1204 is exposed, while the second endpoint may be detected by the presence of boron within the well region 904. A well contact region, such as well contact region 1324, may be formed by doping a bottom portion of a contact opening, such as contact opening 1322. Well contact regions 1324 may be implanted with dopants of the same conductivity type as the well region 904 in which they are located. The well contact region 1324 is heavily doped so that an ohmic contact may be subsequently formed. When the resistive layer 1304 is in place, an isotropic etch may be performed to expose the source regions, such as the uppermost surface of the source regions 1204, as becomes more apparent with respect to the description of fig. 14. At this point in the process, a power transistor, such as the one shown in fig. 13, will be formed.

Fig. 14 includes an illustration of a substantially completed electronic device, including conductive plugs and terminals. More specifically, the conductive layer is formed along exposed surfaces of the workpiece and within contact openings, including contact opening 1322. The conductive layer may comprise a single film or multiple films. In an embodiment, the conductive layer includes a plurality of films, such as an adhesive film, a barrier film, and a conductive filler material. In particular embodiments, the adhesive film may include a high temperature resistant metal, such as titanium, tantalum, or the like; the barrier film may include a high temperature resistant metal nitride such as titanium nitride, tantalum nitride, or the like, or a high temperature resistant metal semiconductor nitride such as TaSiN; and the conductive fill material may comprise tungsten. The number of films and the composition of these films are selected based on electrical properties, subsequent thermal cycling temperatures, other criteria, or any combination thereof. Refractory metals and refractory metal-containing compounds can withstand high temperatures (e.g., such materials can have a melting point of at least 1400C). After reading this specification, the skilled person will be able to determine the composition of the conductive layer to meet the needs or desires of a particular application. Portions of the conductive layer overlying insulating layer 1302 are removed to form conductive plugs, such as conductive plug 1422 within contact opening 1322.

Conductive layers can be deposited to form the source terminal 1424 and the drain terminal 1426. The conductive layers may each comprise a single membrane or a plurality of separate membranes. Exemplary materials include aluminum, tungsten, copper, gold, or the like. Each conductive layer may or may not be patterned to form a source terminal 1424 or a drain terminal 1426, as shown in fig. 14. In a particular embodiment, the drain terminal 1426 may be part of a back contact to a substrate that includes the underlying doped region 102. In another embodiment, the conductive layer used to form the source terminal 1424 may be patterned to also form a gate terminal (not shown) to be connected to the gate signal line 1264. In the illustrated embodiment, no conductive plug extends to the vertically oriented conductive region, and in particular, conductive structure 402.

The electronic device may include many other power transistors that are substantially equal to the power transistor shown in fig. 14. The power transistors are connected in parallel to provide a sufficiently effective channel width of the electronic device that can support the relatively high currents used during normal operation of the electronic device. In particular embodiments, an electronic device may be designed to have a maximum source-drain voltage difference of 30V, and a maximum source-gate voltage difference of 20V. In normal operation, the source-drain voltage difference is no greater than about 20V, and the source-gate voltage difference is no greater than about 9V. Conductive electrode 1262 may be held at a substantially constant voltage during operation to reduce the source-drain capacitance. In a particular embodiment, the conductive electrode 1262 may be approximately 0V, in which case the conductive electrode 1262 may act as a ground plane. In another embodiment, the conductive electrode 1262 may be connected to the source terminal 1424.

The electronic device may be used in applications where the switching speed of the power transistor needs to be rather high. For example, conventional electronic devices are only capable of achieving switching speeds of 0.35 MHz. The embodiments described herein may be used in similar voltages and currents and achieve switching speeds of at least about 2MHz, and in particular embodiments, at least 10MHz, 20MHz, or possibly higher. Non-limiting applications may include electronic devices used as part of a voltage regulator within a computer, such as a personal computer.

These properties can be achieved by forming low-level electronic devices with parasitic characteristics. The resistance (R) across the electronic device while the parasitic capacitance in the power transistor remains relatively low_DSON) Can be kept to a sufficiently low level. When the power transistor has a maximum source-to-gate voltage difference of 20V and a maximum source-to-drain voltage difference of 30V, the electronic device may have a goodness index of no greater than about 30m Ω nC, and in particular embodiments, no greater than 20m Ω nC. The merit index is the resistance (R)_DSON) Multiplied by the voltage from a substantially fully closed or voltage off state to an on or current on state (Q)_TOTAL) The product of the total gate charge required to switch the device. Conventional electronic devices have higher values of superior index. For example, conventional electronic devices with trench power MOSFETs may have a goodness index greater than 70m Ω nC, which is in the United statesAnother conventional device similar to that described in national patent No.7,397,084 may have a figure of merit of at least 50m Ω · nC (both figures of merit relating to a maximum source-gate voltage difference of 20V and a maximum source-drain voltage difference of 30V).

Although meant to limit the invention, some improved performance may involve the use of surface doped regions 504 (e.g., horizontally oriented doped regions) and vertically oriented conductive regions (conductive plugs 402 with or without sidewall doped regions 404). The combination of the surface doped region 504, the vertically oriented conductive region, and the underlying doped region 102 forms a conductive structure having relatively low parasitic characteristics. Fig. 14 includes arrows 1442 illustrating the primary charge carriers (e.g., electrons or holes) flowing through the electronic device, and more specifically the power transistor. Electrons from source terminal 1424 pass through conductive plug 1422 and into source region 1204. When the power transistor is turned on, electrons flow through the channel region of the power transistor (the portion of the well region 904 between the source region 1204 and the surface doped region 504) and then into the surface doped region 504. Within the surface doped region 504, electrons flow more into the horizontal direction, as opposed to the vertical direction, and thus, electrons (and current) flow primarily into the horizontal direction. Electrons flow from the surface doped region 504 into the vertically oriented conductive region, and in particular the conductive structure 402. Within the vertically oriented conduction region, electrons flow more into the vertical direction, as opposed to the horizontal direction, and thus, electrons (and current) flow primarily into the vertical direction.

Because most electrons (current) do not flow themselves perpendicularly through substantially the entire thickness of the semiconductor layer 104, the doping concentration of the semiconductor layer 104 can be reduced without significantly adversely affecting R_DSON. The relatively low concentration of the semiconductor layer 104 helps to reduce parasitic capacitive coupling.

Other embodiments may be used as needed or desired. In particular embodiments, capacitive coupling between the vertically oriented conductive region and the gate electrode may be further reduced. In fig. 15, a portion of a workpiece 1500 is shown having layers 102, 104, 106, and 108 as previously described. In particular embodiments, the pad layer 106, the stop layer 108, or both, may be thicker than the corresponding layers within the workpiece 100 of FIG. 1. The workpiece also includes the slot 202 and sidewalls 204 as previously described. Unlike the workpiece 100, the workpiece 1500 includes a portion 1502 in which a portion of the pad layer 106 under the stop layer 108 has been removed to expose a portion of the major surface 105 of the semiconductor layer 104. The structure shown in fig. 15 can be achieved by subjecting the underlayer 106 to an isotropic etch (wet or dry), wherein the chemistry used for the isotropic etch is selective to other materials of the workpiece 1500 that are exposed during the isotropic etch. In a specific embodiment, the underlying doped region 102 and the semiconductor layer 104 comprise a single crystal semiconductor material, the underlayer comprises an oxide, and the stop layer 108 comprises a nitride. The pad layer 106 is etched using an HF solution to create the undercut shown.

In fig. 16, conductive structure 1602 and doped region 1604 may be formed in a manner similar to conductive structure 402 and sidewall doped region 404. The material for the conductive structure 402 may be conformally deposited such that the gap formed by removing portions of the underlayer 106 is substantially filled. In a specific embodiment, an amorphous silicon or polysilicon layer is conformally deposited. Unlike conductive structure 402, elevated portion 1606 of conductive structure 1602 overlies major surface 105 of semiconductor layer 104 at portion 1502. Unlike sidewall doped region 404, doped region 1604 is formed within portion 1502. The height of elevated portions 1606 of conductive structure 1602 overlying major surface 105 corresponds approximately to the combined thickness of layers 106 and 108. In another embodiment (not shown), the pad layer 106 and the stop layer 108 may be patterned such that both are removed. In other words, the portion of the stop layer 108 overlying the portion 1502 is also removed. In this particular embodiment, the deposition of the material for conductive structure 1602 is not as conformal as the deposition for the embodiment shown in FIG. 16.

Fig. 17 includes an illustration of a workpiece 1500 after additional processing of locations in a process similar to the previous embodiment shown in fig. 12. The features shown in fig. 17 and the corresponding features of fig. 12 are listed in the table below. Each feature in fig. 17 may be of any material, thickness, and may be formed using any of the methods described previously with respect to its corresponding feature shown in fig. 12. For example, gate dielectric layer 1702 may comprise any material, thickness, and be formed using any method as previously described with respect to gate dielectric layer 902.

Watch (A)

FIG. 17	FIG. 12
		Gate dielectric layer 1702	Gate dielectric layer 902
Horizontally oriented doped region 1704	Surface doped region 504
		Well region 1714	Well region 904
Channel region 1722	Channel region 1222
		Source region 1724	Source region 1204
Insulating layer 1732	Insulating layer 602
		Insulating layer 1736	Insulating layer 606
Insulating layer 1752	Insulating layer 622
		Conductive electrode 1762	Conductive electrode 1262
Gate signal line 1764	Gate signal line 1264
		Gate electrode 1786	Gate electrode 1106
Conductive fill material 1796	Conductive fill material 1206

The shape of some features in fig. 17 differs from the corresponding features in fig. 12 because of the different shape of conductive structure 1602 from conductive structure 402. Thus, the horizontally-oriented doped region 1704 does not extend to the trench, and the insulating layers 1732, 1736, 1752, conductive electrode 1762, and gate signal line 1764 change the height between the region above the conductive structure 1602 and another region near the gate electrode 1786. The height change may reduce the capacitive coupling between gate electrode 1786 and conductive structure 1602 as compared to the capacitive coupling between gate electrode 1106 and conductive structure 402 in the embodiment shown in fig. 12. Also, the elevated portion 1606 enables the vertical portion (main portion) of the conductive structure 1602 to be placed further away from the well region 1714 without significantly increasing R_DSON. This greater spacing has a beneficial effect on increasing the breakdown voltage of the device. In a particular embodiment, an uppermost surface of the elevated portion 1606 of the conductive structure 1602 is greater than a lowermost surface of the gate electrode 1786 (e.g., the gate electrode)1786 bottom of sidewall spacer structure) is at a higher elevation.

In another embodiment, a compensation zone may be used to help reduce R_DSON. In the embodiment shown in fig. 18, a compensation region 1804 may be used adjacent to the surface doped region 504. During normal operating conditions, the surface doped region 504 may be consumed from above by the conductive electrode 1262 and from below by the compensation region 1804 simultaneously. This may allow the peak dopant concentration in the surface doped region 504 to increase and result in the same Breakdown Voltage (BV)_DSS) Lower R of rank_DSON。

The compensation region 1804 has an opposite conductivity type from the surface doped region 504 and the underlying doped region 102. In a specific embodiment, the compensation region 1804 has a dopant concentration of no greater than about 2 x 10¹⁷Atom/cm³Or in another embodiment, the dopant concentration is no greater than about 5 x 10¹⁶Atom/cm³. The depth of compensation region 1804 (as measured from major surface 105 of semiconductor layer 104, as shown in fig. 1) is greater than the depth of surface doped region 504, and in another embodiment, portions of semiconductor layer 104 that are not part of a differently doped region (e.g., surface doped region 504, well region 904, sidewall doped region 404, etc.) can be compensation regions. In a specific embodiment, the depth of the compensation regions 1804 is within about 0.5 microns of the depth of the well regions 904. The compensation region 1804 can be formed by doping the semiconductor layer 104 during substantially all or a later portion of the epitaxial deposition. In another embodiment, the compensation regions 1804 may be formed using relatively higher energy implants than those used in forming the surface-doped regions 504. After reading this description, one of ordinary skill in the art will be able to select the energy or energies of the implant (if more than one implant is used to form the compensation region 1804) based on the desired or desired depth and concentration values for the compensation region 1804.

In yet another embodiment (not shown), the insulating layer 602 may be stepped. More specifically, the insulating layer may be thinner closer to the gate electrode 1106 than over the conductive structure 402. When V is_DWhen added, the step of the insulating layer 602Shapes may be more useful. The relatively thinner portion of insulating layer 602 allows less capacitive coupling of gate electrode 1106 to the drain, and the relatively thicker portion of insulating layer 602 reduces the likelihood of dielectric breakdown between conductive structure 402 and conductive electrode 1262.

The transistor as illustrated and described herein may be an NMOS transistor in which the source region 1204, the surface doped region 504, the sidewall doped region 404, and the underlying doped region 102 are all n-type doped, while the channel region 1222 is p-type doped. In this embodiment, the carriers are electrons and the current flows in the opposite direction to the electrons. In another embodiment, the transistor may be a PMOS transistor by reversing the conductivity type of the previously described regions. In this embodiment, the carriers are holes, and the current flows in the same direction as the holes.

Many different aspects and embodiments are possible. Some of these aspects and embodiments are described below. After reading this specification, skilled artisans will appreciate that these aspects and embodiments are exemplary only and do not limit the scope of the invention.

In a first aspect, an electronic device can include a transistor, where the transistor can include a semiconductor layer having a major surface and a conductive structure. The conductive structure can include a horizontally-oriented doped region disposed adjacent the major surface, an underlying doped region spaced apart from the major surface and the horizontally-oriented doped region, and a vertically-oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region. The electronic device may further comprise a conductive electrode overlying and electrically insulated from the conductive structure, wherein the conductive electrode is configured to be substantially constant voltage when the electronic device is in a normal operating state. The electronic device may further include a gate electrode overlying the major surface of the semiconductor layer and a gate signal line overlying the major surface of the semiconductor layer and the conductive structure, wherein the gate signal line overlies the conductive structure in a region occupied by the transistor.

In an embodiment of the first aspect, the vertically oriented conductive regions include elevated portions overlying the major surface of the semiconductor layer. In a specific embodiment, the elevated portion has an uppermost surface located at a higher elevation than a lowermost surface of the gate electrode. In another embodiment, the semiconductor layer includes a compensation region located between the horizontally-oriented doped region and the underlying doped region and extending substantially to the vertically-oriented conductive region, and the compensation region has an opposite conductivity type than the horizontally-oriented doped region and the underlying doped region. In yet another embodiment, the vertically oriented conductive structure includes a conductive plug. In a specific embodiment, the conductive plug comprises doped polysilicon or a refractory metal.

In yet another embodiment of the first aspect, the electronic device further includes a source region disposed adjacent the major surface and a well region disposed adjacent the major surface, wherein a portion of the well region is a channel region of the transistor and is located between the source region and the horizontally-oriented doped region. In a specific embodiment, the electronic device further includes a well contact region disposed adjacent to the source region and an interconnect contacting the source region and the well contact region. In a more specific embodiment, the electronic device is arranged such that, when the electronic device is in a normal operating state, the main carrier flow is from the source region to the underlying doped region via the well region, the horizontally oriented doped region and the vertically oriented conductive structure. In another embodiment, the electronic device further comprises a gate electrode overlying portions of the source region and the channel region. In further embodiments, the interconnect does not overlie and contact the horizontally-oriented doped region or the vertically-oriented conductive region.

In a second aspect, an electronic device can include a semiconductor layer having a major surface and a conductive structure. The conductive structure may include a horizontally-oriented doped region disposed adjacent the major surface, wherein a portion of the well region is located between the source region and the horizontally-oriented doped region, the underlying doped region is spaced apart from the major surface, and the vertically-oriented conductive region is located between the doped horizontal region and the underlying doped region. The semiconductor device may further include a source region disposed adjacent the major surface, a well region disposed adjacent the major surface, wherein a portion of the well region includes a channel region between the source region and the horizontally-oriented doped region. The electronic device may further comprise a gate electrode disposed on the channel region and a conductive electrode configured to be substantially constant voltage when the electronic device is in a normal operating state. A conductive electrode can overlie and be electrically insulated from the conductive structure, and a portion of the conductive electrode can be placed adjacent the gate electrode. The conductive electrode can have a first surface and a second surface opposite the first surface, wherein the major surface is closer to the first surface than the second surface. Each of the first and second surfaces of the conductive electrode may be located at a height between a lowermost point and an uppermost point of the gate electrode within an area occupied by the transistor.

In an embodiment of the second aspect, the electronic device may further comprise a gate signal line overlying the major surface of the semiconductor layer and the conductive structure, wherein within the transistor the gate signal line overlies the conductive structure. In a further embodiment, the horizontally-oriented doped region extends about 0.2 to 2.0 microns along the major surface from the vertically-oriented conducting region toward the source region. In another embodiment, the semiconductor layer has a thickness of no greater than about 5 microns, a portion of the semiconductor layer is located outside the well region, the source region, the horizontally-oriented doped region, and the vertically-oriented conductive region, and a dopant concentration of the portion of the semiconductor layer is no greater than about 1 x 10¹⁶Atom/cm³. In specific embodiments, the dopant concentration is no greater than about 1 × 10¹⁵Atom/cm³. In another embodiment, a portion of the semiconductor layer, the source region, the horizontally oriented doped region and the underlying doped region have the same conductivity type.

In a further embodiment of the second aspect, the semiconductor layer and portions of the well region have a first conductivity type, and the source region, the horizontally-oriented doped region, and the underlying doped region have a second conductivity type opposite the first conductivity type. In yet a further embodiment, the peak dopant concentration of the horizontally oriented doped region is at least about 2 x 10¹⁷Atom/cm³And the peak dopant concentration of each of the vertically oriented conductive region and the underlying doped region is at least about 1 x 10¹⁹Atom/cm³. In the best of thingsIn a bulk embodiment, the peak dopant concentration of the horizontally oriented doped region is no greater than about 2 x 10¹⁸Atom/cm³。

In yet another embodiment of the second aspect, the interconnect does not overlie and contact the horizontally-oriented doped region or the vertically-oriented conductive region.

In a third aspect, an electronic device may include a field effect transistor including a gate dielectric layer. The field effect transistor can be designed to have a maximum gate voltage of about 20V, a maximum drain voltage of about 30V and a figure of merit of no greater than about 30m Ω · nC.

In an embodiment of the third aspect, the figure of merit is no greater than 20m Ω. nC. In another embodiment, the field effect transistor is designed to have a switching speed of at least about 2 MHz. In yet another embodiment, the field effect transistor further includes a channel region comprising primarily a group 14 element.

It is noted that not all of the activities described in the foregoing summary or embodiments are required, that a portion of a particular activity may not be required, and that one or more additional activities may be performed in addition to those described. Further, the order in which activities are listed are not necessarily the order in which they are performed.

Certain features that are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Moreover, reference to values expressed as ranges includes each and every value within that range.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. The benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced, however, are not to be construed as a critical, required, or essential feature or feature of any or all the claims.

The illustrations and descriptions of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. This description and illustration is not intended to be an exhaustive or comprehensive description of all the elements and features of apparatus and systems that utilize the structures or methods described herein. Different embodiments may also be provided in combination in a single embodiment, but rather, different features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Moreover, reference to values expressed as ranges includes each and every value within that range. Many other embodiments will be apparent to the skilled person only after reading this specification. Other embodiments may be utilized and derived from the disclosure, such that structural substitutions, logical substitutions, or other changes may be made without departing from the scope of the disclosure. Accordingly, this disclosure is to be considered as illustrative and not restrictive.

Claims (10)

1. An electronic device comprising a transistor, wherein the transistor comprises:

a semiconductor layer having a major surface and defining a trench;

a conductive structure, comprising:

a horizontally oriented doped region disposed adjacent the major surface;

an underlying doped region spaced apart from the major surface and the horizontally oriented doped region; and

a vertically oriented conductive region extending through a majority of the thickness of the semiconductor layer and electrically connecting the doped horizontal region and the underlying doped region, wherein the vertically oriented conductive region comprises a conductive structure that completely fills the trench;

a conductive electrode overlying and electrically insulated from the conductive structure, wherein the conductive electrode is configured to be at a constant voltage when the electronic device is in a normal operating state;

a gate electrode overlying the major surface of the semiconductor layer;

a gate signal line overlying the major surface of the semiconductor layer and the conductive structure, wherein the gate signal line overlies the conductive structure in an area occupied by the transistor; and

a drain terminal is connected to the underlying doped region.

2. An electronic device, comprising:

a semiconductor layer having a major surface and defining a trench;

a conductive structure, comprising:

a horizontally oriented doped region disposed adjacent the major surface, wherein a portion of the well region is located between the source region and the horizontally oriented doped region;

an underlying doped region spaced from the major surface; and

a vertically oriented conductive region between a doped horizontal region and the underlying doped region, wherein the vertically oriented conductive region comprises a conductive structure that completely fills the trench; a source region disposed adjacent to the major surface;

a well region disposed adjacent the major surface, wherein a portion of the well region includes a channel region between the source region and the horizontally-oriented doped region;

a gate electrode overlying the channel region; and

a conductive electrode configured to be constant voltage when the electronic device is in a normal operating state, wherein:

the conductive electrode overlies and is electrically insulated from the conductive structure;

a portion of the conductive electrode is positioned adjacent to the gate electrode;

the conductive electrode has a first surface and a second surface opposite the first surface;

the major surface is closer to the first surface than the second surface;

each of the first and second surfaces of the conductive electrode is located at a height between a lowermost point and an uppermost point of the gate electrode within an area occupied by the transistor; and

a drain terminal is connected to the underlying doped region.

3. An electronic device, comprising:

a semiconductor layer having a major surface and defining a trench;

a source region disposed adjacent to the major surface;

a conductive structure, comprising:

a horizontally oriented doped region disposed adjacent the major surface,

an underlying doped region spaced from the major surface; and

a vertically oriented conductive region located between the horizontally oriented doped region and the underlying doped region, wherein the vertically oriented conductive region comprises a conductive structure that completely fills the trench;

a gate electrode overlying the semiconductor layer;

a conductive electrode overlying and electrically insulated from the conductive structure;

a patterned insulating layer defining a contact opening extending towards the source region;

a conductive element filling the contact opening and electrically connected to and covering the source region, wherein the conductive element is spaced apart from the conductive electrode; and

a drain terminal is connected to the underlying doped region.

4. An electronic device as claimed in claim 1, 2 or 3, wherein the vertically oriented conductive region comprises an elevated portion overlying a major surface of the semiconductor layer.

5. The electronic device of claim 4, wherein the elevated portion has an uppermost surface that is at a higher elevation than a lowermost surface of the gate electrode.

6. The electronic device of claim 1, 2 or 3, wherein:

the semiconductor layer includes a compensation region;

the compensation region is located between the horizontally-oriented doped region and the underlying doped region and extends to the vertically-oriented conductive region; and is

The compensation region has an opposite conductivity type to the horizontally oriented doped region and the underlying doped region.

7. An electronic device as claimed in claim 1, 2 or 3, wherein the vertically oriented conductive region comprises a conductive plug.

8. The electronic device of claim 1, 2 or 3, wherein:

the conductive structure includes a refractory metal and a compound containing a refractory metal.

9. The electronic device of claim 1, 2, or 3, wherein the horizontally-oriented doped region extends 0.2 to 2.0 microns along the major surface from the vertically-oriented conducting region toward the source region.

10. The electronic device of claim 1, 2 or 3, wherein:

the peak dopant concentration of the horizontally oriented doped region is at least 2 x 10¹⁷Atom/cm³And not more than 2X 10¹⁸Atom/cm³(ii) a And is

Each of the vertically oriented conductive region and the underlying doped region has a peak dopant concentration of at least 1 x 10¹⁹Atom/cm³。