HK1151888B - Electronic device including an integrated circuit with transistors coupled to each other - Google Patents

Description

Electronic device comprising an integrated circuit with transistors coupled to each other

Technical Field

The present disclosure relates to electronic devices and processes of forming electronic devices, and more particularly, to electronic devices including integrated circuits having transistors coupled to each other and processes of forming electronic devices.

Background

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are a common type of power switching device. The MOSFET includes a source region, a drain region, a channel region extending between the source region and the drain region, and a gate structure disposed adjacent to the channel region. The gate structure includes a gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer.

When the MOSFET is in an on-state, a voltage is applied to the gate structure to form a conducting channel region between the source and drain regions, which allows current to flow through the device. In the off state, any voltage applied to the gate structure is sufficiently low that a conduction channel cannot form and thus no current flow occurs. During the off-state, the device must support a high voltage between the source and drain regions.

In certain applications, a pair of power transistors may be used to allow the output to be switched between two different voltages. The output may be connected to the source of the high-side power transistor and to the drain of the low-side power transistor. When the high-side power transistor is activated, the output will be at a voltage corresponding to the voltage on the drain of the high-side power transistor, and when the low-side power transistor is activated, the output will be at a voltage corresponding to the source of the low-side power transistor. In a particular physical implementation, the high-side power transistor and the low-side power transistor are typically discrete transistors on separate dies interconnected to each other by wire bonds or other similar interconnections. The interconnect adds parasitic characteristics to the electronic device, including the high-side and low-side power transistors, which is undesirable.

Disclosure of Invention

The technical solution of the present invention is intended to solve at least one technical problem of the prior art.

Specifically, according to one aspect of the present invention, there is provided an electronic device including an integrated circuit, comprising: a buried conductive region; a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a major surface and an opposing surface, and the buried conductive region is located closer to the opposing surface than to the major surface; a low-side power transistor comprising a drain, wherein: the drain comprises a first doped region in the semiconductor layer and located closer to the major surface than to the opposing surface; a high-side power transistor comprising a source, wherein: the source comprises a second doped region in the semiconductor layer and located closer to the major surface than to the opposing surface; a first vertical conductive structure extending through the semiconductor layer and electrically connected to and adjacent to the buried conductive region and electrically connected to and adjacent to the first doped region; and a second vertical conductive structure extending through the semiconductor layer and electrically connected to and adjacent the buried conductive region and electrically connected to and adjacent the second doped region, the first vertical conductive structure being spaced apart from the second vertical conductive structure.

According to an embodiment of the above electronic device according to the invention, further comprising a third doped semiconductor region having an opposite conductivity type compared to the buried conductive region, wherein the third doped semiconductor region extends through the semiconductor layer.

According to an embodiment of the above electronic device, the second vertical conductive structure is located between the first vertical conductive structure and the semiconductor layer.

In accordance with an embodiment of the above electronic device, wherein the electronic device further comprises a horizontally oriented doped region located adjacent to the main surface, wherein the horizontally oriented doped region is a drift region of the high-side power transistor.

According to another aspect of the invention there is provided a process of forming an electronic device comprising an integrated circuit, the electronic device comprising a high-side transistor and a low-side transistor, the process comprising the steps of: providing a substrate comprising a first semiconductor layer over a buried conductive region, wherein the first semiconductor layer has a major surface and an opposing surface, and the buried conductive region is located closer to the opposing surface than to the major surface; forming a first vertical conductive structure extending through the first semiconductor layer; forming a second vertical conductive structure extending through the first semiconductor layer; a first doped region formed in the semiconductor layer and along the major surface of the first semiconductor layer, wherein the first doped region is part of a drain of the low-side transistor; forming gate electrodes of the high-side transistor and the low-side transistor after forming the first doped region; a second doped region formed in the first semiconductor layer and along the major surface of the first semiconductor layer after forming the gate electrode, wherein the second doped region is part of a source of the high-side transistor, wherein, in the completed device: the first doped region and the buried conductive region are electrically connected to each other via the first vertical conductive structure; and the second doped region and the buried conductive region are electrically connected to each other via the second vertical conductive structure.

According to an embodiment of the above process of the present invention, further comprising the steps of: forming a trench through the first semiconductor layer prior to forming the second vertical conductive structure; forming a doped semiconductor region along sidewalls of the trench, wherein the doped semiconductor region has an opposite conductivity type and a higher doping concentration than the first semiconductor layer than the buried conductive region; and forming an insulating liner in the trench prior to forming the second vertical conductive structure.

According to an embodiment of the above process of the present invention, the step of forming the doped semiconductor region comprises: depositing a second semiconductor layer along the exposed surface of the trench; anisotropically etching the second semiconductor layer to remove a portion of the second semiconductor layer overlying along a bottom of the trench and expose a portion of the buried conductive region.

According to one embodiment of the above process of the present invention, further comprising forming a horizontally oriented doped region located adjacent to the major surface, wherein the horizontally oriented doped region is a drift region of the high-side transistor.

According to one embodiment of the above process of the present invention, wherein each of the high-side transistor and the low-side transistor is a power transistor.

Drawings

Embodiments are shown by way of example and not limited to the accompanying figures.

Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece including a buried conductive region.

Fig. 2 includes an illustration of a cross-sectional view of the workpiece of fig. 1 after forming a buried doped region for a high-side power transistor.

Fig. 3 includes an illustration of a cross-sectional view of the workpiece of fig. 2 after forming a semiconductor layer, a liner layer, and a termination layer.

Fig. 4 includes an illustration of a cross-sectional view of the workpiece of fig. 3 after patterning portions of a liner layer and a termination layer and forming vertical isolation regions.

Fig. 5 includes an illustration of a cross-sectional view of the workpiece of fig. 4 after patterning other portions of the liner layer and the stop layer and forming sidewall spacers.

Fig. 6 includes an illustration of a cross-sectional view of the workpiece of fig. 5 after forming a trench extending through the semiconductor layer to the buried conductive region.

FIG. 7 includes an illustration of a cross-sectional view of the workpiece of FIG. 6 after forming insulating spacers within the trenches.

Fig. 8 includes an illustration of a cross-sectional view of the workpiece of fig. 7 after forming recessed conductive structures within the trenches.

Fig. 9 includes an illustration of a cross-sectional view of the workpiece of fig. 8 after removal of sidewall spacers adjacent to the pad layer and the termination layer and after removal of portions of the insulating spacers on the elevated portions above the conductive structures.

Fig. 10 includes an illustration of a cross-sectional view of the workpiece of fig. 9 after forming a conductive plug and removing the liner layer and the remaining portions of the termination layer.

FIG. 11 includes an illustration of a cross-sectional view of the workpiece of FIG. 10 after forming an implant mask layer and a drain region.

FIG. 12 includes an illustration of a cross-sectional view of the workpiece of FIG. 11 after forming an insulating layer.

FIG. 13 includes an illustration of a cross-sectional view of the workpiece of FIG. 12 after forming a patterned conductive layer.

FIG. 14 includes an illustration of a cross-sectional view of the workpiece of FIG. 13 after forming an insulating layer on the patterned conductive layer.

FIG. 15 includes an illustration of a cross-sectional view of the workpiece of FIG. 14 after patterning portions of the insulating layer and the patterned conductive layer and forming sidewall spacers.

FIG. 16 includes an illustration of a cross-sectional view of the workpiece of FIG. 15 after formation of another conductive layer and well region.

FIG. 17 includes an illustration of a cross-sectional view of the workpiece of FIG. 16 after forming remaining portions of the conductive layer, etching the resulting conductive layer to form gate electrodes, and forming source regions.

Fig. 18 includes an illustration of a cross-sectional view of the workpiece of fig. 17 after forming sidewall spacers, etching portions of the source regions, and forming well contact regions.

Fig. 19 includes an illustration of a cross-sectional view of the workpiece of fig. 18 after forming conductive stripes to the source regions, well contact regions, and conductive plugs.

Fig. 20 includes an illustration of a cross-sectional view of the workpiece of fig. 19 after forming a substantially complete electronic device in accordance with an embodiment of the invention.

Fig. 21 through 25 include illustrations of cross-sectional views of a portion of the workpiece of fig. 3 in which trenches, vertical isolation regions, and vertical conductive structures are formed according to another embodiment.

Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of embodiments of the present invention.

Detailed Description

The following description, taken in conjunction with the accompanying drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This emphasis is provided to help describe the teachings and should not be construed to limit the scope or applicability of the teachings. However, other teachings can of course be used in this application.

As used herein, the terms "horizontally oriented" and "vertically oriented" with respect to a region or structure refer to the primary direction of current flow through such region or structure. More specifically, current may flow through a region or structure in a vertical direction, a horizontal direction, or a combination of vertical and horizontal directions. A region or structure will be referred to as vertically oriented if current flows through the region or structure in a vertical direction or in a combined direction where the vertical component is greater than the horizontal component. Similarly, a region or structure will be referred to as being horizontally oriented if current flows through the region or structure in a horizontal direction or in a combined direction where the horizontal component is greater than the vertical component.

The terms "normal operation" and "normal operating state" refer to the conditions under which an electronic component or device is designed to operate. These conditions may be obtained from a data table or other information about voltage, current, capacitance, resistance, or other electrical parameters. Thus, normal operation does not include operating an electronic component or device entirely outside of its design limits.

The term "power transistor" is used to refer to a transistor designed to operate normally with a difference of at least 10V maintained between the source and drain or emitter and collector of the transistor. For example, when the transistor is in the off state, 10V may be maintained between the source and drain without junction breakdown or other undesirable conditions occurring.

The terms "comprises," "comprising," "including," "includes," "including," "has," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly stated to the contrary, "or" refers to an inclusive "or" and not to an exclusive "or". For example, any one of the following satisfies condition a or B: a is true (or present) and B is false (or not present), a is false (or not present) and B is true (or present), and both a and B are true (or present).

In addition, the use of "a" or "an" is used to describe an element or component described herein. This is done merely for convenience and to give a general sense of the scope of the invention. Such description should be understood to include one or at least one and the singular also includes the plural and vice versa unless it is obvious that it is meant otherwise. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, where more than one item is described herein, a single item may be substituted for that more than one item.

Members of the groups corresponding to the columns in the periodic Table of the elements are used, for example, in CRC Handbook of chemistry and Physics，81^stThe "New symbol" convention seen in Edition (2000-.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronic arts.

In the following figures, two different portions of a workpiece are shown to improve understanding of the effects of processing operations in forming different types of transistors on the same workpiece. These transistors will be part of the same integrated circuit. The diagram closer to the top of the figure corresponds to a high-side power transistor, while the diagram closer to the bottom of the same figure corresponds to a low-side power transistor.

Fig. 1 includes an illustration of a cross-sectional view of a portion of a workpiece 100, the workpiece 100 including a buried conductive region 102. The buried conductive region 102 may include a group 14 element (i.e., carbon, silicon, germanium, or any combination thereof) and may be heavily n-type or p-type doped. For the purposes of this specification, heavily doped is used to mean at least 10¹⁹ atoms/cm³With lightly doped is meant less than 10¹⁹ atoms/cm³The peak doping concentration of (a). The buried conductive region 102 may be a portion of a heavily doped substrate (i.e., a heavily n-type doped wafer) or may be a buried doped region overlying a substrate of the opposite conductivity type or overlying a buried insulating layer (not shown) between the substrate and the buried conductive region 102. In one embodiment, the buried conductive region 102 is heavily doped with an n-type dopant such as phosphorous, arsenic, antimony, or any combination thereof. In particular embodiments, the buried conductive region 102 comprises arsenic or antimony if the diffusion of the buried conductive region 102 is to be kept low, and in particular embodiments, the buried conductive region 102 comprises antimony to be conformalThe level of autodoping (compared to arsenic) is reduced in the formation of the subsequently formed semiconductor layer. The buried conductive region 102 will be used to electrically connect together the source of the high-side power transistor and the drain of the low-side power transistor and become part of the output node of the electronic device.

Referring to fig. 2, a semiconductor layer 204 is formed over the buried conductive region 102. The semiconductor layer 204 may include a group 14 element (i.e., carbon, silicon, germanium, or any combination thereof) and any dopant as described with respect to the buried conductive region 102 or a dopant of the opposite conductivity type. In one embodiment, semiconductor layer 204 is an n-type or p-type lightly doped epitaxial silicon layer having a thickness in a range of about 0.2 microns to about 2.0 microns and no greater than about 10¹⁷ atoms/cm³And, in another embodiment, has a doping concentration of at least about 10¹⁴ atoms/cm³The doping concentration of (c). A semiconductor layer 204 is formed over all of the workpiece 100.

A portion of the semiconductor layer 204 in the high-side power transistor is heavily doped with dopants of an opposite conductivity type as compared to the buried conductive region 102 to form a buried doped region 206. The buried doped region 206 may facilitate insulation within the high-side power transistor and reduce the parasitic characteristics of the high-side power transistor. In a particular embodiment, the buried doped region 206 has a doping of at least about 10¹⁸atoms/cm³The peak doping concentration of the p-type dopant of (a).

Referring to fig. 3, a semiconductor layer 304 is formed over the semiconductor layer 204 (not labeled in fig. 3) and the buried doped region 206. In a particular embodiment, the semiconductor layers 204 and 304 have the same conductivity type and are both lightly doped. Thus, the dashed line in the illustration of the low-side power transistor in fig. 3 shows the approximate location where the semiconductor layer 204 ends and the semiconductor layer 304 begins. Semiconductor layer 304 has a major surface 305. The semiconductor layer 304 may include a group 14 element (i.e., carbon, silicon, germanium, or any combination thereof) and any dopant as described with respect to the buried conductive region 102 or dopants of the opposite conductivity type. In one embodiment, the semiconductor layer 304 is lightly doped n-type or p-typeAn epitaxial silicon layer having a thickness in the range of about 0.5 microns to about 5.0 microns and no greater than about 10¹⁷ atoms/cm³And, in another embodiment, has a doping concentration of at least about 10¹⁴ atoms/cm³The doping concentration of (c). The doping concentration in the semiconductor layer 304 formed or prior to selectively doping regions in the semiconductor layer 304 will be referred to as the background doping concentration. In the subsequent illustration of the low-side power transistor, the combination of semiconductor layers 204 and 304 will be referred to as semiconductor layer 304 and will not include the dashed line.

A liner layer 306 and a stop layer 308 (e.g., a polish stop layer or an etch stop layer) are sequentially formed on the semiconductor layer 304 using thermal growth techniques, deposition techniques, or a combination thereof. Each of the liner layer 306 and the stop layer 308 may comprise an oxide, a nitride, an oxynitride, or any combination thereof. In one embodiment, the pad layer 306 has a different composition than the stop layer 308. In a particular embodiment, the pad layer 306 includes an oxide and the stop layer 308 includes a nitride.

Referring to fig. 4, a patterned masking layer 402 is formed over the stop layer 308. Openings in patterned masking layer 402 are formed where vertical isolation regions are to be formed. Vertical isolation regions are formed where the high-side power transistors are being formed. Thus, the patterned masking layer 402 covers substantially all of the termination layer 308 of the low side power transistor being formed. In a particular embodiment, the exposed portions of the pad layer 306 and the stop layer 308 are removed to expose portions of the semiconductor layer 304. In another embodiment (not shown), the pad layer 306 or the exposed portions of the pad layer 306 and the stop layer 308 are not etched. The presence of the liner layer 306 or the liner layer 306 and the stop layer 308 may help reduce implant channeling during subsequent implants.

Portions of semiconductor layer 304 underlying the openings in patterned masking layer 402 are implanted (as indicated by arrows 422) to form vertical isolation regions 424. The implantation may be performed as a single implantation or as multiple implantations. When a multi-injection is performed,different energies, different species, or different energies and species may be used to form the vertical isolation regions 424. The conductivity type of the vertical isolation region 424 may be the same as the buried doped region 206 and opposite to the conductivity type of the buried conductive region 102. In a particular embodiment, the vertical isolation region 424 is p-type and has a conductivity of at least about 10¹⁸ atoms/cm³The doping concentration of (c). The combination of the vertical isolation region 424 and the buried doped region 206 helps to isolate the portion of the semiconductor layer 304 in the high-side power transistor. After implantation, the patterned masking layer 402 is removed. In another embodiment, described later in this specification, the vertical isolation regions may be formed using other techniques.

Another patterned masking layer (not shown) is formed where the pad layer 306 and the stop layer 308 are removed and a trench is subsequently formed. At this point in the process, the pad layer 306 and the stop layer 308 are patterned within the low side power transistor. If the pad layer 306 or the pad layer 306 and the termination layer 308 are not patterned within the high-side power transistor, the pad layer 306 or the pad layer and the termination layer 308 in the high-side power transistor may be patterned with corresponding portions in the low-side power transistor. After the liner layer 306 and the termination layer 308 are patterned in the low-side power transistor (and possibly the high-side power transistor), the other patterned masking layers are removed.

Sidewall spacers 524 are formed as shown in fig. 5. Sidewall spacers 524 may be used to determine the width of the subsequently formed trench and the width of the remaining portion of the vertical isolation region 424 along the sidewalls of the subsequently formed trench. Sidewall spacers 524 may be formed by depositing a sacrificial layer and anisotropically etching the layer. In particular embodiments, the sacrificial layer may include an oxide, a nitride, an oxynitride, or any combination thereof. In a more particular embodiment, the sacrificial layer and the termination layer 308 have different compositions. The thickness of the sacrificial layer may be no greater than about 900nm or about 700nm, or may be at least about 50nm or about 100 nm.

The exposed portions of the semiconductor layer 304 and portions of the vertical isolation region 424 and the buried doped region 206 within the high-side power transistor are etched to form a trench 624 extending from the major surface 305 toward the buried conductive region 102, as shown in fig. 6. The trench 624 may extend partially or completely through the semiconductor layer 304 or the buried doped region 206. The width of the trench 624 is not so wide that a subsequently formed conductive layer cannot fill the trench 624. In particular embodiments, the width of each trench 624 is at least about 0.3 microns or about 0.5 microns, and in another particular embodiment, the width of each trench 624 is no greater than about 4 microns or about 2 microns. After reading this specification, skilled artisans will recognize that narrower or wider widths outside the particular dimensions described may be used. The trench 624 may extend to the buried conductive region 102; however, the trench 624 may be shallower if needed or desired. The trench 624 is formed using an anisotropic etch. In one embodiment, a timed etch may be performed, and in another embodiment, a combination of endpoint detection (e.g., detecting a dopant species, such as arsenic or antimony, from the buried conductive region 102) and a timed overetch may be used.

Insulating sidewall spacers 724 may be formed along the exposed sidewalls of the trenches 624, as shown in fig. 7. The insulating sidewall spacers 724 may comprise an oxide, nitride, oxynitride or any combination thereof. The layer formed by the insulating sidewall spacers 724 may be thermally grown or deposited and the layer may be anisotropically etched to remove the layer from the bottom of the trench 624. An etch may be performed to extend the trench 624 closer to or further into the buried conductive region 102, if needed or desired. In another embodiment, the insulating sidewall spacers 724 need not be or are not formed within all trenches in the high-side or low-side power transistors. In a particular embodiment, the insulating sidewall spacer 724 may be used only in the trench 624 of the low-side power transistor, and not in the trench 624 of the high-side power transistor. In another particular embodiment, the insulating sidewall spacers 724 may be used only in the trenches 624 of the high-side power transistor, and not in the trenches 624 of the low-side power transistor.

A conductive layer is formed over termination layer 308 and within trench 624 and, in a particular embodiment, substantially fills trench 624. The conductive layer may be polycrystalline and comprise a metal-containing or semiconductor-containing material. In one embodiment, the conductive layer may comprise a heavily doped semiconductor material, such as amorphous silicon or polysilicon. In another embodiment, the conductive layer includes a plurality of films, such as an adhesive film, a barrier film, and a conductive fill material. In particular embodiments, the adhesive film may include a refractory metal, such as titanium, tantalum, tungsten, or the like; the barrier film may comprise a refractory metal nitride such as titanium nitride, tantalum nitride, tungsten nitride, or the like, or a refractory metal semiconductor nitride such as TaSiN; and the conductive fill material may comprise tungsten or tungsten silicide. In a more particular embodiment, the conductive material may comprise Ti/TiN/WSi. The number of films and the selection of the composition of these films depends on the electronic properties, the subsequent thermal cycling temperature, another criterion, or any combination thereof. Refractory metals and refractory metal-containing compounds can be refractory to high temperatures (e.g., such materials can have a melting point of at least 1400 degrees celsius), can be conformally deposited, and have a lower bulk resistivity than heavily n-type silicon. After reading this specification, skilled artisans will be able to determine the composition of the conductive layer to meet their needs or requirements for a particular application.

A portion of the conductive layer overlying the termination layer 308 is removed to form a conductive structure 824 in the trench 624, as shown in the embodiment of fig. 8. The removal may be performed using chemical-mechanical polishing or cladding etching techniques. The stop layer 308 may be used as a polish stop layer or an etch stop layer. The polishing or etching may continue for a relatively short period of time after the stop layer 308 is reached to eliminate non-uniformities on the workpiece relative to the conductive layer thickness, non-uniformities in the polishing or etching operation, or any combination thereof. Continued etching or other removal operations may be used to further recess the conductive structures 824 into the trenches 624, as shown in fig. 8, if needed or desired. Recessed conductive structures 824 may allow for easier electrical connection of vertical isolation regions 724 and conductive structures 824 to each other. Conductive structure 824 forms a vertical conductive region. When in the form of the completed electronic device, the combination of the conductive structure 824 and the buried conductive region 102 electrically connects the source of the high-side power transistor to the drain of the low-side power transistor.

The exposed portions of sidewall spacers 524 and insulating sidewall spacers 724 in trench 624 are removed, as shown in fig. 9. The removal may be performed using an isotropic etching technique using wet or dry etchants. In a particular embodiment, the sidewall spacers 524 and the insulating sidewall spacers 724 comprise oxide and the stop layer 308 comprises nitride, so the sidewall spacers 524 and the insulating sidewall spacers 724 may be selectively removed without removing a substantial portion of the stop layer 308. At this point in the process, portions of the conductive structure 824, the vertical isolation region 724, and the semiconductor layer 304 are exposed.

In another embodiment (not shown), in the low side power transistor, the portion of semiconductor layer 304 proximate trench 624 can be doped to form a portion of the drain region of the low side power transistor. A mask may be formed over the high-side power transistor to reduce the likelihood of reverse doping the vertical isolation region 424 in the high-side power transistor. After the portions of the semiconductor layer 304 are doped, the mask is removed. An optional oxidation operation may be performed to help round the upper corners of the semiconductor layer 304.

In fig. 10, conductive plugs 1002 are formed to electrically connect conductive structures 824 to vertical isolation regions 724 and semiconductor layer 304 or doped regions in semiconductor layer 304. Conductive plug 1002 may be formed using any material and formation method for conductive structure 824, except that the conductive plug is not recessed into trench 624. Conductive plug 1002 and conductive structure 824 may comprise the same or different materials and may be formed using the same or different techniques. The liner layer 306 and the stop layer 308 may be removed at this point in the process.

An implant mask layer 1100 is formed over major surface 305 as shown in fig. 11. Implant mask layer 1100 may comprise an oxide, nitride, or oxynitride and may have a thickness in the range of about 2nm to about 50 nm. Implant mask layer 1100 can be formed by thermal growth or deposition techniques.

Drain regions 1102 and 1122 are formed in the semiconductor layer 304 of the high-side and low-side power transistors, respectively. Each of drain regions 1102 includes a relatively higher doping concentration and deeper portion 1104 and a relatively lighter doping concentration and shallower portion 1106, while each of drain regions 1122 includes a relatively higher doping concentration and deeper portion 1124 and a relatively lighter doping concentration and shallower portion 1126. In another embodiment, the deeper portion 1124 of the drain region 1122 may be omitted from the low side power transistor.

Portions 1104 and 1124 are highly conductive and are designed to be at a high voltage, and portions 1106 and 1126 are somewhat more resistive and reduce the voltage near the subsequently formed gate dielectric and gate electrode. Under normal operating conditions where a high voltage is applied to the drain of the power transistor, most or all of regions 1106 and 1126 will be depleted of carriers, and most or all of regions 1104 and 1124 will not be depleted of carriers. In a particular non-limiting embodiment, the portions 1106 and 1126 are horizontally oriented doped regions that are spaced apart from the buried conductive region 102. Under normal operating conditions, the majority carriers (electrons) or current flowing through portions 1106 and 1126 will be in the horizontal direction.

Portions 1104 and 1124 may comprise a doping type opposite to that of the vertical isolation regions 424 and have a doping type of at least about 10¹⁹ atoms/cm³A doping concentration, and portions 1106 and 1126 may comprise a doping type opposite to that of the vertical isolation region 424 and have a doping type of less than about 10¹⁹ atoms/cm³And at least about 10¹⁶ atoms/cm³The doping concentration of (c). Portions 1106 and 1126 have a depth in the range of about 0.1 microns to about 0.5 microns and extend laterally from portions 1104 and 1124 in the range of about 0.2 microns to about 2.0 microns. The lateral dimensions (from the vertically oriented conductive structures or more heavily doped portions 1104 and 1124) may depend on the voltage difference between the source and drain of the power transistor being formed. As the voltage difference between the source and drain of the power transistor increases, the lateral dimension may also increase. In one embodiment, the voltage difference is no greater than largeAbout 30V, and in another embodiment, the voltage difference is no greater than about 20V. The peak doping concentration in portions 1106 and 1126 may be at about 2 x 10¹⁷atoms/cm³To about 2X 10¹⁸ atoms/cm³And, in particular embodiments, at about 4 x 10¹⁷ atoms/cm³To about 7X 10¹⁷ atoms/cm³Within the range of (1).

In a particular embodiment, portions 1104 and 1124 use the same masking layer and the same implant species and other implant parameters as compared to each other, and portions 1106 and 1126 use the same masking layer and the same implant species and other implant parameters as compared to each other; however, the masking layer and implant species and parameters are different for portions 1104 and 1124 compared to portions 1106 and 1126. In subsequent figures, drain regions 1102 and 1122 are shown without distinguishing between different portions.

In alternative embodiments, portions 1106 and 1126 may extend continuously over the length of a unit cell of a transistor (i.e., to the area where channel and source regions will be subsequently formed). The doping of the channel region (to be described later) is increased commensurately to counter-dope the portion of the drain region in the channel. An advantage of extending the lightly doped portions 1106 and 1126 of the drain into the channel region is that it reduces or eliminates the effects of misalignment of the drain masking layer. In further embodiments, this masking layer may be removed, allowing the implant that forms regions 1106 and 1126 to be continuous across the entire workpiece.

An insulating layer 1202 is formed over conductive plug 1002 and implant shield layer 1100, as shown in fig. 12. The insulating layer 1202 includes at least two different types of regions having different thicknesses. In fact, the insulating layer 1202 has a step-like configuration, the importance of which will be described later in this specification. In the embodiment shown in fig. 12, the insulating layer 1202 includes three regions, each having a different thickness. The thinnest area overlies the more lightly doped portions of drain regions 1102 and 1122 (i.e., portions 1106 and 1126 of fig. 11) and the portion of semiconductor layer 304 proximate major surface 305 and outside of drain regions 1102 and 1122. The thickest region overlies the more heavily doped portions of drain regions 1102 and 1122 (i.e., portions 1104 and 1124). The intermediate region may be located between the thinner and thickest regions and is an optional feature.

In one embodiment, the insulating layer 1202 in the thinnest region has a thickness of at least about 0.02 microns or at least about 0.05 microns, and in another embodiment, the insulating layer 1202 in the thinnest region has a thickness of no greater than about 0.2 microns or no greater than about 0.1 microns. In one embodiment, the insulating layer 1202 in the thickest region has a thickness of at least about 0.15 microns or at least about 0.25 microns, and in another embodiment, the insulating layer 1202 in the thickest region has a thickness of no greater than about 0.8 microns or no greater than about 0.5 microns. The intermediate region (between the thinner and thickest regions) may have substantially the same thickness as the thinnest region or the thickest region, or a thickness intermediate between the thicknesses of the thinner and thickest regions. In one embodiment, the insulating layer 1202 in the intermediate region has a thickness of at least about 0.05 microns or at least about 0.15 microns, and in another embodiment, the insulating layer 1202 in the intermediate region has a thickness of no greater than about 0.5 microns or no greater than about 0.25 microns. In a particular embodiment, the insulating layer 1202 in the thinnest region has a thickness in the range of about 0.03 microns to about 0.08 microns, the insulating layer 1202 in the thickest region has a thickness in the range of about 0.3 microns to about 0.5 microns, and the insulating layer 1202 in the middle region has a thickness in the range of about 0.13 microns to about 0.2 microns.

The insulating layer 1202 can be formed by different techniques and achieve different shapes as seen in the cross-sectional view. The insulating layer 1202 may be formed from a single insulating film or multiple insulating films deposited over the workpiece. The insulating film or films may include an oxide, a nitride, an oxynitride, or any combination thereof. In particular embodiments, the characteristics of insulating layer 1202 are different for points closer to implant shield layer 1100 than for corresponding points farther from implant shield layer 1100. In one embodiment, the composition of the insulating layer 1202 may be changed during or between depositions. For example, an oxide film may be closer to the implant shield layer 1100, and a nitride film may be deposited over the oxide film. In another embodiment, dopants, such as phosphorus, may be incorporated at an increased concentration during post-deposition. In yet another embodiment, the stress in the film can be varied by varying deposition parameters (e.g., rf power, pressure, etc.), even though the composition is substantially the same throughout the thickness of the insulating layer 1202. In further embodiments, combinations of the above approaches may be used. A mask is formed over the thicker and intermediate regions and patterning techniques are used to achieve the desired shape. These techniques include isotropically etching a portion of the insulating layer 1202, optionally etching the insulating material and etching the sidewall etch overlying the mask, etching the insulating material and etching the sidewall overlying the mask, utilizing a different composition (doped oxide etches faster than undoped oxide), patterning after formation of sidewall spacers, another suitable technique, or any combination thereof.

In fig. 13, a conductive layer 1302 is deposited over the insulating layer 1202 and patterned to form an opening 1304 where a drain contact structure is then made to the drain region 1102 of the high-side power transistor. The conductive layer 1302 includes a conductive material or can be made conductive, such as by doping. More specifically, the conductive layer 1302 can include a doped semiconductor material (e.g., heavily doped amorphous silicon, polysilicon, etc.), a metal-containing material (refractory metal, refractory metal nitride, refractory metal silicide, etc.), or any combination thereof. The conductive layer 1302 has a thickness in a range of about 0.05 microns to about 0.5 microns. In a particular embodiment, conductive layer 1302 will be used to form a conductive electrode.

Insulating layer 1402 is formed over conductive layer 1302 as shown in fig. 14. Insulating layer 1402 may include a single film or multiple films. Each film in insulating layer 1402 can include an oxide, a nitride, an oxynitride, or any combination thereof. In another particular embodiment, the nitride film is proximate to the conductive layer 1302 and has a thickness in a range from about 0.05 microns to about 0.2 microns. The oxide film overlies the nitride film and has a thickness in a range of about 0.2 microns to about 0.9 microns. An antireflective film may cover the oxide film or may be incorporated elsewhere into insulating layer 1402. For example, the nitride film may be selected to have an appropriate thickness to serve as an etch stop layer and to serve as an anti-reflective film. In another embodiment, more or fewer films may be used, and the thicknesses described herein are merely illustrative and are not meant to limit the scope of the invention.

The insulating layer 1402, the conductive layer 1302, and the insulating layer 1202 are patterned to form openings, and insulating spacers 1502 are formed, as shown in fig. 15. The opening is formed such that portions of drain regions 1102 and 1122 are located below the opening. Such portions (i.e., portions 1106 and 1126 as shown in figure 11) allow portions of drain regions 1102 and 1122 to underlie portions of subsequently formed gate electrodes. Insulating spacers 1502 are formed along the sides of the opening. The insulating spacers 1502 electrically insulate the conductive layer 1302 from subsequently formed gate electrodes. The insulating spacer 1502 may comprise an oxide, nitride, oxynitride, or any combination thereof, and has a width in the range of about 50nm to about 200nm on the bottom of the insulating spacer 1502.

Fig. 16 includes an illustration of the workpiece after forming gate dielectric layer 1600, conductive layer 1602, and well regions 1604 and 1624. Portions of implant mask layer 1100 are removed by etching and a gate dielectric layer 1600 is formed over the exposed surface of the workpiece. In a particular embodiment, the gate dielectric layer 1600 includes an oxide, a nitride, an oxynitride, or any combination thereof, and has a thickness in a range of about 5nm to about 100 nm. Conductive layer 1602 overlies gate dielectric layer 1600 and may be part of a subsequently formed gate electrode. Conductive layer 1602 can be conductive as deposited, or can be deposited as a high resistance layer (e.g., undoped polysilicon) and subsequently made conductive. Conductive layer 1602 may include a metal-containing or semiconductor-containing material. In one embodiment, the thickness of conductive layer 1602 is selected such that, from a top view, substantially vertical edges of conductive layer 1602 are near the edges of drain regions 1102 and 1122. In one embodiment, conductive layer 1602 is deposited to a thickness of about 0.1 microns to about 0.15 microns.

After conductive layer 1602 is formed, semiconductor layer 304 can be doped to form well region 1604 in fig. 16. The well regions 1604 and 1624 are of a conductivity type opposite to that of the drain regions 1102 and 1122 and the buried conductive region 102. In one embodiment, boron dopants are introduced into semiconductor layer 304 through conductive layer 1602 and gate dielectric layer 1600 to provide p-type dopants for well regions 1604 and 1624. In one embodiment, well region 1604 has a depth greater than that of a subsequently formed source region, and in another embodiment, well regions 1604 and 1624 have a depth of at least about 0.3 microns. In a further embodiment, well regions 1604 and 1624 have a depth of no greater than about 2.0 microns, and in yet another embodiment, no greater than about 1.5 microns. By way of example, well regions 1604 and 1624 may be formed using two or more ion implantations. In a particular embodiment, approximately 1.0 x 10 is used per ion implantation¹³ atoms/cm²Is performed with two implants having energies of about 25KeV and about 50 KeV. In another embodiment, more or less ion implantations may be performed when forming the well region. Different doses may be used at different energies, higher or lighter doses, higher or lower energies, or any combination thereof may be used to meet the needs or desires for a particular application.

In an alternative embodiment (not shown), the dose of the ion implant forming well regions 1604 and 1624 is increased to compensate for drain regions 1102 and 1122 as portions of lightly doped regions 1106 and 1126 extend over the unit cell of the transistor. In yet another embodiment, conductive layer 1602 is not deposited and the implants forming well regions 1604 and 1624 use sidewall spacers 1502 instead as hard mask edges. In a further specific embodiment, the two embodiments may be combined.

Additional conductive material is deposited over conductive layer 1602 and etched to form gate electrodes 1702 and 1722 as shown in figure 17. Additional conductive materials may include any of the materials previously described with respect to conductive layer 1602. Similar to conductive layer 1602, the additional conductive material may be conductive as deposited, or may be deposited as a high resistance layer (e.g., undoped polysilicon) and subsequently made conductive. Conductive layer 1602 and the additional conductive material may have the same composition or different compositions with respect to each other. The thickness of the composite conductive layer, including conductive layer 1602 and additional conductive material, has a thickness in the range of about 0.15 microns to about 0.5 microns. When layer 1602 is not present in the workpiece, the thickness of gate electrodes 1702 and 1722 (as measured along their bottoms) is defined by the thickness of a single conductive layer. In particular embodiments, the additional conductive material comprises polysilicon and may be doped with an n-type dopant during deposition or subsequently doped using ion implantation or another doping technique. The composite conductive layer is anisotropically etched to form gate electrodes 1702 and 1722. In the illustrated embodiment, the gate electrodes 1702 and 1722 are formed without using a mask and have the shape of sidewall spacers. An insulating layer (not shown) may be thermally grown from the gate electrodes 1702 and 1722 or may be deposited over the workpiece. The thickness of the insulating layer may be in the range of about 10nm to about 30 nm.

Source regions 1704 and 1724 may be formed using ion implantation. The source regions 1704 and 1724 are heavily doped and have an opposite conductivity type compared to the well regions 1604 and 1624 and the same conductivity type as the drain regions 1102 and 1122 and the buried conductive region 102. The portion of the well region 1604 between the source region 1704 and the drain region 1102 and below the gate electrode 1702 is a channel region of a high-side power transistor, and the portion of the well region 1624 between the source region 1724 and the drain region 1122 and below the gate electrode 1722 is a channel region of a low-side power transistor.

Well contact regions 1804 and 1824 are formed within well regions 1604 and 1624, respectively, as shown in fig. 18. Insulating spacers 1802 are formed along the gate electrodes 1702 and 1722 and cover portions of the source regions 1704 and 1724 closer to the gate electrodes 1702 and 1722, where the exposed portions of the source regions 1704 and 1724 (not shown in fig. 18) are located closer to the conductive plugs 1002. The insulating spacer 1802 may include an oxide, a nitride, an oxynitride, or any combination thereof, and has a width in a range of about 50nm to about 500nm at a bottom of the insulating spacer 1802.

The exposed portions of source regions 1704 and 1724 are etched to expose underlying portions of well regions 1604 and 1624, respectively. Depending on the composition of the conductive plug, portions of the conductive plug 1002 may or may not be etched when the source regions 1704 and 1724 are etched. If the conductive plug 1002 and the semiconductor layer 304 (from which the well regions 1604 and 1624 and the source regions 1704 and 1724 are formed) are primarily silicon, then some or all of the conductive plug 1002 may be etched when etching through the source regions 1704 and 1724. If conductive plug 1002 and source regions 1704 and 1724 comprise different materials, then conductive plug 1002 may not be etched or a small portion thereof may be etched while etching through source regions 1704 and 1724.

Well contact regions 1804 and 1824 are formed from the exposed portions of well regions 1604 and 1624, respectively. The well contact regions 1804 and 1824 have the same conductivity type as the well regions 1604 and 1624 and have an opposite conductivity type as compared to the source regions 1704 and 1724. In a particular embodiment, the well contact regions 1804 and 1824 have a height of at least about 10¹⁹ atoms/cm³To allow for subsequent ohmic contact formation.

In another embodiment (not shown), additional implants (not shown) having the same conductivity type as the well regions 1604 and 1624 and an opposite conductivity type as the source regions 1704 and 1724 may be used to form well contact regions below the source regions 1704 and 1724. The additional implants may be performed before or after forming source regions 1704 and 1724 and before forming insulating spacers 1802. In this embodiment, the well contact region is located substantially below all of source regions 1704 and 1724. After source regions 1704 and 1724 and well contact regions are formed, insulating spacers 1802 are formed so that only portions of source regions 1704 and 1724 are covered. An etch as previously described is performed to remove portions of source regions 1704 and 1724 and to expose portions of the underlying well contact regions.

Referring to fig. 19, a portion of insulating spacer 1802 is etched to expose portions of source regions 1704 and 1724. Conductive stripes 1902 are then formed to electrically connect source regions 1704, well contact regions 1804, and corresponding conductive plugs 1002 together, and other conductive stripes 1902 are formed to electrically connect source regions 1724 and well contact regions 1824 together. In particular embodiments, a refractory metal such as titanium, tantalum, tungsten, cobalt, platinum, or similar metal may be deposited over the workpiece and selectively reacted with exposed silicon, such as substantially single crystal silicon or polycrystalline silicon, to form a metal silicide. An unreacted portion of the refractory metal covers over the insulating layer 1402 and the insulating spacers 1802 are removed, thus leaving the conductive stripes 1902. Although not shown, uppermost portions of the gate electrodes 1702 and 1722 can be exposed and react with the refractory metal. However, the metal suicide at such locations is spaced apart from the conductive strip 1902, and therefore no electrical shorts are formed between the gate electrodes 1702 and 1722 and any of the source regions 1704 and 1724 and the well contact regions 1804 and 1824. At this point in the process, high-side and low-side power transistors are formed.

Fig. 20 includes an illustration of a substantially completed electronic device. An interlayer dielectric (ILD) layer 2002 is formed and may include an oxide, nitride, oxynitride or any combination thereof. The ILD layer 2002 may comprise a single film or a plurality of discrete films having a substantially constant or varying composition (e.g., further high phosphorous content from the semiconductor layer 304). An etch stop film, antireflective film, or combination may be used in or on the ILD layer 2002 to aid in processing. The ILD layer 2002 may be planarized to improve process latitude in subsequent processing operations (e.g., lithography, subsequent polishing, etc.).

A resist layer (not shown) is formed over ILD layer 2002 and patterned to define resist openings. An anisotropic etch is performed to define contact openings, as shown in fig. 20, that extend through the ILD layer 2002 to expose portions of the drain region 1102 and the conductive strip 1902. The etch may be performed as a timed etch or as an endpoint detection etch with a timed over-etch. An endpoint may be detected when the drain region 1102 or the conductive strip 1902 becomes exposed.

Conductive plugs 2004 and 2024 are formed within contact openings in ILD layer 2002. Conductive plug 2004 is electrically connected to the drain region 1102 of the high-side power transistor, and conductive plug 2024 is electrically connected to the source region 1724 and well contact region 1824 of the low-side power transistor (through conductive strap 1902). An interconnect 2006 overlies the ILD layer 2002 and electrically connects the drain regions 1102 of the high-side power transistors together, and an interconnect 2026 overlies the ILD layer 2002 and electrically connects the source regions 1724 of the low-side power transistors together. Accordingly, interconnect 2006 may be coupled to a drain terminal of an electronic device, while interconnect 2026 may be coupled to a source terminal of the electronic device. Although not shown, another conductive member is used to electrically connect the gate electrodes 1702 of the high-side power transistors together and yet another conductive member is used to electrically connect the gate electrodes 1722 of the low-side power transistors together. Also, yet another conductive member may be used to electrically connect the conductive layer 1302 to the source region 1704 of the high-side power transistor, and yet another conductive member may be used to electrically connect the conductive layer 1302 to the source region 1724 of the low-side power transistor. Control logic may be coupled to the gate electrodes 1702 and 1722 to control the operation of the series-connected high-side and low-side power transistors. The buried conductive region 102 may be coupled to an output terminal of an electronic device.

Although not shown, additional or fewer layers or features may be used to form the electronic device as needed or desired. The field isolation regions are not shown, but may be used to help electrically isolate portions of the high-side power transistor from the low-side power transistor. In another embodiment, more isolation and interconnect levels may be used. For example, a particular interconnect level may be used for conductive layer 1302, and a different interconnect level may be used for gate electrodes 1702 and 1722. As shown in fig. 20, a passivation layer may be formed over the workpiece. After reading this specification, the skilled person will be able to determine the layers and features for their particular application.

The electronic device may include many other power transistors that are substantially the same as the power transistor shown in fig. 20. The high-side power transistors may be connected in parallel with each other, and the low-side power transistors may be connected in parallel with each other. Such a configuration may give a sufficiently effective channel width of the electronic device that may support the relatively high currents used during normal operation of the electronic device. In a particular embodiment, each power transistor may be designed to have a maximum source-to-drain voltage difference of about 30V and a maximum source-to-gate voltage difference of about 20V. During normal operation, the source-to-drain voltage difference is no greater than approximately 20V, and the source-to-gate voltage difference is no greater than approximately 9V. During operation, the conductive layer 1302 may be held at a substantially constant voltage relative to the source terminal of the high-side or low-side transistor to reduce the drain-to-gate capacitance. In a particular embodiment, the conductive layer 1302 may be at substantially 0V relative to a corresponding source terminal, in which case the conductive layer 1302 may act as a virtual ground plane. This virtual ground plane may be at a different potential than the real ground of the application circuit, in case the source terminal of the corresponding transistor is connected to a switch node in the circuit. In another embodiment, a portion of conductive layer 1302 proximate to the high-side power transistor may be coupled to source region 1704 and another portion of conductive layer 1302 proximate to the low-side power transistor may be coupled to source region 1724.

According to the concepts described herein, an integrated circuit may be formed such that high-side and low-side power transistors are located in different portions of the same die. The buried conductive region may electrically connect the source of the high-side power transistor to the drain of the low-side power transistor. Parasitic resistance and inductance can be reduced because wire bonding between a die with a high-side power transistor and another die with a low-side power transistor is no longer required.

One particular benefit of reducing parasitic inductance between the high-side and low-side power transistors is a reduction in ringing of the switch or output node when switching between the high-side and low-side power transistors. During this transient, the parasitic inductance between the high-side and low-side power transistors reacts with the output capacitance of the low-side transistor to form a resonant circuit. This resonant circuit can produce an undesirable high frequency voltage swing on the output node of the circuit. These voltage swings can create undesirable voltage stress on the device, complicate the control circuitry, and reduce the overall power conversion efficiency of the voltage regulator. Embodiments described herein may achieve a reduction in parasitic inductance between high-side and low-side power transistors, thereby minimizing output node ringing. Furthermore, the remaining parasitics between the high-side and low-side power transistors are dominated by the resistance of the buried conductive layer, resulting in a more efficient attenuation of ringing on the output node.

By combining pairs of small high-side and low-side power transistors and then connecting multiple pairs of these transistors together in parallel to create a larger effective device, the parasitic resistance between the two transistor types can be reduced even more. If the average lateral distance between the high-side and low-side power transistors in these pairs is less than the thickness of the buried conductive layer, the current from the high-side transistor does not have to flow through the entire thickness of the buried conductive layer to reach the low-side transistor, thereby reducing the overall parasitic resistance.

Other embodiments may be used, as needed or desired. In a particular embodiment, the liner layer may be formed in a deep trench as a vertical isolation region similar to vertical isolation region 424 prior to forming a conductive structure similar to conductive structure 824. Further, the conductive structure of the high-side power transistor may be formed separately from the conductive structure of the low-side power transistor. The starting point for this process is after the formation of the semiconductor layer 304, the pad layer 306, and the stop layer 308, as shown in figure 3. A mask (not shown) is formed over the workpiece and a trench 2102 for the high-side power transistor is formed and extends completely through layers 304, 306, and 308 as shown in fig. 21. In another embodiment (not shown), the trench 2102 may extend mostly, but not completely, through the semiconductor layer 304. When trench 2102 is formed, the low side power transistor is covered by a mask. A semiconductor layer 2104 is formed along the exposed surface of the workpiece (including the stop layer 308 and within the trench 2102). The semiconductor layer 2104 has a thickness in the range of about 20 to 90 nm. Semiconductor layer 2104 may be p-type doped as it is formed, or may be subsequently doped to a doping concentration no less than about an order of magnitude lower than doped buried region 206. In this embodiment, the semiconductor layer 2104 is also formed over the location of the low-side power transistor.

Semiconductor layer 2104 is anisotropically etched and vertical isolation regions 2204 are formed, as shown in fig. 22. Semiconductor layer 2104 can be amorphous or polycrystalline as deposited. In this embodiment, the vertical isolation regions 2204 in the form of sidewall spacers perform substantially the same functions as previously described with respect to the vertical isolation regions 724. Semiconductor layer 2104 is over-etched so that the top of vertical isolation region 2204 is at or below the bottom of pad layer 306. This etch removes the semiconductor layer 2104 from where the low side power transistor is to be formed. In another embodiment (not shown), selective growth or other selective formation processes may be used to form the vertical isolation regions 2204. A selective process may form the semiconductor layer along exposed semiconductor surfaces, which in this particular embodiment are along the sidewalls and bottom of the trench 2102. In particular embodiments, such a semiconductor layer may be substantially monocrystalline. An anisotropic etch may be used to remove portions of the selectively formed semiconductor layer along the bottom of the trench 2102. The stop layer 308 substantially prevents the selectively formed semiconductor layer from being formed over the semiconductor layer 304 of the high-side and low-side power transistors.

Insulating sidewall spacers 2206 may be formed along the exposed surfaces in the trenches 2102. The insulating sidewall spacers 2206 may comprise an oxide, nitride, oxynitride or any combination thereof. The layer forming insulating sidewall spacers 2206 may be thermally grown or deposited, and this layer may be anisotropically etched to remove it from the bottom of trench 2102. If needed or desired, an etch may be performed to extend the trench 2102 closer to or further into the buried conductive region 102. In another embodiment, insulating sidewall spacer 2206 is omitted.

Conductive structure 2324 is formed in trench 2102 as shown in fig. 23. Conductive structure 2324 may be formed using any of the materials and techniques previously described for conductive structure 824.

In fig. 24, a sacrificial protective layer 2402 may be formed over the conductive structure 2324 of the high-side power transistor to protect the conductive structure 2324 and other features in the trench 2102 from the adverse effects of the formation of the corresponding conductive structure of the low-side power transistor. Sacrificial protective layer 2402 may have a different composition than conductive structure 2324, insulating spacers 2206, vertical isolation regions 2204, and semiconductor layer 304. If each of the conductive structures 2324, insulating spacers 2206, vertical isolation regions 2204, and semiconductor layer 304 comprise an oxide, a silicide, or predominantly silicon (i.e., not silicon oxide or silicon nitride), then sacrificial protective layer 2402 may comprise a nitride or oxynitride. In a particular embodiment, the protective layer 2402 and the stop layer 308 have substantially the same composition. The sacrificial protective layer 2402 may have a thickness in a range of about 5nm to about 30 nm.

After the sacrificial protective layer 2402 is formed, trenches 2422 and insulating spacers 2426 may be formed for the low side power transistor, as shown in fig. 24. Groove 2422 may be formed using any technique as described with respect to groove 2102. Grooves 2422 and 2102 can be formed using the same technique or different techniques. The insulating spacers 2426 may be formed using any materials, thicknesses, and techniques as described with respect to insulating spacer 2206. The insulating spacers 2426 and 2206 can be formed using the same composition or different compositions, substantially the same thickness or different thicknesses (width at the bottom), and the same formation technique or different formation techniques.

A conductive structure 2524 is formed in trench 2422 as shown in fig. 25. Conductive structure 2524 may be formed using any of the materials and techniques as previously described for conductive structure 824. Conductive structures 2324 and 2524 may be formed using the same composition or different compositions, substantially the same amount of recess or different amounts of recess in trenches 2102 and 2422, and the same formation technique or different formation techniques. The sacrificial protective layer 2402 may be removed and processing continues as previously described with respect to the formation of the conductive plug 1002 and the removal of the stop layer 308 and the liner layer 306 (see fig. 10).

In another embodiment, the order in which features are formed as described with respect to fig. 21-25 may be reversed. The processing at the location where the low-side power transistor is formed may be performed before the processing at the location where the high-side power transistor is formed. In this particular embodiment, the protective sacrificial layer 2402 will be formed over the location where the low-side power transistor is being formed, as opposed to the high-side power transistor.

In yet another embodiment, one or more bipolar transistors may be used in place of the field effect transistors. In this embodiment, the current carrying electrodes may include emitters and collectors instead of sources and drains, and the control electrodes may include bases instead of gate electrodes. The emitter of the high-side bipolar transistor may be electrically connected to the collector of the low-side bipolar transistor. If a buried collector is used, the buried collector may be patterned to allow for the creation of a suitably isolated connection to the buried conductive region 102.

Embodiments as described herein may include a polymer having less than about 10¹⁹ atoms/cm³The peak doping concentration of (a). If ohmic contact with the metal-containing material is needed or desired, a portion of such doped region may be locally doped to have at least about 10¹⁹atoms/cm³The peak doping concentration of (a). In a non-limiting embodiment, the buried doped region 206 may have a doping of less than about 10¹⁹ atoms/cm³The peak doping concentration of (a). If the conductive structure 824 comprises W or WSi, the portion of the buried doped region 206 near the conductive structure 824 (e.g., along the bottom of the trench 624) may be implanted to locally increase the peak doping concentration to at least about 10¹⁹ atoms/cm³To help form an ohmic contact between the buried doped region 206 and the conductive structure 824.

Many different aspects and embodiments are possible. Some of these aspects and embodiments are described below. After reading this specification, skilled artisans will appreciate that these aspects and embodiments are illustrative only, and do not limit the scope of the invention.

In a first aspect, an electronic device can include an integrated circuit, the electronic device including a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a major surface and an opposing surface, and the buried conductive region is closer to the opposing surface than to the major surface. The electronic device can also include a first doped region in the semiconductor layer, wherein the first doped region is closer to the major surface than to the opposing surface, and a first current carrying electrode of a first transistor includes the first doped region, wherein the first current carrying electrode is a source or an emitter and is electrically connected to the buried conductive region. The electronic device can also include a second doped region in the semiconductor layer, wherein the second doped region is closer to the major surface than to the opposing surface, and a second current carrying electrode of a second transistor includes the second doped region, wherein the second current carrying electrode is a drain or a collector and is electrically connected to the buried conductive region.

In an embodiment of the first aspect, the first and second transistors are both n-channel transistors or both p-channel transistors, the first current-carrying electrode is the source of the first transistor, and the second current-carrying electrode is the drain of the second transistor. In another embodiment, the electronic device further includes a first vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region and the first doped region or the second doped region. In a particular embodiment, the electronic device further includes a second vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region and the second doped region. The first vertical conductor is electrically connected to the buried conductive region and the first doped region, the first doped region is spaced apart from the second doped region, and the first vertical conductive structure is spaced apart from the second vertical conductive structure. In another particular embodiment, the first vertical conductive structure includes a first doped semiconductor region having the same conductivity type as the buried conductive region.

In another particular implementation of the first aspect, the electronic device further includes a second doped semiconductor region having a conductivity type opposite the buried conductive region, wherein the second doped semiconductor region extends through the semiconductor layer. In a more particular embodiment, the semiconductor layer is substantially monocrystalline and the second doped semiconductor region is polycrystalline. In an even more particular embodiment, the electronic device further includes a second vertical conductive structure extending through the semiconductor layer and electrically connected to the buried conductive region and the second doped region. In another particular embodiment, the electronic device further includes a first insulating liner between the second vertical conduction region and the semiconductor layer, a second insulating liner between the first vertical conduction region and the semiconductor layer, or first and second insulating liners.

In another more particular implementation of the first aspect, the second doped semiconductor region has at least approximately 1 x 10¹⁹ atoms/cm³And the semiconductor layer has a doping concentration of not more than about 1 x 10¹⁷ atoms/cm³Background doping concentration of (1). In another embodiment, each of the first transistor and the second transistor is a power transistor.

In a second aspect, a process of forming an electronic device including an integrated circuit may include: providing a substrate comprising a first semiconductor layer over a buried conductive region, wherein the first semiconductor layer has a major surface and an opposing surface, and the buried conductive region is closer to the opposing surface than to the major surface. The process may also include: a first doped region formed in the semiconductor layer and along the major surface of the first semiconductor layer, wherein the first doped region is part of a first current carrying electrode of a first transistor, and the first current carrying electrode is a source or emitter. The process may further comprise: forming a first vertical conductive structure extending through the first semiconductor layer; wherein, in the completed device, the buried conductive region, the first vertical conductive structure, and the first doped region are electrically connected to each other. The process may also include: a second doped region formed in the first semiconductor layer and along the major surface of the first semiconductor layer, wherein the second doped region is part of a second current carrying electrode of a second transistor, and the second current carrying electrode is a drain or collector. The process may further comprise: forming a second vertical conductive structure extending through the first semiconductor layer, wherein, in the completed device, the buried conductive region, the second vertical conductive structure, and the second doped region are electrically connected to one another.

In an embodiment of the second aspect, the process further comprises: a first trench is formed extending through the first semiconductor layer prior to forming the first vertical conductive structure therein, and a second trench is formed extending through the first semiconductor layer prior to forming the second vertical conductive structure therein. In a particular embodiment, forming the first semiconductor layer includes epitaxially growing a substantially single crystal semiconductor layer, forming the first vertical conductive region includes depositing a polycrystalline material, and forming the second vertical conductive region includes depositing a polycrystalline material. In another particular embodiment, the process further includes forming a first insulating liner in the second trench. In a more particular embodiment, the process further includes forming a second insulating liner in the first trench.

In another particular implementation of the second aspect, the process further includes forming a first doped semiconductor region along sidewalls of the first trench. The first doped semiconductor region has an opposite conductivity type as compared to the buried conductive region and a higher doping concentration than the first semiconductor layer. A first insulating liner is disposed between the first doped semiconductor region and the first vertical conductive region. In a more particular embodiment, forming the first doped semiconductor region includes depositing a second semiconductor layer along the exposed surfaces of the first trenches and anisotropically etching the second semiconductor layer to remove portions of the second semiconductor layer along the bottoms of the trenches and expose a portion of the buried conductive region.

In yet another particular embodiment of the second aspect, the process further includes implanting dopants into the first semiconductor layer to form an implanted doped semiconductor region in the first semiconductor layer. The dopant is of an opposite conductivity type as compared to the buried region, forming the first trench is performed after forming the implanted doped region, and forming the first vertical conductive region is performed such that the first vertical conductive region is formed in the first trench.

In another particular embodiment, the process further includes forming a doped semiconductor region, wherein the doped semiconductor region has an opposite conductivity type as compared to the buried conductive region and a higher doping concentration than the first semiconductor layer, and in the completed device, the doped semiconductor region is closer to an opposing surface of the buried conductive region and the first semiconductor layer than to a major surface of the first semiconductor layer. In a more particular embodiment, each of the buried conductive region, the first and second doped regions, and the semiconductor doped region has at least about 1 x 10¹⁹ atoms/cm³And the first semiconductor layer has a doping concentration of not more than about 1 x 10¹⁷ atoms/cm³Background doping concentration of (1). In another embodiment, the process further includes forming a horizontally oriented doped region adjacent the major surface and the second doped region, wherein the horizontally oriented doped region is a drift region of the second transistor.

Note that not all of the activities described above in the general description or the embodiments are required, that a portion of a specific activity may not be required, and that one or more further activities may be performed in addition to those described. Still further, the order in which activities are listed is not necessarily the order in which they are performed.

Certain features that are, for clarity, described herein in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, references to values specified in a range include each value within that range.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. The benefits, advantages, solutions to problems, and any feature(s) that may cause any benefit, advantage, or solution to occur or become more pronounced, however, are not to be construed as a critical, required, or essential feature or feature of any or all the claims.

The description and illustrations of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. The specification and drawings are not intended to serve as an exhaustive or comprehensive description of all the elements and features of apparatus and systems that utilize the structures and methods described herein. Separate embodiments may also be provided in combination in a single embodiment, and conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, references to values specified in a range include each value within that range. Many other embodiments may be apparent to a skilled artisan only after reading this specification. Other embodiments may be used and derived from the disclosure, such that a structural substitution, logical substitution, or another change may be made without departing from the scope of the disclosure. Accordingly, the present disclosure is to be considered as illustrative and not restrictive.

Claims (9)

1. An electronic device comprising an integrated circuit, comprising:

a buried conductive region;

a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a major surface and an opposing surface, and the buried conductive region is located closer to the opposing surface than to the major surface;

a high-side power transistor comprising a drain, wherein:

the drain includes a first doped region in the semiconductor layer, and

the first doped region is located closer to the major surface than to the opposite surface;

a low-side power transistor comprising a source, wherein:

the source electrode includes a second doped region in the semiconductor layer, and

the second doped region is located closer to the major surface than to the opposite surface;

a first vertical conductive structure extending through the semiconductor layer and electrically connected to and adjacent to the buried conductive region and electrically connected to and adjacent to the first doped region; and

a second vertical conductive structure extending through the semiconductor layer and electrically connected to and adjacent to the buried conductive region and electrically connected to and adjacent to the second doped region,

the first vertical conductive structure is spaced apart from the second vertical conductive structure.

2. The electronic device of claim 1, further comprising a third doped semiconductor region having an opposite conductivity type as compared to the buried conductive region, wherein the third doped semiconductor region extends through the semiconductor layer.

3. The electronic device of claim 1, wherein the electronic device further comprises an insulating liner between the second vertical conductive structure and the semiconductor layer.

4. An electronic device according to claim 1 or 3, wherein the electronic device further comprises a horizontally oriented doped region located adjacent to the major surface, wherein the horizontally oriented doped region is a drift region of the low side power transistor.

5. A process of forming an electronic device comprising an integrated circuit, the electronic device comprising a high-side transistor and a low-side transistor, the process comprising the steps of:

providing a substrate comprising a first semiconductor layer over a buried conductive region, wherein the first semiconductor layer has a major surface and an opposing surface, and the buried conductive region is located closer to the opposing surface than to the major surface;

forming a first vertical conductive structure extending through the first semiconductor layer;

forming a second vertical conductive structure extending through the first semiconductor layer;

a first doped region formed in the semiconductor layer and along the major surface of the first semiconductor layer, wherein the first doped region is part of a drain of the low-side transistor;

forming gate electrodes of the high-side transistor and the low-side transistor after forming the first doped region;

a second doped region formed in the first semiconductor layer and along the major surface of the first semiconductor layer after forming the gate electrode, wherein the second doped region is part of a source of the high-side transistor,

wherein, in the finished device:

the first doped region and the buried conductive region are electrically connected to each other via the first vertical conductive structure; and is

The second doped region and the buried conductive region are electrically connected to each other via the second vertical conductive structure.

6. The process of claim 5, further comprising the steps of:

forming a second trench through the first semiconductor layer prior to forming the second vertical conductive structure;

forming a doped semiconductor region along sidewalls of the second trench, wherein the doped semiconductor region has an opposite conductivity type and a higher doping concentration than the first semiconductor layer than the buried conductive region; and

forming an insulating liner in the second trench prior to forming the second vertical conductive structure.

7. The process of claim 6, wherein forming the doped semiconductor region comprises:

depositing a second semiconductor layer along the exposed surface of the second trench;

anisotropically etching the second semiconductor layer to remove a portion of the second semiconductor layer overlying along a bottom of the second trench and expose a portion of the buried conductive region.

8. The process of claim 5, 6 or 7, further comprising forming a horizontally oriented doped region located adjacent to the major surface, wherein the horizontally oriented doped region is a drift region of the low side transistor.

9. The process of claim 8, wherein each of the high-side transistor and the low-side transistor is a power transistor.