HK1160986B

HK1160986B - Electronic device including a buried insulating layer and a vertical conductive structure extending therethrough and a process of forming the same

Info

Publication number: HK1160986B
Application number: HK12101209.1A
Authority: HK
Inventors: G．H．罗切尔特; G．M．格里瓦纳; P．J．兹德贝尔
Original assignee: 半导体元件工业有限责任公司
Priority date: 2010-02-08
Filing date: 2012-02-08
Publication date: 2017-01-20

Description

Electronic device including buried insulator layer and vertical conductive structure passing through the buried insulator layer and method

Technical Field

The present invention relates to electronic devices and processes for forming electronic devices, and more particularly, to electronic devices including a buried insulating layer and a vertical conductive structure extending through the buried insulating layer and processes for forming the same.

Prior Art

Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are a common type of power switching device. The MOSFET includes a source region, a drain region, a channel region extending between the source and drain regions, and a gate structure disposed adjacent to the channel region. The gate structure includes a gate electrode layer disposed adjacent to and separated from the channel region by a thin dielectric layer.

When the MOSFET is in the on state, a voltage is applied to the gate structure to form an on channel region between the source and drain regions, which allows current to flow through the device. In the off state, any voltage applied to the gate structure is low enough so that no significant current flows through the channel of the transistor. During the off state, the device should withstand a high voltage between the source and drain regions.

In certain applications, a pair of power transistors may be used to allow the output to be switched between two different voltages. The output may be connected to the source of the high-side power transistor and to the drain of the low-side power transistor. The output will be at a voltage corresponding to the voltage on the drain of the high-side power transistor when the high-side power transistor is activated and the output will be at a voltage corresponding to the source of the low-side power transistor when the low-side power transistor is activated. In certain physical embodiments, the high-side power transistor and the low-side power transistor are typically separate transistors on separate dies, interconnected to each other by bond wires or other similar interconnects. The interconnect adds parasitic characteristics to the electronic device including the high-side and low-side power transistors, which is undesirable.

Drawings

The embodiments are explained by way of example and are not limited by the accompanying drawings.

Fig. 1 includes a circuit diagram of a portion of an electronic device.

Fig. 2 includes a cross-sectional view of a portion of a workpiece including a buried conductive region, a buried insulating layer, and a semiconductor layer.

Fig. 3 includes a cross-sectional view of the workpiece of fig. 2 after forming a pad layer, a stop layer, and etching trenches in the workpiece.

Fig. 4 includes a cross-sectional view of the workpiece of fig. 3 after forming vertical conductive structures within the trenches.

Fig. 5 includes a cross-sectional view of the workpiece of fig. 4 after forming a conductive plug over the vertical conductive structure.

Fig. 6 and 7 include cross-sectional views of the workpiece of fig. 5 after forming an implanted silk screen layer, horizontally-oriented doped regions, and drain regions within a portion of the workpiece where high-side and low-side power transistors are being formed.

Fig. 8 includes a cross-sectional view of the workpiece of fig. 6 and 7 after forming an insulating member.

FIG. 9 includes a cross-sectional view of the workpiece of FIG. 8 after forming a patterned conductive layer.

FIG. 10 includes a cross-sectional view of the workpiece of FIG. 9 after forming insulating members from the patterned conductive layer and forming conductive electrodes.

FIG. 11 includes a cross-sectional view of the workpiece of FIG. 10 after forming sacrificial spacers and sacrificial features.

FIG. 12 includes a cross-sectional view of the workpiece of FIG. 11 during an implantation step after the sacrificial spacers have been removed.

FIG. 13 includes a cross-sectional view of the workpiece of FIG. 12 after removal of the sacrificial members and formation of insulating spacers.

FIG. 14 includes a cross-sectional view of the workpiece of FIG. 13 after forming a channel region and a deep body dopant region.

FIG. 15 includes a cross-sectional view of the workpiece of FIG. 14 after forming gate electrodes, source extension regions, and body regions.

Fig. 16 includes an enlarged view of the workpiece at the location shown in fig. 15.

FIG. 17 includes a cross-sectional view of the workpiece of FIG. 15 after forming insulating spacers and heavily doped source regions.

Fig. 18 includes an enlarged view of the workpiece at the location shown in fig. 17.

FIG. 19 includes a cross-sectional view of the workpiece of FIG. 17 after forming another set of spacers, etching portions of the heavily doped source regions, and forming heavily doped body contact regions.

Fig. 20 includes an enlarged view of the workpiece at the location shown in fig. 19.

FIG. 21 includes a cross-sectional view of the workpiece of FIG. 19 after forming silicide features.

Fig. 22 and 23 include cross-sectional views of the workpiece of fig. 21 after forming a first level interconnect for the transistor structure of the high-side transistor and the low-side transistor.

Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of various embodiments of the present invention.

Detailed Description

The following description, in conjunction with the accompanying drawings, is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This emphasis is provided to assist in describing the invention and should not be construed as limiting the scope or applicability of the invention. However, other embodiments may be used based on the teachings disclosed in this application.

As used herein, the terms "horizontally oriented" and "vertically oriented" with respect to a region or structure refer to the primary direction of current flow through such region or structure. More specifically, current may flow through a region or structure in a vertical direction, a horizontal direction, or a combination of vertical and horizontal directions. A region or structure will be referred to as vertically oriented if current flows through such region or structure in a vertical direction or a combination of directions in which the vertical component is greater than the horizontal component. Similarly, if current flows through a region or structure in a horizontal direction or a combination of directions in which the horizontal component is greater than the vertical component, such region or structure will be referred to as horizontally oriented.

The term "metal" or variants thereof is meant to include elements within any of groups 1 to 12, elements within groups 13 to 16, elements defined along or below the atomic numbers 13(Al), 31(Ga), 50(Sn), 51(Sb) and84 (Po). The metal does not include Si or Ge.

The terms "normal operation" and "normal operating state" refer to the condition under which an electronic component or device is designed to operate. These conditions may be obtained from a data table or other information regarding voltage, current, capacitance, resistance, or other electronic parameters. Thus, normal operation does not include operating an electronic component or device well beyond its design limits.

The term "power transistor" means a transistor designed to operate normally to maintain a difference of at least 10V before the source and drain or collector and emitter of the transistor. For example, when the transistor is in an off state, 10V is maintained between the source and drain without junction breakdown or other undesirable conditions.

The terms "comprises," "comprising," "including," "includes," "including," "has," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that comprises a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. Further, unless expressly stated to the contrary, "or" means an inclusive or and not an exclusive or. For example, condition a or B is satisfied by any one of the following: a is true (or present) and B is false (or not present), a is false (or not present) and B is true (or present), and both a and B are true (or present).

Furthermore, the use of "a" or "an" is used to describe elements and components described herein. This is done merely for convenience and to give a general sense of the scope of the invention. This description should be read to include one or at least one and the singular also includes the plural and vice versa unless it is meant otherwise. For example, when a single item is described herein, more than one item may be used in place of a single item. Similarly, where more than one item is described herein, a single item may be substituted for the more than one item.

Members of the family corresponding to columns in the periodic Table of the elements use the convention "New symbols", as in the CRCHandbooko of chemistry and Physics, 81^stEdition (2000-.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The materials, methods, and examples are illustrative only and not intended to be limiting. To the extent not described herein, many details regarding specific materials and processing acts are conventional and may be found in textbooks and other sources within the semiconductor and electronic arts.

Fig. 1 includes a circuit diagram of a portion of an electronic device 10. In the embodiment shown in fig. 1, electronic device 10 may include a power switching circuit. Electronic device 10 includes a transistor 12, where a drain region of transistor 12 is coupled to, for example, V_DAnd the source region of transistor 12 is coupled to, for example, V_OUTThe terminal of (1). Electronic device 10 also includes a transistor 14, where a drain region of transistor 14 is coupled to a source of transistor 12, and a source region of transistor 14 is coupled to, for example, V_SThe terminal of (1). The gate electrodes of transistors 12 and 14 may be coupled to control terminals 162 and 164 of control unit 16. In particular embodiments, control unit 16 may be configured such that only one of transistors 12 and 14 is enabled at any particular point in time. When transistor 12 is enabled (transistor 14 is disabled), V_OUTWill be substantially V_DWhen transistor 14 is enabled (transistor 12 is disabled), V_OUTWill be substantially V_S. Can use the control sheetElement 16 determines when V_OUTWill be driven from V_SSwitch to V_DAnd from V_SSwitch to V_DAnd vice versa. In a more specific embodiment, transistors 12 and 14 may be power switching transistors in a high frequency voltage regulator.

The physical structures corresponding to transistors 12 and 14 and the processes for forming the physical structures described above will be described below. In the following description, transistor 12 may be referred to as a high-side power transistor and transistor 14 may be referred to as a low-side power transistor. Much of the description will focus on the physical structure forming the high-side power transistor; however, the formation of the low side power transistor is similar. In one embodiment, transistors 12 and 14 will be part of the same integrated circuit. In a particular embodiment, control unit 16 is located on the same integrated circuit as transistors 12 and 14.

Fig. 2 includes a cross-sectional view of a portion of a workpiece 200 including a buried conductive region 202, a buried insulating layer 204, and a semiconductor layer 206. Buried conductive region 202 may include an element of group 14 (i.e., carbon, silicon, germanium, or any combination thereof) and may be heavily doped N-type or P-type. In this specification, heavily doped means at least about 1x10¹⁹Atom/cm³Is less than about 1x10, lightly doped means¹⁹Atom/cm³The peak dopant concentration of (a). Buried conductive region 202 may be a portion of a heavily doped substrate (e.g., a heavily N-type doped wafer) or may be a buried doped region disposed over a substrate of the opposite conductivity type, or may be a buried doped region located over another buried insulating layer (not shown) disposed between the substrate and buried conductive region 202. In one embodiment, buried conductive region 202 is heavily doped with an N-type dopant, such as phosphorus, arsenic, antimony, or any combination thereof. In one embodiment, the buried conductive region 202 includes arsenic or antimony if the diffusion of the buried conductive region 202 is to be kept low, and in one embodiment, the buried conductive region 202 includes antimony to reduce self-oxidation (as compared to arsenic) during formation of a subsequently formed semiconductor layerThe doping level. The buried conductive region 202 will serve to electrically connect the source of the high-side power transistor and the drain of the low-side power transistor together and will be part of the output node of the electronic device.

A buried insulator layer 204 is disposed over the buried conductive region 202. During normal operation, the buried insulator layer 204 helps to isolate the voltage on the buried conductive region 202 from a portion of the semiconductor layer 206. The buried insulating layer 204 may include an oxide, a nitride, or an oxynitride. The buried insulator layer 204 may include one film or a plurality of films having the same or different compositions. The thickness of the buried insulator layer 204 may range from at least about 0.2 microns or at least about 0.3 microns. Further, the thickness of the buried insulator layer may be no greater than about 5.0 microns or no greater than about 2.0 microns. In one embodiment, the thickness of the buried insulator layer 204 ranges from about 0.5 microns to about 0.9 microns.

A semiconductor layer 206 is disposed over the buried insulating layer 204 and has a main surface 205 where transistors and other electronic elements (not shown) are formed. The semiconductor layer 206 may include a group 14 element (i.e., carbon, silicon, germanium, or any combination thereof) and any of the dopants described with respect to the buried conductive region 202 or dopants of the opposite conductivity type. In one embodiment, semiconductor layer 206 is a lightly doped N-type or P-type epitaxial silicon layer having a thickness in a range from about 0.2 microns to about 5.0 microns and a doping concentration no greater than about 1x10¹⁷Atom/cm³In another embodiment, the doping concentration is at least about 1x10¹⁴Atom/cm³. The semiconductor layer 206 may be disposed over the entire workpiece 200. The dopant concentration within the formed semiconductor layer 206 or within the semiconductor layer 206 prior to selectively doping regions within the semiconductor layer 206 will be referred to as the background dopant concentration.

Workpiece 200 may be formed using various fabrication techniques. In one embodiment, wafer bonding techniques may be used. For example, the buried conductive region 202 and the semiconductor layer 206 may be portions of different substrates that are bonded together. The oxide may be thermally grown from one or both substrates. In one particular embodiment, the buried conductive region 202 may include a low doping near the surface from which the oxide is grown. The doping concentration within the buried conductive region 202 may be slightly higher due to dopant accumulation at the interface with the oxide. Thus, the buried conductive region 202 may be heavily doped except for the portion near the oxide interface, which may have a very low dopant concentration separate from the oxide layer. After bonding, a large portion of one of the substrates may be removed to leave the semiconductor layer 206. An oxide layer thermally grown from one or both substrates may form at least a portion of the buried insulator layer 204. In another embodiment, buried conductive region 202 may be in the form of a heavily doped wafer. A semiconductor layer 206 may be epitaxially grown from the buried conductive region 202. An oxygen implant and anneal may be performed to form the buried insulator layer 204 from a portion of the buried conductive region 202, the semiconductor layer 206, or both. After reading this description, one skilled in the art will understand that other techniques may be utilized to form the workpiece 200.

Referring to fig. 3, a pad layer 302 and a stop layer 304 (e.g., a polish stop layer or an etch stop layer) are sequentially formed over the semiconductor layer 206 using a thermal growth technique, a deposition technique, or a combination thereof. Each of the pad layer 302 and the stop layer 304 may include an oxide, a nitride, an oxynitride, or any combination thereof. In one embodiment, the pad layer 302 has a different composition than the stop layer 304. In one embodiment, the pad layer 302 comprises an oxide and the stop layer 304 comprises a nitride.

A patterned mask layer (not shown) is formed over the stop layer 304. The buried insulator layer 204 and the trench 322 in the semiconductor layer 206 are formed where a vertical conductive structure is to be formed. In one embodiment, exposed portions of the buried insulator layer 204, the semiconductor 206, the stop layer 304, and the pad layer 302 are removed. The structure shown in the embodiment of fig. 3 is formed using an anisotropic etching technique. In another embodiment, the buried insulator layer 204 is not substantially removed, and in another embodiment, the buried insulator layer 204 is removed to substantially all or only a portion of the thickness disposed below the opening. In one particular embodiment, the width of each trench 322 is at least about 0.05 microns or about 0.1 microns, and in another particular embodiment, the width of each trench 322 is no greater than about 2 microns or about 1 micron. The patterned mask layer may be removed after forming trenches 322.

Insulating spacers 324 may be formed within trenches 322. The insulating spacers 324, which may also be referred to as insulating liners, may help to electrically insulate the semiconductor layer 206 from vertical conductive structures that will be subsequently formed within the trenches 322. In the illustrated embodiment, a thermal oxidation may be performed to form the insulating spacers 324. In another embodiment (not shown), insulating spacers may be conformally deposited and the insulating layer anisotropically etched to form the insulating spacers. The width of the insulating spacers 324 ranges from about 20 nanometers to about 200 nanometers.

Fig. 4 includes the drawing after extending the trenches and forming vertical conductive structures 422. Any remaining insulating material (e.g., oxide) along the bottom of trenches 322 may be removed, as shown in fig. 3, trenches 322 may extend into buried conductive region 202 to form trench extensions 402. In one embodiment, the trench extension 402 may enter the buried conductive region 202 by at least about 0.2 microns, and in another embodiment, the trench extension 402 may enter the buried conductive region 202 by at least about 0.3 microns. In another embodiment, trench extension 402 may be no greater than approximately 5.0 microns, and in another embodiment, trench extension 402 may be no greater than approximately 2.0 microns. In another embodiment, the trench extension may be deeper or shallower than described above. Removal of the insulating material and formation of trench extensions 402 may be accomplished using an anisotropic etch technique.

A conductive layer is formed over stop layer 304 and within trench 322, which in one particular embodiment substantially fills trench 322. The conductive layer may be polycrystalline and comprise a metal-containing or semiconductor-containing material. In one embodiment, the conductive layer may comprise a heavily doped semiconductor material, such as amorphous silicon or polysilicon. In another embodiment, the conductive layer includes a plurality of films, such as an adhesive film, a barrier film, and a conductive filling material. In one particular embodiment, the adhesion film may include a refractory metal such as titanium, tantalum, tungsten, and the like; the barrier film may comprise a refractory metal nitride, such as titanium nitride, tantalum nitride, tungsten nitride, and the like, or a refractory metal-semiconductor-nitride, such as TaSiN; and the conductive fill material may comprise tungsten or tungsten silicide. In a more specific embodiment, the conductive layer may comprise Ti/TiN/WSi. The number of film(s) and the selection of the components of those film(s) depends on the electrical properties, the temperature of the subsequent heating cycle, other criteria, or any combination thereof. The refractory metal and refractory metal-containing compound may be subjected to high temperatures (e.g., the refractory metal may have a melting point of at least 1400 ℃), may be conformally deposited, and has a low bulk resistivity compared to heavily doped N-type silicon. After reading this specification, those skilled in the art will be able to determine the composition of the conductive layer that meets their needs or meets the desires for a particular application. During the formation of the conductive layer, voids 424 may be formed within trenches 322. If formed, the void 424 is generally disposed in a region near the buried insulator layer 204. Thus, in the embodiment shown in fig. 4, substantially all voids 424 are disposed at a height spaced apart from the height of major surface 205 of semiconductor layer 206. Specifically, substantially all of voids 424 are configured at a height no greater than about one-half of the overall thickness of semiconductor layer 206.

As shown in the embodiment of fig. 4, the portion of the conductive layer disposed over the stop layer 304 is removed, thereby forming a vertical conductive structure 422 within the trench 322. The removal may be accomplished using chemical mechanical polishing or blanket etching techniques. The stop layer 304 may function as a polish stop layer or an etch stop layer. Polishing or etching may continue for a relatively short time after the stop layer 304 is reached to account for non-uniformities in the thickness of the conductive layer on the workpiece, non-uniformities in the polishing or etching operation, or any combination thereof. If needed or desired, a continuation of the etching or other removal operation may be used to further recess the vertical conductive structures 422 into the trenches 322, as indicated by arrows 426 in fig. 4. The recess may allow a subsequently formed source region of the high-side transistor structure and a drain region of the low-side transistor structure to be electrically connected to the vertical conductive structure 422. When in the form of a completed electronic device, the combination of the vertical conductive structure 422 and the buried conductive region 202 electrically connects the source of the high-side power transistor to the drain of the low-side power transistor.

Referring to fig. 5, although a portion of the stop layer 304 (not shown in fig. 5) is present, the pad layer 302 is etched and a portion of the stop layer 304 is undercut to expose a portion of the semiconductor layer 206 near the trench 322. At this point in the embodiment shown in fig. 4, an additional etch of the trench fill material may be performed, exposing an upper surface of trench liner material 324. Portions of the stop layer 304 are then removed. Conductive plugs 522 are formed within the trenches that help electrically connect the vertical conductive structures 422 to doped regions that will be subsequently formed within the semiconductor layer 206. Conductive plug 522 may be formed using any material and method for forming vertical conductive structure 422, except that conductive plug 522 may or may not be recessed within trench 322. Conductive plug 522 and vertical conductive structure 422 may comprise the same material or different materials and may be formed using the same technique or different techniques. The combination of conductive plug 522 and vertical conductive structure 422 may form a vertically oriented conductive region 542. Hereinafter, vertically oriented conductive region 542 may refer to vertical conductive structure 422, conductive plug 522, or a combination of vertical conductive structure 422 and conductive plug 522. At this point in the process, the pad layer 302 may be removed.

Fig. 6 and 7 show the workpiece after forming the implanted silk screen layer 602, the horizontally oriented doped region 622, and the drain region 624. Fig. 6 includes a partial transistor structure for the high-side power transistor 12 and fig. 7 includes a partial transistor structure for the low-side power transistor 14. Implanted silk layer 602 is formed over major surface 205 and may comprise an oxide, nitride, or oxynitride and may have a thickness in the range of about 2 nanometers to about 90 nanometers. The implanted silk screen layer 602 may be formed by a thermal growth technique or a deposition technique.

In the embodiment shown in fig. 6 and 7, the horizontally oriented doped region 622 may be formed over substantially all of the regions forming the transistor structure for the high-side and low-side power transistors. Within the power transistor, the horizontally oriented doped region 622 may be a major portion of a drift region that forms the power transistor. In a normal operating state, charge carriers (e.g., electrons) or current flow primarily in a horizontal direction through the horizontally oriented doped region 622. If the integrated circuit includes a control unit 16, a mask layer (not shown) may be formed to protect all or part of the semiconductor layers of the electronic components that are forming the control unit 16. The horizontally oriented doped region 622 may have less than about 1x10¹⁹Atom/cm³And a dopant concentration of at least about 1x10¹⁶Atom/cm³The depth of the horizontally oriented doped region 622 may be less than about 0.9 microns in one embodiment, and less than about 0.5 microns in another embodiment.

A masking layer (not shown) may be formed and patterned to define an opening over the portion of semiconductor layer 206 where drain region 624 is formed. In fig. 6, a drain region 624 for the high-side transistor 12 is formed within the semiconductor layer 206. The drain region 624 includes a relatively higher dopant concentration than the horizontally oriented doped region 622. Drain region 624 may have a thickness of at least about 1x10¹⁹Atom/cm³The depth of the drain region 624 may be less than about 0.9 microns in one embodiment, and less than about 0.5 microns in another embodiment.

In fig. 7, the drain region of the low side transistor 14 may comprise an upper portion of a vertically oriented conductive region 542. In one embodiment, the upper portion may correspond to conductive plug 522 in fig. 5. Thus, the masking layer may completely cover the semiconductor layer 206 of the transistor of the low side power transistor 14 being formed. In another embodiment (not shown), an opening may be formed adjacent to the vertically oriented conductive region 542 as shown in fig. 7, and the portion of the semiconductor layer 206 below the opening may be doped to form a drain region similar to drain region 624.

In one embodiment, the horizontally oriented doped region 622 may be formed before the drain region 624. In another embodiment, the horizontally oriented doped region 622 may be formed after the drain region 624.

Fig. 8 includes a diagram after forming an insulating feature 802 over drain region 624. Although not shown in fig. 8, the insulating member 802 (fig. 7) is also formed over the vertically oriented conductive region 542 for the low side transistor 14, while the drain region of the transistor structure for the low side power transistor 14 is formed adjacent to the vertically oriented conductive region 542. The insulating feature 802 can help reduce capacitive coupling between the drain region and a subsequently formed conductive electrode and increase the breakdown voltage between the drain region 624 and a subsequently formed conductive electrode. The insulating member 802 may include one insulating layer or a plurality of insulating layers. In the embodiment shown in FIG. 8, insulating layers 812 and 814 are formed continuously over the workpiece, where insulating layers 812 and 814 have different compositions. For example, the insulating layer 812 may include nitride and the insulating layer 814 may include oxide. The insulating layer 814 can help reduce capacitive coupling and the insulating layer 812 can be an etch stop during formation of the drain contact. The thickness of the insulating layer 812 may range from about 20 nanometers to about 90 nanometers, and the thickness of the insulating layer 814 may range from about 50 nanometers to about 500 nanometers.

A mask layer (not shown) may be formed over the insulating layer 814 and the insulating layer 814 patterned to include mask features configured over portions of the transistor structure where the drain regions have been formed. Insulating layer 814 can be etched to provide a tapered profile and insulating layer 812 can be etched with or without a tapered profile. The mask layer can be removed after etching the insulating layer 814 and before or after etching the insulating layer 812.

In other embodiments, the tapered edges of insulating layer 814 can be formed using various techniques. In one embodiment, the composition of the insulating layer 814 can be varied during deposition or between depositions. For example, the insulating layer 814 may include a plurality of insulating films having different compositions. In another embodiment, a dopant, such as phosphorus, may be incorporated at an increased concentration during deposition of the latter portion. In yet another embodiment, the stress within the insulating layer 814 can be varied by varying deposition parameters (e.g., rf power, pressure, etc.) even though the composition is substantially the same throughout the thickness of the insulating layer 814. In another embodiment, a combination of the above may be used. Specific etching techniques for insulating layer 814 may include: isotropically etching the insulating layer 814; alternately etching a portion of the insulating layer 814 and etching the sidewall edges of the upper mask features, etching another portion of the insulating material and etching the sidewall edges of more upper mask features, and so on; utilizing a differential composition (doped oxide etches faster than undoped oxide etches); or any combination thereof.

In fig. 9, a conductive layer 902 is deposited over the insulating member 802 and patterned to form an opening (e.g., opening 904) at a location that will subsequently result in a drain contact structure to the drain region 624 for the transistor structure of the high-side power transistor 12. The conductive layer 902 comprises a conductive material or can be made conductive, for example, by doping. More specifically, the conductive layer 902 may include a doped semiconductor material (e.g., heavily doped amorphous silicon, polysilicon, etc.), a metal-containing material (e.g., a refractory metal nitride, a refractory metal silicide, etc.), or any combination thereof. The conductive layer 902 has a thickness ranging from about 0.05 microns to about 0.5 microns. In a particular embodiment, the conductive layer 902 will be used to form a conductive electrode.

Fig. 10 includes an insulating feature 1002 formed over the drain region 624 and a portion of the horizontally oriented doped region 622. The insulating member 1002 may be formed by forming one or more patterned insulating layers. In the embodiment shown in fig. 10, insulating layer 1012 and insulating layer 1014 are deposited over conductive layer 902. The insulating layers 1012 and 1014 may comprise an oxide, a nitride, or any oxynitride, and in one particular embodiment, have different compositions from each other. For example, the insulating layer 1012 may include an oxide, and the insulating layer 1014 may include a nitride. The thickness of the insulating layer 1012 ranges from about 0.2 microns to about 2.0 microns and the thickness of the insulating layer 1014 ranges from about 20 nanometers to about 900 nanometers.

A mask layer (not shown) is formed over the insulating layer 1014 and the insulating layer 1014 is patterned to form mask features configured over the insulating layer 1014 where the insulating features 1002 are formed. Portions of the conductive layer 902 and insulating layers 1012 and 1014 are patterned and the mask features are removed. The patterning of the conductive layer 902 forms separate conductive electrodes 1032 for the high-side power transistor 12 and the low-side power transistor 14. The conductive electrode 1032 for the high-side power transistor 12 will be electrically connected to the source region of the subsequently formed high-side power transistor 12, and the conductive electrode 1032 for the low-side power transistor 14 (not shown in fig. 10) will be electrically connected to the source region of the subsequently formed low-side power transistor 14.

Insulating spacers 1022 are formed along the sidewalls of insulating layers 1012 and 1014 and conductive electrode 1032. In one particular embodiment, the insulating spacers 1022 comprise nitride, and the insulating spacers 1022 are formed by depositing a nitride layer to a thickness in the range of approximately 20 to 90 nanometers and anisotropically etching the nitride layer to form the insulating spacers 1022. The openings 1042 are configured over portions of the semiconductor layer 206 where source and channel regions will be formed.

Fig. 11 includes sacrificial features 1122 and sacrificial spacers 1102 formed within openings 1042. The width of sacrificial spacer 1102 corresponds to the width of the doped region to be formed at least partially within the horizontally oriented doped region 622. The importance of the subsequently formed doped regions will be described later in this specification. The width of sacrificial spacers 1102 (hereinafter "spacer width") measured at the base of sacrificial spacers 1102 may be at least about 0.11 times the depth of the horizontally-oriented doped regions 622. The spacer width may be no greater than about 5 times the depth of the horizontally oriented doped region 622. In one embodiment, the spacer width may range from about 0.3 to about 2 times the depth of the horizontally-oriented doped region 622. In another embodiment, the spacer width is at least about 0.05 microns, and in yet another embodiment, the spacer width is no greater than about 0.3 microns.

The sacrificial member 1122 is disposed at a portion of the opening 1042 proximate to the horizontally oriented doped region 622. Sacrificial feature 1122 has a thickness sufficient to substantially prevent doping of the underlying regions when doping is performed after sacrificial spacer 1102 is removed. In one embodiment, the sacrificial member 1122 has a thickness of at least about 100 nanometers. In another embodiment, the sacrificial member 1122 may fill approximately 10 to 70 percent of the depth of the opening 1042. With sacrificial spacer 1102 selectively removed, sacrificial member 1122 does not cover the entire top of sacrificial spacer 1102.

Sacrificial spacer 1102 has a different material than insulating layer 1014, insulating spacers 1022 of insulating component 1002, and sacrificial component 1122. The sacrificial feature 1122 has a different material than the insulating spacers 1022 and insulating layer 1014 of the insulating feature 1002.

In a particular embodiment, the insulating layer 1014 and the insulating spacers 1022 comprise nitride, the insulating spacers 1022 comprise amorphous or polycrystalline silicon, and the sacrificial member 1122 comprises an organic resist material. As previously discussed, the insulating spacers 1022 are formed by depositing a layer comprising amorphous or polycrystalline silicon to a thickness corresponding to the width of the spacers and anisotropically etching the layer. The sacrificial member 1122 may be formed by an organic resist material covering over the workpiece and within the opening 1042. The organic resist material can be etched back, leaving the sacrificial member 1122. In one particular embodiment, the organic resist material may be etched with endpoint detection of the detection arrangement of the insulating layer 1014, the insulating spacers 1022, or the sacrificial member 1122. Timed etches may be used to achieve a desired thickness of the sacrificial member 1122.

In another embodiment, the composition of sacrificial features 1122 or sacrificial spacers 1102 may be varied. For example, sacrificial component 1122 or sacrificial spacer 1102 may comprise a metal-containing material. For example, sacrificial component 1122 or sacrificial spacer 1102 may comprise tungsten. In yet another embodiment, the sacrificial member 1122 may comprise an oxide. For example, heavily doped non-dense deposited oxides have a higher etch rate than thermal oxides or dense oxides made of tetraethylorthosilicate.

The sacrificial component 1122 may be reflowed if needed or desired. Reflow may be performed to reduce the likelihood of implant shadowing from portions of sacrificial member 1122 disposed over portions of sacrificial spacer 1102.

Fig. 12 includes a workpiece diagram during the doping action that forms doped regions 1222. The doping action may be performed as an implant. In one embodiment, ion implantation (as indicated by arrows 1202) is directed at the exposed surface of the workpiece at a tilt angle of substantially 0 ° (i.e., substantially perpendicular to the major surface 205 of the semiconductor layer 206). In another embodiment, other angles may be used, and the workpiece may be rotated during or between implantation portions to reduce the effects of shadowing caused by the insulating member. If the channel is considered, the implantation may be performed with a tilt angle of about 7 °. Implantation may be performed during 4 portions, wherein the workpiece is rotated by approximately 90 ° between each portion.

The dopant concentration of doped region 1222 is greater than the dopant concentration of the horizontally oriented doped region 622. In one embodiment, the dopant concentration of doped region 1222 is no greater than about 9 times the dopant concentration of horizontally oriented doped region 622. In a particular embodiment, the dopant concentration of doped region 1222 ranges from about 2 to about 5 times the dopant concentration of horizontally oriented doped region 622. In another embodiment, when using an infusion, the dose may range from about 2x10¹²Ion/cm²To about 2x10¹³Ion/cm²。

The depth of the doped region 1222 may not necessarily have a particular limitation. In one embodiment, the doped region 1222 can be deeper than the horizontally oriented doped region 622 by no more than about 0.2 microns. If the doped regions 1222 are deeper, they may interfere with subsequently formed deep implant regions. Doped region 1222 may be deeper if no deep implant regions are formed. In another embodiment, the doped region 1222 may have a depth corresponding to the main current flowing through the transistor structures of the high-side and low-side power transistors 12 and 14. During normal operation, if the electrons flowing through the channel region are located primarily within 0.05 microns of the major surface at the drain side of the channel region, the depth of doped region 1222 may be about 0.05 microns deep. In another embodiment, the depth of the doped region 1222 may range from about 0.5 to about 2 times the depth of the horizontally oriented doped region 622. In yet another embodiment, the depth of the doped region 1222 may range from about 0.5 to about 2 times the width of the sacrificial spacer 1102.

The implant energy may vary based on the selected dopant species. For example, when the implanted species is P⁺(phosphorus ions), the energy range may be about 40keV to about 150keV, when the implant species is As⁺The energy range may be from about 100keV to about 350 keV. If the high-side power transistor and the low-side power transistor are P-channel transistors (instead of N-channel transistors), then when the implant species is B⁺The energy range may be about 15keV to about 50keV when the implant species is BF₂ ⁺The energy range may be about 50keV to about 180 keV.

After the doped regions 1222 are formed, the sacrificial features 1122 may be removed. The width of doped region 1222 may be any width dimension described above with respect to the spacer width of sacrificial spacer 1102.

Fig. 13 includes a diagram after another set of insulating spacers is formed. The insulating spacers cover the doped regions 1222 so that they are not counter-doped when a channel implant is subsequently performed. Thus, the insulating spacers may have any of the width dimensions described above with respect to the spacer width of sacrificial spacers 1102. In a particular embodiment, the depth of the insulating spacers may range from about 0.8 to about 1.2 times the width of the doped region 1222. Insulating member 1302 is substantially the same as insulating member 1002 with the addition of an insulating spacer. To simplify fig. 13, the combination of the insulating spacers 1022 and another group of insulating spacers is shown as insulating spacers 1304. The insulating spacer 1304 may comprise a different material than the injection silk screen layer 602. In a particular embodiment, the insulating spacers 1304 may comprise nitride. After forming the insulating member, insulating member 1302 defines an opening 1306.

Figure 14 includes forming a deep body doped region 1404 and a channel region 1402 under the opening 1306. Channel region 1402 is formed adjacent to major surface 205 of semiconductor layer 206, while deep body doped region 1404 is remote from major surface 205. In contrast to avalanche breakdown between the drain region 624 and the channel region 1402, the deep body doped region 1404 may provide an alternative channel during avalanche breakdown between the drain region 624 and the deep body doped region 1404. Thus, if avalanche breakdown occurs involving drain region 624, current flows through deep body doped region 1404 in preference to channel region 1402. Thus, there is little probability that channel region 1402 will be permanently altered if avalanche breakdown occurs. The depth and concentration of the deep body doped region 1404 may be related to the depth and concentration of the channel region 1402.

If the depth of the deep body doped region 1404 is shallow, the current flowing during avalanche breakdown may comprise a portion of the channel region 1402. More specifically, if the deep body dopant region 1404 is deep at its maximum depth, avalanche breakdown between the drain region 624 and the channel region 1402 will occur, and thus the deep body dopant region 1404 will not be able to effectively protect the channel region 1402. In one embodiment, the peak concentration of the deep body doped region 1404 is at least about 0.1 microns deeper than the peak concentration of the channel region 1402, and in another embodiment, the peak concentration of the deep body doped region 1404 is no more than about 0.9 microns deeper than the peak concentration of the channel region 1402. In another embodiment, the peak concentration of the deep body doped region 1404 ranges from about 0.6 microns to about 1.1 microns below the major surface 205.

In one embodiment, the deep body doped region 1404 has a greater dopant concentration than the channel region 1402. In a particular embodiment, the peak concentration of the deep body doped region 1404 may range from about 2 to about 10 times the peak dopant concentration of the channel region 1402.

The deep body doped regions 1404 may have a width wider than the width of the openings 1306 between the insulating members 1302. The deep body doped region 1404 may be formed by implantation, which may be characterized by a projected range (Rp) and a spread (Δ Rp). During implantation, Δ Rp may be used to approximate lateral erosion of dopants within semiconductor layer 206. Thus, a significant portion of the deep body doped region 1404 is disposed under the doped region 1222.

The deep body doped region 1404 may be formed using one implant or a combination of implants. The deep body doped region 1404 may or may not contact the buried insulator layer 204. As the depth of the deep body doped region 1404 increases, the current during avalanche breakdown can spread over a larger area. In one particular embodiment, the deep body doped region 1404 may be spaced apart from the buried insulator layer 204 to reduce capacitive coupling with the buried conductive region 202. In another embodiment, the deep body doped region 1404 may be in contact with the buried insulating layer 204 in order to suppress parasitic field effect transistors, wherein the gate dielectric comprises the buried insulating layer 204. The dose may range from about 5x10 for one implant or for the (implant combined) implant with the lowest Rp¹³Ion/cm²To about 5x10¹⁴Ion/cm²。

Can pass through the dosage range of about 5x10¹²Ion/cm²To about 5x10¹³cm²The energy may be selected to achieve an Rp in the range of about 0.05 microns to about 0.3 microns.

The deep body doped region 1404 may be formed before or after the channel region 1402. In a specific embodiment, deep body doped region 1404 is formed and the portion of implanted silk layer 602 exposed within opening 1306 is removed. Another implanted silk screen layer (not shown) may be formed prior to forming channel region 1402. The other implanted silk screen layer may be an oxide or a nitride. The other infusion silk screen layer may be thinner than infusion silk screen layer 602. In a particular embodiment, another implanted silk screen layer is thermally grown to a thickness in a range of about 11 nanometers to about 50 nanometers. Ions for the channel region 1402 may be implanted through another screen implant layer.

Fig. 15 includes a workpiece diagram after forming gate dielectric layer 1502, gate electrode 1522, insulating layer 1524 along exposed surfaces of gate electrode 1522, source extension regions 1542 and body regions 1562. Exposed portions of implanted silk screen layer 602 and other implanted silk screen layer(s), if present, are removed by etching and gate dielectric layer 1502 is formed over the exposed surfaces along the bottom of opening 1306. In a particular embodiment, gate dielectric layer 1502 comprises an oxide, a nitride, an oxynitride, or any combination thereof, and has a thickness in a range from about 5 nanometers to about 100 nanometers. Gate electrode 1522 is disposed over gate dielectric layer 1502. The gate electrode 1522 can be formed by depositing a layer of conductively deposited material, or can be made conductive subsequently. The material layer may comprise a metal-containing or semiconductor-containing material. In one embodiment, the layer is deposited to a thickness of about 0.1 microns to about 0.5 microns. The material layer is etched to form a gate electrode 1522. In the illustrated embodiment, gate electrode 1522 is formed without using a mask and has the shape of a sidewall spacer.

An insulating layer 1524 may be thermally grown from the gate electrode 1522 or may be deposited over the workpiece. The insulating layer 1524 may have a thickness in a range from about 10 nanometers to about 30 nanometers. The dopant concentration of source extension 1542 can be higher than about 5x10¹⁷Atom/cm³And less than about 5x10¹⁹Atom/cm³. Body region 1562 may electrically connect channel region 1402 and deep body doped region 1404, and body region 1562 may reduce the likelihood of having a more resistive region between channel region 1402 and deep body doped region 1404 than without body region 1562. Body region 1562 may also reduce the likelihood of breakdown between the source and drain of the transistor structure. Body region 1562 has the same characteristics as channel region 1402 and deep body doped region 1404And has a conductivity type of at least about 1x10¹⁸Atom/cm³The peak dopant concentration of (a).

Fig. 16 shows a positional relationship between the respective features of the workpiece in fig. 15. The distance 1582 corresponds to the distance between the gate electrode 1522 and the conductive electrode 1032, and the width 1584 corresponds to the width of the doped region 1222. As shown in the embodiment of fig. 16, the right edge of the doped region 1222 may extend laterally to a location below the interface between the insulating spacer 1304 and the conductive electrode 1032. In an alternative embodiment, the right edge of the doped region 1222 may extend laterally to a location below the conductive electrode 1032. In a particular embodiment, the lateral extension of the right edge of doped region 1222 is not located under insulating layers 812 and 814. The left edge of doped region 1222 may extend laterally to a location within channel region 1402. The width 1584 may be up to about 1.5 times the distance 1582, and in one particular embodiment, the width 1584 may be up to about 1.2 times the distance 1582. There is no known lower limit to width 1584. In one embodiment, the width 1584 may be at least about 0.2 times the distance 1582, and in another embodiment, the width 1584 may be at least about 0.4 times the distance 1582.

Fig. 17 includes insulating spacers 1602 and heavily doped source regions 1642. FIG. 18 includes an enlarged view of a portion of FIG. 17 to better illustrate the positional relationship between various features of the workpiece. Insulating spacers 1602 are formed to cover portions of the source extension regions 1542. Insulating spacers 1602 may be formed by depositing an insulating layer and anisotropically etching the insulating layer. Insulating spacers 1602 may comprise an oxide, nitride, oxynitride, or any combination thereof, and have a width at the base of insulating spacers 1602 in a range of about 50 nanometers to about 200 nanometers. Heavily doped source regions 1642 allow for subsequent ohmic contact fabrication and have a thickness of at least about 1x10¹⁹Atom/cm³Dopant concentration of (a). Heavily doped source regions 1642 may be formed using ion implantation. The heavily doped source region 1642 has an opposite conductivity type compared to the channel region 1402 and the same conductivity type as the drain region 624 and the buried conductive region 202.

Fig. 19 includes spacers 1702, openings 1704, and heavily doped body contact regions 1722. FIG. 20 includes an enlarged view of a portion of FIG. 19 to better illustrate the positional relationship between various features of the workpiece. In contrast to fig. 17, fig. 19 and 20 do not show the vertically oriented conductive region 542 near the center of fig. 17. In one embodiment, the positions of the vertically oriented conductive regions 542 may be offset from each other to allow for a more compact layout of the transistor. For example, the respective vertically oriented conductive regions 542 that contact the heavily doped source regions 1642 near the middle of fig. 19 and 20 may be positioned further back than lie along the plane of fig. 19 and 20. In another embodiment, the heavily doped source regions 1642 of the high-side transistor structure may have the form of one heavily doped source region, and the heavily doped source regions 1642 of the low-side transistor structure (not shown in fig. 19 and 20) may have the form of a different heavily doped single source region. Thus, the vertically oriented conductive region 542 need not extend through each portion of the heavily doped source region 1642 that is located between corresponding gate electrodes 1522 of the same transistor structure.

In fig. 19 and 20, spacers 1702 are formed to define the portions where heavily doped body contact regions 1722 will be formed. The spacers 1702 may be formed by depositing an insulating layer and anisotropically etching the insulating layer. The spacers 1702 may comprise an oxide, nitride, oxynitride, or combination thereof. In one particular embodiment, spacers 1702 may be sacrificial spacers that are removed after forming heavily doped body contact regions. Thus, the spacers 1702 need not be insulating material. Opening 1704 is defined in part by the sides of spacer 1702 facing each other.

Along the bottom of opening 1704, portions of gate dielectric layer 1502 and heavily doped source regions 1642 are etched. Heavily doped body contact regions 1722 are then formed along the bottom of openings 1704. The heavily doped body doped region 1722 has the same conductivity type as the channel region 1402 and the deep body doped region 1404, and has at least about 1x10¹⁹Atom/cm³To allow for subsequent ohmic contact formation.

Body regions 1562 and heavily doped body contact regions 1722 help ensure that a good electrical contact is made with vertically oriented conductive regions 542 (when vertically oriented conductive regions 542 include a metal-containing material) and help facilitate subsequently formed metal suicide regions. In another embodiment, body regions 1562 may be formed and heavily doped body contact regions 1722 are not formed. In another embodiment, heavily doped body contact regions 1722 are formed and body regions 1562 are not formed. After reading this specification, those skilled in the art will be able to determine the electrical properties they need or desire and determine whether body region 1562, heavily doped body contact regions 1722, or a combination of body region 1562 and heavily doped body contact regions 1722 should be achieved.

FIG. 21 includes conductive members 1822 and 1824. In one embodiment, a portion or all of spacers 1702 are removed to expose more heavily doped source regions 1642. A conductive feature 1822 is formed over gate electrode 1522 and allows for better contact and lower resistance. The conductive members 1824 electrically connect the heavily doped source region 1642, the heavily doped body contact region 1722, and the vertically oriented conductive region 542 (if present) to one another. In one particular embodiment, a refractory metal (e.g., Ti, Ta, W, Co, Pt, etc.) may be deposited over the workpiece and selectively reacted with exposed silicon (e.g., substantially single crystal or polycrystalline silicon) to form a metal silicide. The unreacted portions of the refractory metal over the insulating material are removed, thereby leaving conductive features 1822 and 1824. At this point in the process, transistor structures for the high-side and low-side power transistors 12 and 14 are formed.

Fig. 22 and 23 include a transistor structure diagram within the high-side power transistor 12 (fig. 22) and the low-side power transistor after forming the first level interconnect. An interlayer dielectric (ILD) layer 1902 is formed and may include an oxide, a nitride, an oxynitride, or any combination thereof. The ILD layer 1902 may comprise one film having a substantially constant or varying composition (e.g., a high phosphorous composition away from the semiconductor layer 206) or may comprise a plurality of discrete films. An etch stop film, anti-reflective film, or combination may be used to aid in the process, either within the ILD layer 1902 or over the ILD layer 1902. The ILD layer 1902 may be planarized to improve process margins during subsequent processing operations (e.g., photolithography, subsequent polishing, etc.).

In the embodiment shown in fig. 22 and 23, the ILD layer 1902 is patterned to define contact openings, and conductive plugs 1922, 1924, 1926, 1928, 1932, 1934, and 1938 are formed within the contact openings. Conductive plugs 1922 and 1932 contact conductive electrodes 1032 within the high-side and low-side transistors, respectively. Conductive plugs 1924 and 1934 contact conductive members 1824 in contact with heavily doped source regions 1642 and heavily doped body contact regions 1722. Conductive plugs 1924 and 1934 are located within the high-side and low-side transistors, respectively. Conductive plug 1926 contacts drain region 624 within high-side transistor 12. Note that no conductive plug contacts drain region 624 within low side transistor 14. Conductive plugs 1928 and 1938 contact conductive members 1822 disposed over gate electrode 1522 in the high-side and low-side transistors, respectively.

A plurality of other conductive plugs are formed and will be visible in other views. Although not shown in fig. 22 and 23, substantially all of the conductive electrodes 1032 within the high-side transistor 12 are electrically connected to a conductive plug 1922, and substantially all of the conductive electrodes 1032 within the low-side transistor 14 are electrically connected to a conductive plug 1932. Substantially all of the conductive members 1824 within high-side transistor 12 are electrically connected to conductive plug 1924 or vertically oriented conductive region 542, and substantially all of the conductive members 1824 within low-side transistor 14 are electrically connected to conductive plug 1934. Substantially all of the conductive components 1822 within high-side transistor 12 are electrically connected to conductive plug 1928, and substantially all of the conductive components 1822 within low-side transistor 14 are electrically connected to conductive plug 1938. As such, substantially all gate electrodes 1522 within high-side transistor 12 are electrically connected to conductive plug 1928, and substantially all gate electrodes 1522 within low-side transistor 14 are electrically connected to conductive plug 1938. Substantially all of the drain region 624 within the high-side transistor 12 is electrically connected to a conductive plug 1926, and substantially all of the horizontally-oriented doped region 622 within the low-side transistor 14 is electrically connected to the vertically-oriented conductive region 542.

Another interlayer dielectric (ILD) layer 2002 is formed and may include an oxide, nitride, oxynitride or any combination thereof. ILD layer 2002 may include any of the components described with respect to ILD layer 1902 above. ILD layer 2002 may have substantially the same or different composition than ILD layer 1902. The ILD layer 2002 is patterned to define contact openings.

Interconnects 2022, 2026, 2032, and 2038 are formed that extend at least partially within contact openings within ILD layer 2002. An interconnect 2022 electrically connects the conductive electrode 1032 and the conductive member 1824 within the high-side transistor 12. Interconnect 2032 electrically connects the conductive member 1824, the conductive electrode 1032, and V within the low-side transistor 14_STerminals (fig. 1). An interconnect 2026 (one of which is shown in FIG. 22) electrically connects the drain region 624 within the high-side transistor 12 and V_DTerminals (fig. 1). An interconnect 2038 (one of which is shown in fig. 23) electrically connects the gate electrode within the low-side transistor 14 and the control unit 16 (fig. 1). Although not shown, other interconnects electrically connect the gate electrode 1522 within the high-side transistor 12 and the control unit 16.

Although not shown, additional or fewer layers or features may be used to form an electronic device, if needed or desired. The field isolation regions are not shown, but may be used to help electrically isolate portions of the high-side power transistor from the low-side power transistor. In another embodiment, more levels of isolation and interconnection may be used. A passivation layer may be formed over the workpiece or may be formed within the interconnect level. After reading this description, those skilled in the art will be able to determine the layers and features for their particular applications.

The electronic device may include a number of other transistor structures that are substantially the same as the transistor structures shown in fig. 22 and 23. The transistor structures in fig. 22 may be connected in parallel with each other to form high side power transistor 12, and the transistor structures in fig. 23 may be connected in parallel with each other to form low side power transistor 14. The above configuration may give a sufficient effective channel width of the electronic device that can withstand the relatively large currents used during normal operation of the electronic device. In one particular embodiment, each power transistor may be designed to have a maximum source-drain voltage difference of about 30V, and to have a maximum source-gate voltage difference of about 20V. During normal operation, the source-drain voltage is no greater than about 20V, and the source-gate voltage difference is no greater than about 9V.

In yet another embodiment, one or more bipolar transistors may be used in place of the field effect transistors. In this embodiment, the current carrying electrode may include an emitter region and a collector region instead of the source and drain regions, and the control electrode may include a base region instead of the gate electrode. The emitter of the high-side bipolar transistor may be electrically connected to the collector of the low-side bipolar transistor. If a buried collector is used, the buried collector may be patterned to allow the fabrication of the appropriate isolated connection to the buried conductive region 202.

Embodiments as described herein may include a substrate having less than about 1x10¹⁹Atom/cm³Of the peak dopant concentration of (a). If ohmic contacts with metal-containing materials are needed or desired, a portion of the doped regions can be locally doped to have a doping of at least about 1x10¹⁹Atom/cm³The peak dopant concentration of (a). In a non-limiting example, buried conductive region 202 may have a thickness of less than about 1x10¹⁹Atom/cm³The peak dopant concentration of (a). If the vertical conductive structure 422 comprises W or WSi, portions of the buried conductive region 202 of the nearby vertical conductive structure 422 may be implanted to locally increase the peak dopant concentration to at least about 1x10¹⁹Atom/cm³Thereby helping to form an ohmic contact between the buried conductive region 202 and the vertical conductive structure 422. In other embodiments, the conductivity types may be reversed. As described herein, an N-channel transistor structure is shown. In an alternative embodiment, a P-channel transistor structure may be formed.

The buried insulator layer 204 may be used to reduce unwanted parasitic effects compared to transistor structures that do not include the buried insulator layer 204 and rely on a PN junction to be formed between the buried conductive region 202 and the semiconductor layer 206. In particular, buried insulator layer 204 may provide better isolation and may allow for the doping concentration of semiconductor 206 to be varied without concern for junction breakdown. As transistor structures are made smaller, the dopant concentration of the semiconductor layer 206 may increase. Further, dopants from the deep body doped region 1404 may extend to or near a surface of the semiconductor layer 206 opposite the major surface 205. The presence of the buried insulator layer 204 may allow for higher doping concentrations within the semiconductor layer 206, whether from the background doping concentration or the deep body doping region 1404, since junction breakdown at the bottom of the semiconductor layer 206 is eliminated by the presence of the buried insulator layer 204. In addition to more design freedom, buried insulating layer 204 may reduce process complexity when forming semiconductor layer 206 and doped regions within the layer.

Many different aspects and embodiments are possible. Some of those aspects and embodiments will be described below. After reading this description, those skilled in the art will appreciate that those aspects and embodiments are merely illustrative and are not intended to limit the scope of the invention.

In a first aspect, an electronic device may include a buried conductive region, a buried insulating layer over the buried conductive region; a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a major surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than the major surface. The electronic device can also include a first current carrying electrode of a first transistor, where the first current carrying electrode is disposed along the major surface and spaced apart from the buried conductive layer. The electronic device may further include a first vertical conductive structure extending through the buried insulating layer, wherein the first vertical conductive structure is electrically connected to the first current carrying electrode and the buried conductive region.

In one embodiment of the first aspect, the electronic device further comprises an insulating liner disposed between the first vertical conductive structure and the semiconductor layer. In another embodiment, the first vertical conductive structure extends at least about 0.2 microns into the buried conductive region. In another embodiment, the first vertical conductive structure defines a void adjacent to the buried insulator layer, wherein substantially all of the void is disposed at a height spaced apart from a height of the major surface.

In another embodiment of the first aspect, the buried conductive region has a first dopant concentration at a first location and a second dopant concentration at a second location; the buried insulator layer is closer to the first location than the second location; and the first dopant concentration is less than the second dopant concentration. In a specific embodiment, the buried conductive region has a third dopant concentration at a third location, wherein the buried insulating layer is closer to the third location than the first and second locations; and wherein the third dopant concentration is greater than the first dopant concentration and less than the second dopant concentration. In a more specific embodiment, the buried conductive region is N-type doped.

In another embodiment of the first aspect, the first current carrying electrode is a drain region. In another embodiment, the electronic device further comprises a second current carrying electrode of a second transistor, wherein the second current carrying electrode is disposed along the major surface and spaced apart from the buried conductive layer; and a second vertical conductive structure extending through the buried insulating layer, wherein the second vertical conductive structure is electrically connected to the second current carrying electrode and the buried conductive region. In a specific embodiment, the first current carrying electrode is a drain region of the first transistor and the second current carrying electrode is a source region of the second transistor. In another embodiment, the first and second transistors are both N-channel power transistors or both P-channel power transistors. In another specific embodiment, the first transistor is a low-side transistor of a power switching circuit and the second transistor is a high-side transistor of the power switching circuit. In another specific embodiment, the first transistor includes a first control electrode and the second transistor includes a second control electrode. The electronic device further includes a first control terminal coupled to the first control electrode, and a second control terminal coupled to the second control electrode.

In a second aspect, a method of forming an electronic device may comprise: providing a substrate comprising a semiconductor layer disposed over a buried insulator layer, the buried insulator layer being located over a buried conductive region, wherein the semiconductor layer has a major surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than the major surface. The method also includes forming a first doped region within the semiconductor layer and along the major surface of the first semiconductor layer, wherein the first doped region is part of a first current carrying electrode of a first transistor. The method may further include forming a first vertical conductive structure extending through at least a portion of the buried insulating layer and the semiconductor layer, wherein the buried conductive region, the first vertical conductive structure, and the first doped region are electrically connected to one another in the completed device.

In one embodiment of the second aspect, the method further comprises forming a trench through the first semiconductor layer and the buried insulator layer. In a particular embodiment, forming the first vertical conductive structure includes depositing a conductive material within the trench. In another embodiment, the method further includes thermally oxidizing a portion of the semiconductor layer along the walls of the trench prior to depositing the conductive material. In a more specific embodiment, the method further comprises extending the trench to a depth of at least 0.2 microns in the buried conductive region, wherein extending the trench is performed after thermally oxidizing a portion of the semiconductor layer and before depositing a conductive material.

In another embodiment of the second aspect, the method further includes forming a second doped region within the semiconductor layer and along the major surface of the second semiconductor layer, wherein the second doped region is part of a second current carrying electrode of a second transistor. The method further includes forming a second vertical conductive structure extending through at least a portion of the buried insulating layer and the semiconductor layer, wherein the buried conductive region, the second vertical conductive structure, and the second doped region are electrically connected to one another in the completed device. In a particular embodiment, forming the second doped region is performed after forming the second vertical conductive structure, forming the first conductive structure and forming the second conductive structure are performed in substantially the same time period, and forming the first conductive structure is performed before forming the first doped region.

Note that not all of the activities in the above summaries or examples are required, that a portion of a specific activity may not be required, and that one or more further activities may be performed in addition to those described. Further, the order in which the acts are listed is not necessarily the order in which the acts are performed. For clarity, certain features that are described in the context of separate embodiments may also be present in combination in a single embodiment. Conversely, various features that are, for brevity, described in the context of a single embodiment, may also be provided separately or in any subcombination. Further, reference to values stated in ranges includes each and every value within that range.

Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced, however, are not to be construed as a critical, required, or essential feature or element of any or all the claims.

The illustrations and figures of the embodiments described herein are intended to provide a general understanding of the structure of the various embodiments. The specification and drawings are not intended to be an exhaustive or complete description of all the features and elements of apparatus and systems that may use the structures or methods described herein. Separate embodiments may also be combined in one embodiment, and conversely, various features that are described in the context of a single embodiment may also be present separately or in any subcombination for the sake of brevity. Further, reference to values stated in ranges includes each and every value within that range. Numerous other embodiments may be apparent to those of skill in the art upon reading this specification only. Other embodiments may be utilized and derived from the disclosure, such that structural substitutions, logical substitutions, or other changes may be made without departing from the scope of the disclosure. Accordingly, the present disclosure is to be considered as illustrative and not restrictive.

Claims

1. An electronic device, comprising:

embedding a conductive region;

a buried insulating layer over the buried conductive region;

a semiconductor layer disposed over the buried insulating layer, wherein the semiconductor layer has a major surface and an opposite surface, and the buried conductive region is disposed closer to the opposite surface than the major surface;

a first current carrying electrode of a first transistor, wherein the first current carrying electrode is disposed along the major surface and spaced apart from the buried conductive region;

a first vertical conductive structure extending through the buried insulating layer, wherein the first vertical conductive structure is electrically connected to the first current carrying electrode and the buried conductive region; and

wherein the first vertical conductive structure defines a void adjacent to the buried insulator layer, wherein substantially all of the void is disposed at a height spaced apart from a height of the major surface.

2. The electronic device of claim 1, further comprising an insulating liner disposed between the first vertical conductive structure and the semiconductor layer.

3. The electronic device of claim 1, wherein the first current carrying electrode is a drain region.

4. The electronic device of claim 1, wherein:

the buried conductive region having a first dopant concentration at a first location and a second dopant concentration at a second location;

the buried insulator layer is closer to the first location than the second location; and

the first dopant concentration is less than the second dopant concentration.

5. The electronic device of claim 4, wherein the buried conductive region has a third dopant concentration at a third location, wherein:

the buried insulating layer is closer to the third location than the first and second locations; and

the third dopant concentration is greater than the first dopant concentration and less than the second dopant concentration.

6. An electronic device, comprising:

a buried conductive region of a first conductivity type;

a buried insulating layer over the buried conductive region;

a first vertical conductive structure extending through the buried insulating layer, wherein the first vertical conductive structure is electrically connected to the first current carrying electrode and the buried conductive region of the first conductivity type;

a second current carrying electrode of a second transistor, wherein the second current carrying electrode is disposed along the major surface and spaced apart from the buried conductive layer region; and

a second vertical conductive structure extending through the buried insulating layer, wherein the second vertical conductive structure is electrically connected to the second current carrying electrode and the buried conductive region of the first conductivity type.

7. The electronic device of claim 6, wherein the first current carrying electrode is a drain region of the first transistor and the second current carrying electrode is a source region of the second transistor.

8. The electronic device of claim 6, wherein the first and second transistors are both N-channel power transistors or both P-channel power transistors.

9. The electronic device of claim 6, wherein the first transistor is a low-side transistor of a power switching circuit and the second transistor is a high-side transistor of the power switching circuit.

10. The electronic device of claim 1, further comprising:

the first current carrying electrode includes a horizontally oriented doped region having a first conductivity type;

a channel region of the transistor, wherein the channel region has a second conductivity type opposite the first conductivity type; and

a body region having a second conductivity type and disposed below the channel region, wherein the channel region has a shallower depth than the body region and further extends toward the horizontally-oriented doped region.

11. A method of forming an electronic device, comprising:

providing a substrate comprising a semiconductor layer disposed over a buried insulator layer, the buried insulator layer being located over a buried conductive region, wherein the semiconductor layer has a major surface and an opposing surface, and the buried conductive region is disposed closer to the opposing surface than the major surface;

forming a first doped region within the semiconductor layer and along the major surface of the semiconductor layer, wherein the first doped region is part of a first current carrying electrode of a first transistor; and

forming a first vertical conductive structure extending through at least a portion of the buried insulating layer and the semiconductor layer, wherein in the completed device the buried conductive region, the first vertical conductive structure, and the first doped region are electrically connected to each other;

forming a second doped region within the semiconductor layer and along the major surface of the semiconductor layer, wherein the second doped region is part of a second current carrying electrode of a second transistor; and

forming a second vertical conductive structure extending through at least a portion of the buried insulating layer and the semiconductor layer, wherein in the completed device the buried conductive region, the second vertical conductive structure, and the second doped region are electrically connected to each other.

12. The method of claim 11, further comprising forming a trench through the semiconductor layer and the buried insulating layer, wherein forming the first vertical conductive structure comprises depositing a conductive material within the trench.

13. The method of claim 11, further comprising:

forming a trench penetrating the semiconductor layer and the buried insulating layer; and

thermally oxidizing a portion of the semiconductor layer along the walls of the trench prior to depositing the conductive material.

14. The method of claim 13, further comprising extending said trench to a depth of at least 0.2 microns in said buried conductive region, wherein extending said trench is performed after thermally oxidizing a portion of said semiconductor layer and before depositing a conductive material for said first vertical conductive structure.

15. The method of claim 11, further comprising:

forming a second doped region after forming the second vertical conductive structure;

forming a first vertical conductive structure and forming a second vertical conductive structure during the same time period; and

the first vertical conductive structure is formed prior to forming the first doped region.

16. The method of claim 15, wherein the first current carrying electrode is a drain region of the first transistor and the second current carrying electrode is a source region of the second transistor.

17. The method of claim 11, further comprising:

forming a horizontally oriented doped region within the semiconductor layer, wherein the horizontally oriented doped region has a first conductivity type and is part of a drift region of a transistor;

forming an insulating layer over the horizontally-oriented doped region, wherein the insulating layer is patterned to define an opening;

forming a channel region within the semiconductor layer, wherein the channel region has a second conductivity type opposite the first conductivity type, and the channel region is formed under the opening in the insulating layer;

forming a gate electrode over the channel region after forming the channel region;

forming a bulk region within the semiconductor layer, wherein:

the body region having a second conductivity type;

the channel region is configured between the body region and the horizontally oriented doped region; and

the body region is formed after the gate electrode is formed.