[go: up one dir, main page]

GB2400709A - System and method for programming ONO dual bit memory cells - Google Patents

System and method for programming ONO dual bit memory cells Download PDF

Info

Publication number
GB2400709A
GB2400709A GB0417770A GB0417770A GB2400709A GB 2400709 A GB2400709 A GB 2400709A GB 0417770 A GB0417770 A GB 0417770A GB 0417770 A GB0417770 A GB 0417770A GB 2400709 A GB2400709 A GB 2400709A
Authority
GB
United Kingdom
Prior art keywords
bit
programming
memory cells
assures
memory array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0417770A
Other versions
GB2400709B (en
GB0417770D0 (en
Inventor
Darlene Hamilton
Timothy Thurgate
Janet S Y Wang
Michael K Han
Narbeh Derhacobian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/050,483 external-priority patent/US6567303B1/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0417770D0 publication Critical patent/GB0417770D0/en
Publication of GB2400709A publication Critical patent/GB2400709A/en
Application granted granted Critical
Publication of GB2400709B publication Critical patent/GB2400709B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

A system and methodology is provided for programming first bit (CO, C2, C4, C6) and second bit (C1, C3, C5, C7) of a memory array (68) of dual bit memory cells (10, 82, 84, 86, 88) at a substantially high delta VT. The substantially higher VT assures that the memory array (68) will maintain programmed data and erase data consistently after higher temperature stresses and/or custumer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit (C0, C2, C4, C6) of the memory cell (10, 82, 84, 86, 88) causes the second bit (C1, C3, C5, C7) to program harder and faster due to the shorter channel (8) length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) that assures a controlled first bit VT and slows down programming of the second bit (C1,C3, C5, C7). Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

Description

GB 2400709 A continuation (72) Inventor(s): Darlene Hamilton Timothy
Thurgate Janet S Y Wang Michael K Han Narbeh Derhacobian (74) Agent and/or Address for Service: Brookes Batchellor LLP 102-108 Clerkenwell Road, LONDON, EC1M USA, United Kingdom
GB0417770A 2002-01-16 2002-12-17 System and method for programming ONO dual bit memory cells Expired - Fee Related GB2400709B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/050,483 US6567303B1 (en) 2001-01-31 2002-01-16 Charge injection
PCT/US2002/040775 WO2003063167A2 (en) 2002-01-16 2002-12-17 System and method for programming ono dual bit memory cells

Publications (3)

Publication Number Publication Date
GB0417770D0 GB0417770D0 (en) 2004-09-15
GB2400709A true GB2400709A (en) 2004-10-20
GB2400709B GB2400709B (en) 2005-12-28

Family

ID=27609070

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0417770A Expired - Fee Related GB2400709B (en) 2002-01-16 2002-12-17 System and method for programming ONO dual bit memory cells

Country Status (8)

Country Link
JP (1) JP2005516330A (en)
KR (1) KR20040071322A (en)
CN (1) CN100433193C (en)
AU (1) AU2002367512A1 (en)
DE (1) DE10297641T5 (en)
GB (1) GB2400709B (en)
TW (1) TWI260639B (en)
WO (1) WO2003063167A2 (en)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6928001B2 (en) 2000-12-07 2005-08-09 Saifun Semiconductors Ltd. Programming and erasing methods for a non-volatile memory cell
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US7190620B2 (en) 2002-01-31 2007-03-13 Saifun Semiconductors Ltd. Method for operating a memory device
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US6967873B2 (en) * 2003-10-02 2005-11-22 Advanced Micro Devices, Inc. Memory device and method using positive gate stress to recover overerased cell
US7366025B2 (en) 2004-06-10 2008-04-29 Saifun Semiconductors Ltd. Reduced power programming of non-volatile cells
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1684307A1 (en) 2005-01-19 2006-07-26 Saifun Semiconductors Ltd. Method, circuit and systems for erasing one or more non-volatile memory cells
US7184313B2 (en) 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
US7307878B1 (en) 2005-08-29 2007-12-11 Spansion Llc Flash memory device having improved program rate
US7957204B1 (en) 2005-09-20 2011-06-07 Spansion Llc Flash memory programming power reduction
US8358543B1 (en) 2005-09-20 2013-01-22 Spansion Llc Flash memory programming with data dependent control of source lines
US7433228B2 (en) 2005-09-20 2008-10-07 Spansion Llc Multi-bit flash memory device having improved program rate
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
KR100666223B1 (en) * 2006-02-22 2007-01-09 삼성전자주식회사 3-level nonvolatile semiconductor memory device for reducing coupling noise between memory cells and driving method thereof
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US7969788B2 (en) * 2007-08-21 2011-06-28 Micron Technology, Inc. Charge loss compensation methods and apparatus
CN111863086B (en) * 2019-04-29 2022-07-05 北京兆易创新科技股份有限公司 Method and device for controlling programming performance

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011725A (en) * 1997-08-01 2000-01-04 Saifun Semiconductors, Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6044022A (en) * 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
US6307784B1 (en) * 2001-02-28 2001-10-23 Advanced Micro Devices Negative gate erase
WO2001084552A2 (en) * 2000-05-04 2001-11-08 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
WO2002071410A2 (en) * 2001-02-28 2002-09-12 Advanced Micro Devices, Inc. Higher program threshold voltage and faster programming rates based on improved erase methods

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675537A (en) * 1996-08-22 1997-10-07 Advanced Micro Devices, Inc. Erase method for page mode multiple bits-per-cell flash EEPROM
US5870335A (en) * 1997-03-06 1999-02-09 Agate Semiconductor, Inc. Precision programming of nonvolatile memory cells
US6512701B1 (en) * 2001-06-21 2003-01-28 Advanced Micro Devices, Inc. Erase method for dual bit virtual ground flash

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6011725A (en) * 1997-08-01 2000-01-04 Saifun Semiconductors, Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6044022A (en) * 1999-02-26 2000-03-28 Tower Semiconductor Ltd. Programmable configuration for EEPROMS including 2-bit non-volatile memory cell arrays
WO2001084552A2 (en) * 2000-05-04 2001-11-08 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6307784B1 (en) * 2001-02-28 2001-10-23 Advanced Micro Devices Negative gate erase
WO2002071410A2 (en) * 2001-02-28 2002-09-12 Advanced Micro Devices, Inc. Higher program threshold voltage and faster programming rates based on improved erase methods

Also Published As

Publication number Publication date
CN100433193C (en) 2008-11-12
DE10297641T5 (en) 2005-01-05
CN1628358A (en) 2005-06-15
GB2400709B (en) 2005-12-28
TW200302486A (en) 2003-08-01
TWI260639B (en) 2006-08-21
AU2002367512A1 (en) 2003-09-02
KR20040071322A (en) 2004-08-11
GB0417770D0 (en) 2004-09-15
WO2003063167A2 (en) 2003-07-31
WO2003063167A3 (en) 2003-12-04
JP2005516330A (en) 2005-06-02

Similar Documents

Publication Publication Date Title
GB2400709A (en) System and method for programming ONO dual bit memory cells
WO2002071410A3 (en) Higher program threshold voltage and faster programming rates based on improved erase methods
EP1227498A3 (en) An EEPROM array and method for operation thereof
DE69913441D1 (en) High data rate write method for non-volatile FLASH memories
EP1022746A3 (en) Method of operating a two-transistor flash memory cell
GB2401460A (en) Partial page programming of multi level flash semiconductor memory
AU2003296988A1 (en) An improved method for making high-density nonvolatile memory
AU3124700A (en) Floating gate memory apparatus and method for selected programming thereof
AU2001283185A1 (en) Method and system for dual bit memory erase verification
GB2430291A (en) Erase algorithum multi-level bit flash memory
IL146275A0 (en) Programming and erasing methods for an nrom array
AU2003222282A1 (en) A system and method for erase voltage control during multiple sector erase of a flash memory device
US6396745B1 (en) Vertical two-transistor flash memory
AU2002363046A1 (en) Method for erasing a memory cell
TW200514087A (en) Methods for enhancing erase of a memory device, programmable read-only memory device and method for preventing over-erase of an NROM device
AU2001280941A1 (en) Non-volatile memory, method of manufacture and programming
WO2001084552A3 (en) Programming of nonvolatile memory cells
TWI317947B (en) Nand non-volatile storage device and methods of using and making the same
EP1603137A3 (en) Program/erase method for p-channel charge trapping memory device
KR19990057230A (en) Program Method of Semiconductor Memory Device
TW200506952A (en) Semiconductor device
TW200608406A (en) Methods and systems for high write performance in multi-bit flash memory devices
WO2007117610A3 (en) Methods for erasing memory devices and multi-level programming memory device
SG105590A1 (en) Single bit nonvolatile memory cell and methods for programming and erasing thereof
WO2004023239A3 (en) Method of recovering overerased bits in a memory device

Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20150618 AND 20150624

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20181217