TWI260639B - Charge injection - Google Patents

Abstract

A system and methodology is provided for programming first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) of a memory array (68) of dual bit memory cells (10, 82, 84, 86, 88) at a substantially high delta VT. The substantially higher VT assures that the memory array (68) will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. At a substantially higher delta VT, programming of the first bit (CO, C2, C4, C6) of the memory cell (10, 82, 84, 86, 88) causes the second bit (C1, C3, C5, C7) to program harder and faster due to the shorter channel (8) length. Therefore, the present invention employs selected gate and drain voltages and programming pulse widths during programming of the first bit (C0, C2, C4, C6) and second bit (C1, C3, C5, C7) that assures a controlled first bit VT and slows down programming of the second bit (C1, C3, C5, C7). Furthermore, the selected programming parameters keep the programming times short without degrading charge loss.

Description

1260639 IX. Description of the Invention: [Technical Field] The present invention relates generally to a memory system, and more particularly to an electronic flash using a virtual ground architecture and having a dual bit memory transistor unit A system and method for programming and erasing a number of bit segments in a memory device. [Prior Art] A flash memory is an electronic memory medium that can be rewritten and can retain its contents without power supply. Flash memory devices typically dictate a lifetime of 100,000-to-300,000 write cycles. Unlike a memory chip that can erase a single byte of Dynamic Random Access Memory (DRAM) and Static Memory Access Memory (SRAM), L system The flash memory is erased and written in units of blocks or segments of a plurality of bits. Flash memory system is electrically erasable programmable read-only memory (Electrieally Erasable) that can be erased in the original position

Programmable Read Only Memory; referred to as EEPROM) Progressively, Flash Flash has a lower cost and higher component density. This new type of EEPROM has evolved into a non-volatile memory that combines the high component density of EpR〇M with the EEPROM's ability to electrically erase these two advantages. - One pass, the flash memory system is constructed by storing a single bit of information in the memory unit structure of the parent. In this single-bit L-body structure, the 'per-$ mem unit usually contains—metal oxide semiconductor 92257 (revision) 6 1260639 (Metal Oxide Semiconductor · - ^ 槿 槿 and right / a, nickname M 〇s) transistor structure, :: or "well - source, - drain, and - = ^ stacked interpole structure above the channel. The stack

The gate can be further ordered as a #P layer (sometimes referred to as a channel oxygen::) well = above the 匕 substance: the pottery contains a polycrystalline intergranular medium overlying the interpole On the eve of the eve, and covering the floating, the 曰ϋ 夕 晶 晶 之 曾 曾 = = = = = = = = = = = = = = = = 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘)Floor. Finally, the polycrystalline control gate is above the dielectric layer between the turns. The splicing system is connected to a column associated with such a memory unit to form a plurality of segments in a typical 峨 configuration::: at::,: and, The memory cells are based on the electric field generated by the -conducting bit line in the channel of e ° 4 according to the stacked gate structure, and in the source and 汲 = 0R configuration, the transistors in a single row Each bit reads the same bit. In addition, each flash memory unit is connected to the (four) word line, and all the flash memory sources are connected to the common source terminal. In the operation, individual flash memory cells are addressed via respective ridges and control circuits via respective squall lines and word lines to perform programming (writing), or erase functions. The single-bit stack is pressed. The ultra-fast flash memory unit is applied to the control gate, and the predetermined potential of the source potential is connected to be higher than the The sow:: programming. Crossing the two ends of the tunnel oxide y 冋 琢 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致 导致In the process. Rdheim teeth 7 and w Shi T early in the channel area of the thunder tooth S':::: and entered the floating gate, and trapped in the floating gate surrounded. The memory of the polycrystalline media and the tunnel oxide is trapped by the trapped electrons. The change of the threshold voltage of the memory cell generated by the (four) trapped electrons: (and thus the change in the channel conductivity) causes the program to be programmed. - In order to erase the type of single-bit stacked inter-flash memory, the voltage is applied to the source and the control gate is held at a negative potential, and the drain is floated. Under these conditions, an electric field is generated across the (four) oxide between the floating gate and the source. The part of the maneuvering sub-cluster that was originally trapped in the floating gate and covered in the floating pole over the secret zone is in this part, and the self-floating gate is taken out and worn in hwler-Nordheim. Entering the source region via the accompanying oxide with the effect. When the electrons are removed from the floating gate, the memory unit is erased. In a conventional single bit flash memory device, an erase is performed to determine whether a memory block or a group of such memory cells 7L has been erased correctly. The current single bit erase confirmation method provides an erase of the acknowledgment bit or memory cell and applies the complementary erase pulse to the individual memory cells. This method cannot pass the initial confirmation. Then confirm the status of the erased memory unit and continue the process. 92257 (Revised) 8 1260639

Order until the memory unit or bit is successfully erased

...,, 'This improved programming and erasing method and system will ensure that the data bits in the dual-bit memory virtual ground architecture are correctly programmed and erased, and the structural characteristics of this architecture can be handled. Where or the bit or the memory unit. J圯 惊 early, this flash memory in a single memory unit. The single-program programming and erase-recognition methods have not used features that do not use polysilicon structures, such as a device such as 0Ν0 flash memory in a layered word line connection. MODIFIED PROGRAMMING AND ERASING METHODS FOR USE OF THE INVENTION The present invention provides a first and a second of a dual bit memory cell for programming a memory array under a relatively high deltaVT Bit = system and method. This relatively high ντ ensures that after a relatively long period of temperature stress and/or customer operation in a relatively long period of time, the stencil array consistently maintains the programmed data and erases the data. At a relatively high voltage difference, programming the first bit of the memory cell causes the programming of the second bit to become less variable and faster due to the shorter channel length. Therefore, the present invention employs the selected gate and drain voltages and the programmed pulse width during programming of the first and second bits, which ensures a controlled first bit ντ and slows down Programming of the 9280639 (Revised) 1260639 two-bit. In addition, the charge loss of the Heng charge is accompanied by the jitter: the second programming parameter can be made without making the invention work for a long time. Therefore, it is possible to minimize the double-dimensional record field similar to - (10) 〇 & white, flat, erase, and confirm, j raw data retention and excessive erasure formation, and use a 〇N〇 The invention provides significant; = the dual-bit memory cell architecture associated with the party is not limited to any particular dual-effects' and the invention is equally applicable to the programming or configuration of the dual-bit programming. Although it is gone, it is one---the early one-element associated with the charge is not easily changed.

The charge may be produced in D and early 70 is more difficult to erase. For example, the residual buds of the buds in the 5 mics of the hexagrams are simply erased by the singularity of the singularity. Therefore, the system and the square constant - the early heart of the same -0N0 transistor at the opposite end of the positive moon = the remaining bit 70 (complimentary bit) programming, confirmation, - spear, Θ erase including - The group erase pulse is applied to the two-bit |-memory unit of the normal bit and the residual bit. The group erases the pulse wave force at one end of the 7 ° day of the day, and wipes the pulse wave at both ends, followed by a single-end erase pulse applied to the end, and a single-ended erase applied to the other end Pulse wave (constructed). In one aspect of Ben Maoming, a system and method for erasing a dual bit flash memory unit for a memory and array is provided. The system and method include: pre-programming each of the normal line position and the remaining line position 10 92257 (revision) 1260639 binary confirmation bit 2 of each normal and residual bit line position = erasing request is moved to - Before the address, each bit address is executed, and the ride is confirmed. Alternatively, the bit of the (five) or word line can be erased so that the positive and the remaining bits of &quot;ο must be confirmed by erasing before moving to the next 1/0 or word line. If the location of the address = is lower than the maximum ντ used to define the blank state, then a set of erases is applied, and the erased veins are applied to the normal and attached for a specified duration (eg, 10 milliseconds). The bit in the remaining line position - the two ends erase the pulse L, the bit is applied to the normal position and the position in the line position in the specified line position (for example, i milliseconds) t One of the first single-end erased pulse waves, and in the - specified duration (for example, i milliseconds) knows!! Positive!! Position and the other line position in the remaining line position : The second I end erases the pulse wave. These acknowledgment and erase steps are repeated until the -normal and residual bits in the segment are below the maximum VT used to define a blank = cell. The </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> A soft mode pulse is provided to the bit S that has been determined to have been over erased. The cord confirmation should include a low source voltage to turn off leakage current from other memory cells on the same line. Performing a second or final acknowledgment erase procedure on the bit in the positive f-line position and the residual line position to ensure that the soft program pulse wave does not raise the level bit to define - above the maximum VT of the memory unit . 92257 (Revised) 11 1260639 In order to achieve the foregoing and related objects, the present invention includes the features fully described in the specification and clearly indicated in the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The drawings illustrate in detail certain exemplary aspects of the invention and the actual two aspects of the invention: and the embodiments: are representative of the ways in which the invention may be employed. The invention, its advantages, and novel features will be readily apparent from the following description of the invention. Eight Objects [Embodiment] The present invention will be described in detail with reference to the accompanying drawings. The present invention relates to a method and system for programming (writing), confirming (reading), and correctly erasing a dual bit memory unit operating under the bit reading mode. The present invention provides a double-bit memory cell in an array for correct operation in the meta-mode using the &quot;flash=body=4 wafer erase or segment erase operation&quot; , and although the following text is shown in association with the use of two bits of each memory unit for the location 7&quot;memory unit architecture and x', but we can understand that the present invention can also be applied to 1 His type of architecture and other two-bit architectures use body Lee. For the sake of /, he is referred to the drawings, and the drawings illustrate various examples in which the present invention can be implemented. : or multiple oriented - instantiate a dual bit memory unit. 〇). The sandwich: comprises a tantalum nitride layer (16)' between the tantalum nitride layer (16) and the lower dioxy-cut layer (18), and the second layer is formed. Ν layer (3.). - a polycrystalline layer (9) is provided on the ’ 且 and provides a word line connection of the memory unit (1). 92257 (Revised) 12 1260639 bit line (32) is located in the (10) layer (9) below the first area (4). 'The second second bit line (34) is located below the second area (4). Under (10) :). The bit lines (32) and (34) are composed of a conductive portion (24) = selected oxide portion (22). A stone ion core implant (2〇) is placed on each end of each bit line and (34), and the f temple line line contacts the lower dioxygen layer at the two ends (18). ) or a wide transistor. The doping concentration of these core seeds is higher than the doping concentration of P soil, and helps to control the memory unit (1〇). Is this memory unit (1〇) located in? On the substrate region (9), and the team bell ion implant forms a bit line (32) (9), thus forming a channel between the p-type substrate and a channel (2) is composed of a single electric a crystal structure having a dipole of an exchangeable source formed by the Kunn ion implantation portion (24), and the n+ Shishen ion value input portion (24) is formed as a polycrystalline stone word line A portion of the gate of (12) is commonly disposed on the p-type substrate region (9). Although the first and second bit lines (32) and (34) are illustrated with respect to the conductive portion (24) and the freely selectable oxide portion (22), the province is to understand or use only A conductive portion forms the bit line. In addition, although the first! The figure shows a number of gaps in the layer of nitride (16), but it is understood that the tantalum nitride layer (16) can also be fabricated in a single or single layer without gaps. The nitride layer (16) forms a trapped layer of Φ Φ m α 0 . The programming of the memory cell is accomplished by applying a voltage to the drain and gate and grounding the source. This voltage generates an electric field along the channel, which accelerates the electrons and jumps into the nitride from the substrate 92257 (revision) 13 1260639 layer (9), a phenomenon known as hot electron injection electron injection). Because the electrons get most of the energy on the drain', the electrons are trapped and remain stored at the atmosphere layer near the drain. The memory unit (10) is generally uniform and the drain and source are interchangeable. Since the nitride is not electrically conductive, the first charge (Μ) can be injected into the nitride U6) near the first end of the central region (5), and the second charge (28) can be injected into the nitride (16). The middle is close to the second end of the central area (5). Therefore, if the bits are not moved, each memory unit can have two bits instead of one. As described above, the first charge (26) can be stored at the first end of the central region (5) in the nitride layer (16), and the second charge (3)) can be stored: a nitride layer At the second end of the central zone (1) in (16), there may be two bits per brother-remembering single το (1G). The two-bit memory cell (1〇) is generally symmetrical, so the drain and source are interchangeable. Thus, when programming the left azimuth element (3), the first bit line (32) can be used as the 汲 extreme ' and the second bit line (34) can be used as the source terminal. Similarly to f, the m-line (9) can be used as the source terminal when the right azimuth is programmed and the extreme ' and the first bit line (32) can be used. The first table does not show a group-specific voltage parameter for reading, programming, and single-ended erasing of the dual bit memory cell (10) having the first bit (3) and the second bit ^. 92257 (revision) 14

Homework------Shishi Memory tMJ - Early Gate Gate &quot;~------- Bit Line 0 Bit Line 1 Note 5 Baye Take-------- ηΓΓ CO Vcc 0 Volt 1.2 volt extra line master--~~~---. Cl Vcc ------- _ 1.2 volt-one 0 volt' 1 JJ normal line---- CO y.25 to 9.5 volts 5 to 5.5 i Ιτ^0 volts hot electronic programming Tian^shan ±ί Cl 9.25 to 9H —------- ^~~0^~—5 to 5.5 volts ^hot electrons Ώ3 JWlXl It — λ CO -3 to -6 5 to 6 volts - floating hot electron injection into the soil except Xiit" _ 丄 ^ χ Cl -3 to -6 volts floating _ 5 to 6 volts hot electrons in addition to C1, C0 -3 to -6 volts 5 to 5 Various embodiments of up to 6 volts of hot electron injection A are asked. The invention is particularly applicable to a memory device that uses two bits of a two-bit memory unit for data or information storage. The inventor of this test has found that: programming and erasing a cell (such as bit C0) in such a memory cell will cause the associated bit of the bit (e.g., bit C1) Burn and/or erase. For example, repeated programming of the bit C1 of the memory cell (1 〇) may cause charge accumulation in the bit c〇, and vice versa: 彳 In addition, the erase voltage pulse wave is repeatedly applied to the bit c 1 to 4 Excessive erasure of bit C0. These phenomena in the associated bit are further reduced in the performance of the job of the bit in the positive g job (eg '^ effectally read, write/program, and/or erase one or two bits This power of the yuan). The present invention further selectively ensures that individual bits S of such a brother cell are individually programmed, confirmed, erased, and re-centered to further ensure that the block or segment erase is performed in the flashing stone. Have a memory unit during work

Correct erasure has solved these problems with dual-bit memory cell technology. I brother 2 does not show the programming of two bits in the memory unit (10). 92257 (Revised Edition) 1^ 1260639 $ For ease of explanation, a bit is called a normal bit (N〇rman NB for short), and the associated bit is called a reserved bit, (c〇mplimentary Bit; _ CB). During the read operation, the junction of the memory cell closest to the read is the ground terminal, and the other end of the transistor is the drain. This way is called reverse reading. During programming and erasing, the drain is switched to the closest junction, and the voltage at the closest junction is the drain voltage instead of ground, which is used to read and confirm the job. The two-bit memory unit (1 〇 ) can be considered as three parts of an action, which are a reserved bit area (40), a central area (42), and a normal bit area (44). The residual bit area (40) and the central area (42) are close to the drain/source junction, and the local v-single can be modified during programming and erasing operations. The central zone (42) should be close to the natural VT generated in the process of the memory unit (1 〇). The tantalum nitride (16) from the ON stack (30) is used to store the first electron (38) in the normal bit region (44) and the second charge (π) in the extra bit region (40). . Since nitride is not a conductor, the charge added or removed during, and during the erase and erase operations should not be re-distributed by itself, but should remain in the original implanted position. That is, each end of the transistor may have a different charge and a different VT that are almost independent of the other end. For example, if the natural or erase/blank ντ of the cb and NB is approximately 1.2 volts, and if the nb is programmed to a VT of approximately 3.8 volts, the Bayu CB should still be near blank. Furthermore, if two bits are programmed to a 3.8 volt VT and then the NB is erased, the CB should be approximately 3.8 volts and the NB should be approximately 1.2 volts. 16 92257 (Revised Edition) 1260639 In addition, during the read operation of the NB, the charge of the CB bit line should be connected by a pole, because the source (connected) must be The junction closest to the identified memory unit. The operation::: reverse reading operation, because the reverse reading method of the junction of the confirmed memory unit covers the junction of the other-bits, but any of the channels in the channel The charge will modify = CB and the effective VT of the edge NB. When the area of the areas becomes higher or lower, the other areas may also be affected, which are all part of the same transistor. After the third graphical user programming parameter is programmed for the CB, please ask::::!: (, programming to _(44) programming operation such as = the shorter channel is due to being close to the second bit: =;. The charge stored on the first: bit. Because of the shorter channel length of the first charge, the programming of the second bit is programmed much faster because it is less susceptible to change. The second position: the younger brother, so the erasing of the second bit is slower than the erasing of the first t. The invention can be used to select the bit 1 and eliminate the programming and The residual charge accumulated in the erase cycle (: the heart charge (46) may stay in the memory list and erase characteristics. The amount is in the :- cycle programming, - bit programming charge (46) position will be 92257 (Revised version) 17 1260639 Changed the CB area (40) and the area (4 times with the secondary yarn of the programming and erasing cycle plus ^νΤ, and the combination of the steps provided during the erasing is provided - ^ ^ plus. Both ends and single-ended wipes use the double-bit 71 of one of the memory cells of the last array to erase the outermost bit of the spurs 4 and usually have different passes. Length 2::: will be erased slowly, but both ends of the pulse wave dry "70 has the best effect. So, added a single-end finalization" in order to maintain the outermost part of the memory unit of the array Therefore, it is important to monitor the ντ of the NB area (44), the central area (4), and the CB area (40), and keep the ντ of the areas at a known level. 'In order to operate the memory unit correctly. It is usually performed during erasing (hereinafter referred to as "dual-bit erasure,") to monitor and control the CB and the VT of the VT. Therefore, in the present invention The programming parameters are selected to ensure that the bits are not over-wired due to residual f-charge and that erasing is performed to ensure that the residual charge in the central region (42) is controlled. Programming & erasing by &amp; During the ντ distribution, the erasing and programming time of the programming and erasing cycles will remain stable. Figure 5 shows the memory cell (丨〇) using the two-bit editing and erasing method of the present invention in programming and Erasing the situation after the week. Many flash memories have command logic and In-state state machine for automating complex programming and erase operations. SRAM module components can be used by a microcontroller to control the operation of command logic and memory systems. Program. When a system is powered on, 18 92257 (Revised) 1260639 usually loads these programs into the -SRAM. Available - Busbars transfer control commands from a processor to the command logic and will flash from that The data read by the memory device or written to the flash memory material: command logic and - main processor exchange. The flash memory device = the same state machine generates command logic for detailed operations (4), for example Perform the various individual steps required to program, read, and erase jobs. The state machine is thus used to reduce the resources (four) required for a processor (not shown) that is typically used in connection with a microchip containing flash memory. Referring now to Figure 6, there is provided a system ((8) for performing programming, validation, soft programming, and a memory array (68) employing the dual bit memory cell of the present invention, and In this example, the memory array (68) is constructed by a plurality of 64 kappa segments (69). A segment (69) of the flash memory array includes a memory array (68). A knife comprising all memory cells grouped together via all word lines sharing the same sector address. The sector address is typically an address bit used to address one or more memory cells in the memory array η (for example, six) most significant address bits of the signal, where η is an integer, for example, 8 〇 〇 each 64 Κ segment (69 ), one 疋 ', 4 Orthogonal bits, and 4 The four memory cells of the residual bit or the four double-bit memory cells form the column. We understand that the memory array f ^) can be configured in any number of different configurations, for example, it can be used in 8 = L 8 normal bits and 8 residual bits on the raft constitute the dish sectionIn addition, any number of segments can be employed and is limited only by the size of the application and the size of the device employing the flash memory array (68). 92257 (Revised Edition) 19 1260639 SiS (60) contains an address decoder (62) connected to the flash memory, the array of gates (68), used in the array (drinking various suggestions such as Each program is decoded during programming, reading, confirming, and erasing. The address decoder receives address bus information from a system controller (not shown) or similar device. - The command logic component (64) includes an internal state machine (65). The life logic component (64) is coupled to the address memory array (68). The command logic and state machine are connected to a system controller or similar device = bus to receive commands or instructions. These commands or commands call the command logic (64) and the algorithms embedded in the state machine (65). The algorithms define various programming, reading, erasing, soft programming, and validation methods as will be described herein. - Voltage generation H (four) (66) is connected to the memory array (68) as well as the command logic (64) and the state machine (65). The voltage generator component (66) is controlled by command logic (64) and state machine (65). The voltage generator component (66) is operative to generate the voltages required to program, read, erase, soft program, and validate the memory cells of the memory array (68). Figure 7 is a top or plan view illustrating a partial memory cell layout of a 64K block (70). This example is shown with reference to a 64κ block composed of 16 bits/〇. We understand that each block can be composed of 8-bit, 32-bit, 64-bit, or more bits of I/O, and is not limited to 64K (for example, it can be ι28κ, 256K, etc.) . The 64K block (7〇) can be a segment (sect〇r), or a portion of a segment. For example, one or more blocks having contacts connected to a common metal bit line may constitute a 20 92257 (Revision) 1260639 segment. The stack of strips or layers (72) extends to the length of the array of memory and includes blocks (70). Block (70) contains 16 groups of 1/〇 or lines (^又). Each sub- or I/O group consists of eight transistors or eight normal bits and eight residual bits. Each 1/〇 includes a polysilicon sub-wire (74) for addressing the memory cells of the columns. A plurality of bit lines are not below the stacking layer (72) to initiate reading, writing, and erasing of individual bits of the memory cells. Each of the meta-lines is connected to a first contact (78) and each metal bit line (not shown) at one end of the sixteen-column of the group, and is connected to the other end of the group. A second contact (79). In the example shown in FIG. 7, five bit lines are shown, and thus one twist line is connected to one end of every other transistor in a row, and two select transistors are used to select two transistors. Four bits to perform read, write, and erase. Figure 8 is a schematic diagram of reading, writing, and erasing each of the 7L bits by using a plurality of selected transistors and three bit lines to address the other four dual bit memory cells in 歹J. The first dual bit memory unit (82) includes a first bit C兀 and a second bit C1, and the second bit memory unit (84) includes a first bit C2 and a second bit C3, the third pair The bit memory unit (%) packet 3 has a first bit tl C4 and a second bit, and the fourth dual bit memory cell (88) includes a first bit C6 and a second bit C7. These four double-bit fes, single 7^ can form an 8-bit word. A selection gate (88) (SelO) and a delay (90) (Sell) are provided to activate the bit CO, ci, and the dual bit memory unit (84) of the dual bit memory unit (82). Bits C2, C3 are taken, written, and erased. There are selection gates (92) (Sel2) and 21 92257 (revision) 1260639 selection gates (94) (Sel3) for starting the bits C4, C5, and double bits of the dual-bit memory unit (86) The bit of the memory unit ((10)), C7 read, write, and erase. The first switch (96) is connected to the first bit line BL0 'the second switch (98) is connected to a second bit line 1, and the third switch (1 〇〇) is connected to the third bit line BL2. The first, first, and second open relationships couple the corresponding bit line between the power supply (VDD) and the ground (GND). Any of the bits of the two-bit memory cells can be read by providing different voltage configurations as shown in Table 2 below. In the example of Fig. 8, the bit C0 of the "two-bit memory unit... is being read". Table 2

During double-bit programming, -- , , choose a more ντ change value, electric two-loss: at these higher change values, more than one rate (four) is slower than the second bit on the programming transistor occur. Figure 9 does not change the value between when the programming voltage is much lower: the network - the relationship between the programming time and the V of the first bit (11 〇). Because of the programming of the second bit, 92257 (Revised) 22 1260639 II changed and the faster case, so the second bit determines the double-bit erase between k and the method that can be used to erase the double bit. It is important to select the programming condition that makes the second 兀 programmed VT close to the first bit programming... otherwise the double bit erase may be very slow, and the programmed first = 兀 will be Excessive erasure. In general, the most critical is to control the gate voltage during the programming of the first bit to limit the VT range of the first bit. In order to control the VT of the first bit, the two bits are selected from about 9.25 volts to about 9.5 volts in the power plant, and the IGBT is selected from about 5.0 volts to about 5.5 volts and will program the pulse wave. The pulse wave is as wide as 0.5 microseconds. These conditions help to maintain the stricter first bit VT 'and slow down the programming of the second bit. The key characteristic of the ΟΝΟ two-bit memory unit is the number of times to accelerate the high-temperature baking (75 to 200 degrees Celsius) to the date of the day. Degree No. ® is the electric charge of the voltmeter #招门,:程=:(Program and Erase; referred to as ρε) week (four) times 2 a relationship diagram (m). This figure presents a possible reliability problem, which increases as the amount of power consumption increases as the number of programming and erase cycles increases.兮Two days to move AA w ' U0 曰r: After the meta-programming state (when programming the electric body but the other end is blank or unprogrammed, the state occurs) appears in a larger cycle There is a large charge loss when the number of times:::: The bit is lost when the programmed one is consumed. • 5 volts 'to compensate for the charge caused by recycling 92257 (revised version) 23 1260639 Considering the flow of the previous paragraphs 11 to 14 and the examples of the system, please refer to the method of the first application. . A will be easier to understand. The method according to the present invention can be carried out in a sequential manner::: The simplicity of the description, although the solutions of Figures 11 to 14 are not limited to 2, but are shown and described, but we are The invention is in a different order, and because some steps can be performed according to other steps of the present invention, and/or can be illustrated and implemented according to the present invention. Not all of the steps shown are necessary for a method of the moon. The flash memory key property of the present invention is: in the knowledge, the singularity, the singularity, the singularity, the singularity, the singularity, the singularity, the singularity, the singularity

Li can be used to burn and erase the number of cycles - the strong function. This kind of 'image erasing cycle number ~ 疋 because the pen and the amount of wear and tear with the programming and - end is blank two-way the end of the transistor, but another unprogrammed 'this state occurs" appeared in Degree \ two: = there is a problem of large charge loss. At 25 摄 Celsius; the second baking/dishness of the 'memory cell transistor' is not Gaussian.::an). Below 250 degrees Celsius 'because of the charge in the nitride, the ancient &quot;knife cloth, and the localized strength near the larger polycrystalline litter gap = the nitride charge of the trap', so close to the larger word line (central part 1 two,) _, the memory cell transistor consumes more charge. After all the devices have been cycled through the same number of cycles, a. The charge dissipation distribution under the phase H material is repeated. After the number of cycles exceeds the coffee cycle, the programming and erasing conditions during the use of 92257 (Revised) 24 1260639 3 exhibit little effect on the relationship between charge loss and periodicity. 'Change: ^ After the :_ cycle charge loss, increase the programming ντ = (for example 'make ντ change value equal to 2 to 25 volts) to ensure that the flash memory array is in the late life of the flash memory; . We decided: you can choose a specific programming ^ ί, in a · 25 to 9 · 5 volts ... a fairy: a predetermined programming pulse applied G. 5 microseconds), and the two-bit memory one way to a higher VIY2 0 you 5 ? s' from the heart only (to the 2.5 illusion, and still maintain the pole (four) programming time in the double-bit job. We decided: Photographed endangered, sweet and sturdy / dish (such as ^ 50 The lower 'charge loss is a function of the number of cycles. Use the "correction of this type of charge loss associated with the use of the memory to program the memory cell to a slower rate between 2.0 volts to 2.5 volts. The equipotential (for example, at ν_9 25 ^; 1VdTln = 5.0 to 5.5 volts, the application of the pulse wave of each word to w Μ ^ has better control over the effect of the two-bit programming with the residual bit interference. Figure 11 illustrates a particular method for determining the VT handoff value of a two-bit memory cell of a memory array operating in a two-bit mode in accordance with one aspect of the present invention. The method begins with a step ( 200), where f疋 is - against - normal blank or unprogrammed VT of memory cells in the array In step γ 0Λ, ", Α (05) in the array to change the value of Bo variety of programming of the batch and the &amp; J Ding vanadium right vagus and erase programming cycle times, and then perform a

The south temperature is accelerated for roasting (K 〇〇 to 250 degrees). Then, in step (210) 92257 (Revised) 25 1260639, it is determined that the memory cells are charged according to the amount of charge loss; the value is: (10)), and the root selects a programming parameter (for example, /v text value). In step (220), Vdrain=5.0 to 5 5 volts-gate=9·25 to 9.5 volts, and VT, and slow down to the second: enough to control the first bit of the s, s, everyone, private 0 In step (225), the programming parameters selected by your field &amp; select the erase cycle for the other array of the batch, and then perform the accelerated bake. In the car dry programming and decision step (225) by - ”, A ( 230) _ 'This method Λ . 该 These programming and erasing cycles of the surrogate fruit 3 No { is acceptable. If the 哕 cage start # ^ 功日7,,, 〇果疋("No" branch), the result of 2/period is unacceptable and the result of the erasing cycle is acceptable. The logic and shape of the temple will be the same as in the step (plus). , sighing to use the VT to change the value and the 潠鍟=pot and gate potential to program the two bits of the two-bit memory unit

— We should understand that it is not only possible to use a program that changes the value of 冋VT under normal programming conditions, but also in the two-bit erase method; the programming method described above can also be used in the programming or programming phase. Figure 12 shows the programming parameters used with a selected programming parameter (for example, Vgate = 9.25 to 95 volts Vdram - 5.0 to 5.5 volts, VT change value between 2 volts and 25 volts applied 0.5 microseconds) Wave) method. The two-bit erase method shown in FIGS. 14 to 14 includes a memory cell erase program 'to control the residual bit end and the normal bit end of each memory transistor in a blank or erased state. Ντ threshold upper and lower limit 92257 (revised edition) 26 1260639 (for example, minimum VT spitting volts 'maximum ντ spit 8 volts'). In addition, the two-bit male division method includes a soft programming program to avoid the possibility of causing excessive erasure of the memory unit during a long programming day, and controlling the programming time. This soft editing may also affect the amount of charge loss after recycling. Finally, that. The erase private sequence may include a second erase program to ensure that any memory is not programmed by the soft programming program. Figures 12 through 14 = The two-bit S method improves the flash memory soap of the present invention operating during extended cycle use (e.g., 1 〇〇, programming and erasing (ΡΕ) cycles of coffee 2) Programming and erasing features. Figure 12 does not show an erase method using thermoelectric hole injection at the high-voltage junction of the normal and residual bits. The one-bit reprogramming process will cause accumulated residual charge, while single-ended erase or conventional un:: will not reach within acceptable voltage levels and/or acceptable erasure time. This residual charge. This two-bit erase method ensures the control of the normal bit and the blank VT of 2 bits by using the acknowledgment and modification after each =. Therefore, the two-bit erase method applies a series of erase conditions or sequences to the residual bits within the single-snapshot and their associated normal bits during the pulse period. The erase sequence is an erase pulse of one end or two poles, which makes the source and the drain of all the cells of the money cell high-voltage (for example, 4 to 7 y. Allowable margin) The normal bit of the element and its phase _ discharge. After the iron will be:: the wave is applied to the residual bit (for example, the residual bit is the pole = two (four)' and the other transistor junction is floating) Then, the - single-ended read wave is applied to the normal bit (for example, 'the bungee of the normal bit end becomes 92257 (revised version) 27 1260639 and the voltage, and the other thunder is erected τ-yuan, why is it? The second is floating.) Regardless of the bit to be confirmed, the order of the pulse of the 寻, μ, 鳊, 是, 可以, 除, 士, 士, 士, 士, _, _ Significantly improved results are achieved in the ΟΝΟ two-bit architecture at approximately 75% to 95% of the wave time. In the case of 雔二12Λ, one is used for the one according to the invention The programming and erasing of the flash memory array of the unit is performed: the method begins with the step (3〇〇), at which time the beer is called the erase program. The port 'can send the command from the controller to the The state machine is set to 'the erase program. The bit in the set position and the extra line position is programmed to the ντ change value in step (10)). The programmed money parameter is: at (4).25 to 9.5 volts. Vdrain=5.〇 to 5.5 volts, VT change value between 2 volts and 25 volts, apply a pulse of ^ microseconds. The method then proceeds to step (3) 〇), which will point to the memory of the array The address counter of the ground is set to the first address. The method then proceeds to step (315). In step (315), the method performs a confirm erase on the address location of a sector; the address location may be a single bit. A memory address of the location, or a 1/〇 or word location of the sector is addressed. If the acknowledgment erasure of the address location fails, the method continues to step (320). At step (32) 〇), this method determines whether the maximum pulse count has been reached. To the maximum pulse count ("YES" branch), the method continues to step (325), indicating that the device is indeed failing. If the maximum pulse count ("No" branch has not been reached), then the method proceeds to the step (330), in order to apply the erase pulse. In the step (330), the method is continued in the period of 8 to 12 sec., 92265 (revision) 28 1260639 = between: the two ends are erased by pulse application Each of the sections attached to the normal line position (for example, the pulse wave of the joint between the positions of a predetermined position is after the discharge of the section, and a period of .5 to 2 seconds (for example, ! milliseconds) will be A single-ended pulse wave is applied to a bit in the position of the residual line, and a bit that is in the range of 1 to 5 milliseconds (for example, 1 millisecond) is applied, and the bit is applied to the normal row position. . The method then knows (3) 5) to confirm the erasure of the current address location. If the confirmation of the location is erased, the method continues to step (3). The control determines whether the current bit or the 1/〇 address is the maximum address position. The memory unit $I/O address is not the maximum address location ("otherwise the address of the address counter is incremented to the next address location in step (340). The method then returns to step (315)' to perform the pair The next bit, the erase of the position is read. If it is determined in step (335) that the maximum address ("Yes" branch) has been reached, then the method proceeds to the soft sequence shown in Figure 13 to ensure The memory unit has not been over-erased. The erase method shown by 帛® is followed by a soft programming method to control the minimum (over-erased) normal bit and the f-bit VT of the blank state. The erased memory cell is a sum of small values of ντ below the blank state, and is not a conventional row drain potential element. Although it is not possible to store trapped holes in the nitride layer. :, but the electric field used to erase the memory cell is extremely high' and may reduce the local VT of the memory cell below the natural state. When this happens, the normal bit of the over-erased memory cell and Among the remaining bits The programming time of one or two bits will increase. Therefore, execute 92257 (revision) 29 1260639 shown in Figure 13 = programming method to eliminate the over-erased memory cells and to save the cycle Stable programming time. Figure 13 shows a method for performing a soft path on the flash memory array to ensure that the memory cell portion of the flash memory is not over-erased. In the step (cheer), The soft programming program is started, for example, the w7 can be transferred from the controller to the flash memory device: the soft programming program is called. In an alternative embodiment, the soft program can be It is part of the overall erase program and begins the soft programming procedure after completing the method shown in Figure 12. The method then proceeds to step (405) 'The address counter is now set to the first address. This method f Thereafter, proceeding to step (41〇). In step (410), the method performs a confirmation of the soft programming of the address position of »Hai. The confirmation should include a lower source voltage 'to suppress any sub-critical leakage. If the soft programming of the acknowledgement of the address location fails, the method continues to step (415) to determine if the maximum pulse count has been reached (eg, 5 pulses). If the maximum pulse has been reached. The wave count ("yes" branch) is indicated as a true failure at step (425). If the maximum pulse count has not been reached (&quot;no" branch), then the method proceeds to step (420) 'to make a soft programming A pulse wave is applied to the address location and returns to step (410) to confirm if the address location has passed the soft programming confirmation condition. If the address location of the sector is passed in step (41), the method continues to step (43A), at which point it is determined whether the maximum address of the sector has been reached. If the maximum sector address (,, no branch) has not been reached, then the address location 30 92257 (revision) 1260639 of the address counter is moved to the secondary-address location in step (435), and the method returns to the step ( 4 〇 〇), the next address position in the memory array 夂 these steps. If it is determined in step (430) that the ', ', and 5's are set ("Yes" branch), then the method enters the 4th attack address order. The second eraser of Figure 14 shows a method for performing a second erase process on a flash memory column in accordance with the present invention to ensure that the soft edit is performed. The method begins with the second erase program of ^~4^ such as 'can be'-the command is transmitted from control 11 to set to flash. I have thought about the state machine on the clothes and called the second erase program. In an embodiment, the second erasing procedure may be the method of the overall erasing procedure after the methods shown in FIG. 12 and FIG. 13 begin the wiping of the private sequence. The party S then enters the step (5G5), at this time

The counter is set to the first address position. The method then proceeds to step U 51〇): In step (51〇), the method performs a confirm erase on the address locations of one region of the memory array. The address location may be a memory address of a single bit location, or a 1/〇 or word location of the segment. If the (4) recording confirmation fails, the method continues: : (52 〇). In the step (52〇) towel, the method determines whether a large pulse count has been taken. If the maximum pulse count has been reached ("Yes, the method continues to step (530), indicating a true failure of the device. If the maximum pulse count has not been reached (&quot;No" branch), Then the party goes to step (525) to apply the erase pulse. In step (525), the method applies a wipe pulse to the period of 8 to 12 milliseconds for a period of 92257 (revision) 31 1260639. Each of the remaining line positions of the segment and the normal line position (eg, a 10 millisecond pulse). After a period of discharge, a single-ended pulse is applied for a duration of 0.5 to 2 milliseconds (eg, i milliseconds) To the bit in the margin row position, then apply a single-ended pulse to the normal row = centered bit for a duration of 5 to 2 milliseconds (eg, 1 millisecond). The method then returns to the step (other), in order to confirm the erasure of the current address location. If the current address location confirmation erase is passed, the method proceeds to step (535) to determine whether the current bit or I/O address is the maximum address location. If If the pre-memory unit or the IP address is not the maximum address location "branch", then the address location of the address counter is incremented to the next address location in step (5). The method then returns to step (510) to perform the Erase of the next address position: Confirm. If it is determined in step (535) that the maximum address ("Yes" branch) has been reached, then the method ends and the device returns to normal operation. For other purposes, the present invention includes the full description and specific features of the second embodiment, but it will be understood by those skilled in the art that the present invention is also possible. Therefore, the present invention will be included in _ &quot All such changes, modifications, and variations within the spirit and scope of the invention are to be construed as merely referring to the embodiments of the various embodiments. One or more other features of other embodiments [Simplified illustrations] 92257 (Revised) 32 1260639 Figure 1 is a side cross-sectional view of each of the early embodiments in which the present invention can be implemented; 2nd It is used to explain a normal area of a programmed memory unit and the double bit of the attached area: in the double bit chart; °丨思早 7L side view section 罘3 picture is the material explanation due to double: [The over-programming of the element will result in uneven charge accumulation. The central area = double-dimensional memory unit side view; the early middle picture is used to explain the residual charge after using only single-ended erase_ early 兀(4) The double-dimensional unit of the central area erased and wiped is close to the memory unit at the edge of the array—there is a side view of the side of the array; and the fifth picture is used to explain the removal after the erase according to the present. Stayed in the double position of the array near the array I - early residual charge, the production of _, ° has been early in the central area of the ^ 兀 饫 饫 饫 饫 饫 饫 饫 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; The present invention is directed to a block diagram of various system-oriented systems of the month. Figure 7 is an array of ancient two-bit flash memory arrays according to the present invention: sub-port: 16-bit memory $8 64-section-part a top view of the two-dimensional memory unit of the two-dimensional memory unit: Figure 1. According to the present invention - a first Yuan ντ change value /, brother: bit 兀 edit / time between the relationship diagram; process and is according to the invention oriented ν τ change value charge loss and the relationship between the column and erase cycle; 92257 (revision) 33 1260639 The η diagram is used to determine the relatively high v-parameter parameters for programming the second-dimensional memory unit based on the method of the present invention, the value and the choice of the second-bit method. Figure 12 is a flow chart of a method for performing erase confirmation on a unit according to the 'I + 啜叼-face of the present invention; FIG. 13 is for performing the erase confirmation method according to the present invention. A flow chart of a method for bi-directional music U-picture (four) programming, ·= early memory of the memory single force 14 picture is used to perform the double-bit method after performing the soft programming method according to the present invention ί Two-way brother 13 _ A flowchart of the method of performing the confirmation erase.仏早7&quot;Array of memory cells [Main component symbol description] Array of double bits 4 First region 6 Second region 9 P-type substrate region 12 Polycrystalline seconds layer 16 Nitride seconds layer 20 Boron ion core implant 24 Conductive portion 28, 39 second charge 32 first bit line 40 extra bit area 46 charge 68 5 fe, body array 5, 42 8 10 14 18 22 26, 38 30 34 44 60 central channel double bit memory The second bit line normal bit region system of the oxide layer in the oxide layer of the oxide layer

69 64Κ Section 92257 (Revised) 34 1260639 62 Address Decoder 64 Command Logic Component 65 State Machine 66 Voltage Generator Component 70 64K Block 72 ΟΝΟ Stacking Strip 74 Polycrystalline Second Strand 76 Row 78 First Contact 79 Second contact 82 first dual bit memory unit 84 second dual bit memory unit 86 third double bit memory unit 88 fourth double bit memory unit 88, 90, 92, 94 select gate 96 first switch 98 Second switch 100 third switch 35 92257 (revision)

Claims (1)

Brother 9 2 1 Ο Ο 2 9 6 Patent Application Amendment Patent Application Revision (April 19, 1995) 1 · A ΟΝΟ double-bit memory early element (1 用来 for programming in dual-bit mode A method of bits in ' 8 2 ' 8 4,8 6,8 8 ), the method package comprising the steps of: applying a programmed pulse wave to the dual bit memory unit (1 〇, 8 2, 8 4 At least one bit of 86, 88) by applying a voltage to the drain of the at least one bit and simultaneously applying a voltage to the gate of the at least one bit; ® confirming the at least one bit The VT change value is in the range of about 2 volts to about 2.5 volts; and the step of repeatedly applying a programming pulse until the VT change of the at least one bit is at about 2 〇 至 to about 2.5 volts In the range. 2. The method of claim 1, wherein the step of applying a programming pulse comprises the steps of: applying a voltage ranging from about 5 volts to about 5 5 volts to the drain, and simultaneously A voltage is applied to the gate from a voltage of about 9.25 volts to about 9.5 volts. 3. The method of claim 1, wherein the double-bit § hex unit (10, 82, 84, 86, 88) operates in a two-bit mode, wherein the ΟΝΟ double-bit The memory unit (1, 82, 84, 86, 88) has a normal bit and a residual bit, wherein the normal bit and the residual bit are programmed. 4. A method for determining programming parameters to program a dual-bit memory cell array in the two-bit mode working 92257 (revision) / 9. 126^639 (6-method, the method comprises the following steps: , bit TL Performing a pre-processing and erasing cycle on at least one of the arrays, then performing accelerated baking, at least one of the programming and erasing cycles, and accelerating at least one of the arrays The bit-to-electricity determines the increment of the VT change value to = dry out at least one of the at least one array of the additional array; and 70 &lt; electrical determines several programming parameters so that it can be connected Programming the memory cells within the increased VT change value internally includes a programming pulse width, a potential of the programming pulse at i of the bit, and a current on the pole of the bit Programming one of the pulse potentials. ' M 5. For the method of applying the fourth item, the programming pulse width is about 9.25 volts to the gate potential of 9.5 volts and about 5 volts to About 5.5 volts, the potential of the drain is about 〇 5 microseconds. 6. The method of claim 5, further comprising the steps of: setting command logic (64) and state machine (65) to facilitate programming of the selected drain and gate potentials The increased ντ change value. 7. A system for programming a dual bit memory cell array (68) operating in a dual bit mode, the system comprising: ΟΝΟ dual bit flash memory cell array (); coupled to the address of the dual bit flash memory cell array (68) 92257 (revision) 2 L_- address % code component (6 2 ), the address decoder component (a) is adapted to provide a pair Accessing the bits of the dual bit flash memory cells; a voltage generator (66) adapted to provide an appropriate voltage for the 0Ν0 dual bit flash memory cells The bit is programmed and erased; and a command logic component (64) including a state machine (65) coupled to the array and the address decoder component ( 62), and is operable to control the voltage production For (66), the command logic component (64) and the state machine (65) are adapted to program at least one bit by programming: selecting the at least one bit; applying a programming pulse, the programming pulse will a first voltage is applied to a drain of the at least one bit and a second voltage is applied to the gate of the at least one bit; confirming that the VT change of the at least one bit is between about 2.0 volts to about 2.5 volts And the step of repeatedly applying a programming pulse until the VT change value of the at least one bit is in the range of about 2.0 volts to about 2.5 volts. 8. The system of claim 7, wherein the voltage applied to the drain is in the range of about 5.0 volts to about 5.5 volts and the voltage applied to the gate is about 9.25 volts. Up to a range of approximately 9.5 volts. 9. The system of claim 8 wherein the programming pulse has a duration of about 0.5 microseconds. 10. The system of claim 7, wherein the dual-element Lv Yiyi cell array (6 8) operates in a two-bit mode, wherein each 3 92257 (corrected version) Φ. changes II Φ Change II · μ·« ·μ «ΐΜ·Μ**ΜνΊ&gt;ι^ ' One of the two-bit memory cells has normal bits and residual bits, wherein the normal bits and the reserved bits Is programmed. 92257 (revision) 4