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AU2001283185A1 - Method and system for dual bit memory erase verification - Google Patents

Method and system for dual bit memory erase verification

Info

Publication number
AU2001283185A1
AU2001283185A1 AU2001283185A AU8318501A AU2001283185A1 AU 2001283185 A1 AU2001283185 A1 AU 2001283185A1 AU 2001283185 A AU2001283185 A AU 2001283185A AU 8318501 A AU8318501 A AU 8318501A AU 2001283185 A1 AU2001283185 A1 AU 2001283185A1
Authority
AU
Australia
Prior art keywords
bit memory
erase verification
dual bit
memory erase
dual
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001283185A
Inventor
Edward V. Bautista
Pau-Ling Chen
Darlene Hamilton
Weng Fook Lee
Keith H. Wong
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of AU2001283185A1 publication Critical patent/AU2001283185A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
AU2001283185A 2000-11-21 2001-08-07 Method and system for dual bit memory erase verification Abandoned AU2001283185A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/717,550 US6331951B1 (en) 2000-11-21 2000-11-21 Method and system for embedded chip erase verification
US09717550 2000-11-21
PCT/US2001/024828 WO2002043073A1 (en) 2000-11-21 2001-08-07 Method and system for dual bit memory erase verification

Publications (1)

Publication Number Publication Date
AU2001283185A1 true AU2001283185A1 (en) 2002-06-03

Family

ID=24882474

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001283185A Abandoned AU2001283185A1 (en) 2000-11-21 2001-08-07 Method and system for dual bit memory erase verification

Country Status (9)

Country Link
US (1) US6331951B1 (en)
EP (1) EP1350253B1 (en)
JP (1) JP4601250B2 (en)
KR (1) KR100788491B1 (en)
CN (1) CN1322515C (en)
AU (1) AU2001283185A1 (en)
DE (1) DE60143125D1 (en)
TW (1) TW519652B (en)
WO (1) WO2002043073A1 (en)

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US7130213B1 (en) 2001-12-06 2006-10-31 Virage Logic Corporation Methods and apparatuses for a dual-polarity non-volatile memory cell
US6992938B1 (en) * 2001-12-06 2006-01-31 Virage Logic Corporation Methods and apparatuses for test circuitry for a dual-polarity non-volatile memory cell
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US7190620B2 (en) 2002-01-31 2007-03-13 Saifun Semiconductors Ltd. Method for operating a memory device
US6639844B1 (en) * 2002-03-13 2003-10-28 Advanced Micro Devices, Inc. Overerase correction method
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US6700822B1 (en) * 2002-05-15 2004-03-02 Taiwan Semiconductor Manufacturing Company Pre-decoder for glitch free word line addressing in a memory device
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DE60230129D1 (en) * 2002-07-10 2009-01-15 St Microelectronics Srl Line selection circuit for memory cell array
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
JP2004079602A (en) * 2002-08-12 2004-03-11 Fujitsu Ltd Nonvolatile memory having a trap layer
US6735114B1 (en) 2003-02-04 2004-05-11 Advanced Micro Devices, Inc. Method of improving dynamic reference tracking for flash memory unit
US6975541B2 (en) * 2003-03-24 2005-12-13 Saifun Semiconductors Ltd Alternating application of pulses on two sides of a cell
US6956768B2 (en) * 2003-04-15 2005-10-18 Advanced Micro Devices, Inc. Method of programming dual cell memory device to store multiple data states per cell
US6822909B1 (en) 2003-04-24 2004-11-23 Advanced Micro Devices, Inc. Method of controlling program threshold voltage distribution of a dual cell memory device
US6775187B1 (en) 2003-04-24 2004-08-10 Advanced Micro Devices, Inc. Method of programming a dual cell memory device
US6778442B1 (en) 2003-04-24 2004-08-17 Advanced Micro Devices, Inc. Method of dual cell memory device operation for improved end-of-life read margin
US6768673B1 (en) 2003-04-24 2004-07-27 Advanced Micro Devices, Inc. Method of programming and reading a dual cell memory device
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
EP1656677A1 (en) * 2003-08-13 2006-05-17 Koninklijke Philips Electronics N.V. Improved erase and read schemes for charge trapping non-volatile memories
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7206224B1 (en) * 2004-04-16 2007-04-17 Spansion Llc Methods and systems for high write performance in multi-bit flash memory devices
US6834012B1 (en) * 2004-06-08 2004-12-21 Advanced Micro Devices, Inc. Memory device and methods of using negative gate stress to correct over-erased memory cells
US6987696B1 (en) * 2004-07-06 2006-01-17 Advanced Micro Devices, Inc. Method of improving erase voltage distribution for a flash memory array having dummy wordlines
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7042766B1 (en) 2004-07-22 2006-05-09 Spansion, Llc Method of programming a flash memory device using multilevel charge storage
US7042767B2 (en) * 2004-08-02 2006-05-09 Spansion, Llc Flash memory unit and method of programming a flash memory device
US7180775B2 (en) * 2004-08-05 2007-02-20 Msystems Ltd. Different numbers of bits per cell in non-volatile memory devices
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
EP1686592A3 (en) 2005-01-19 2007-04-25 Saifun Semiconductors Ltd. Partial erase verify
US7167398B1 (en) * 2005-02-23 2007-01-23 Spansion L.L.C. System and method for erasing a memory cell
US7158416B2 (en) * 2005-03-15 2007-01-02 Infineon Technologies Flash Gmbh & Co. Kg Method for operating a flash memory device
US7113431B1 (en) * 2005-03-29 2006-09-26 Spansion Llc Quad bit using hot-hole erase for CBD control
US7184313B2 (en) 2005-06-17 2007-02-27 Saifun Semiconductors Ltd. Method circuit and system for compensating for temperature induced margin loss in non-volatile memory cells
US8116142B2 (en) 2005-09-06 2012-02-14 Infineon Technologies Ag Method and circuit for erasing a non-volatile memory cell
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
JP4672024B2 (en) * 2005-12-15 2011-04-20 スパンション エルエルシー Nonvolatile memory device and control method of nonvolatile memory device
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7319615B1 (en) 2006-08-02 2008-01-15 Spansion Llc Ramp gate erase for dual bit flash memory
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US7672159B2 (en) * 2007-01-05 2010-03-02 Macronix International Co., Ltd. Method of operating multi-level cell
US7548462B2 (en) * 2007-06-29 2009-06-16 Macronix International Co., Ltd. Double programming methods of a multi-level-cell nonvolatile memory
CN101923900B (en) * 2009-06-09 2014-06-11 北京兆易创新科技股份有限公司 Erasing method and device for non-volatile memory
KR200458048Y1 (en) * 2009-09-14 2012-01-18 배승관 Locking device with adjustable wire length
CN102890617B (en) * 2011-07-18 2015-06-10 群联电子股份有限公司 Memory control method, memory controller and memory storage device
KR102569820B1 (en) * 2018-10-25 2023-08-24 에스케이하이닉스 주식회사 Memory controller and operating method thereof
TWI822596B (en) * 2023-02-23 2023-11-11 華邦電子股份有限公司 Memory device and erasing method thereof

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DE69630320T2 (en) * 1996-06-14 2004-07-29 Macronix International Co. Ltd., Hsinchu SIDE MODE FLOATING GATE MEMORY ARRANGEMENT WITH MULTI-BIT CELLS
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KR100227638B1 (en) 1996-11-22 1999-11-01 김영환 Erasing circuit of a flash memory
JP3409986B2 (en) * 1997-01-31 2003-05-26 株式会社東芝 Multi-valued memory
US5928370A (en) 1997-02-05 1999-07-27 Lexar Media, Inc. Method and apparatus for verifying erasure of memory blocks within a non-volatile memory structure
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
KR100257854B1 (en) 1997-12-10 2000-06-01 김영환 How to erase flash memory
JP3672435B2 (en) * 1998-04-22 2005-07-20 富士通株式会社 Nonvolatile memory device
KR20000030974A (en) 1998-10-29 2000-06-05 김영환 Method and device for verifying elimination of serial flash memory

Also Published As

Publication number Publication date
WO2002043073A1 (en) 2002-05-30
CN1322515C (en) 2007-06-20
KR100788491B1 (en) 2007-12-24
EP1350253B1 (en) 2010-09-22
JP4601250B2 (en) 2010-12-22
TW519652B (en) 2003-02-01
US6331951B1 (en) 2001-12-18
CN1478281A (en) 2004-02-25
JP2004515024A (en) 2004-05-20
EP1350253A1 (en) 2003-10-08
KR20030048159A (en) 2003-06-18
DE60143125D1 (en) 2010-11-04

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