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FR3058561B1 - Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif - Google Patents

Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif Download PDF

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Publication number
FR3058561B1
FR3058561B1 FR1660682A FR1660682A FR3058561B1 FR 3058561 B1 FR3058561 B1 FR 3058561B1 FR 1660682 A FR1660682 A FR 1660682A FR 1660682 A FR1660682 A FR 1660682A FR 3058561 B1 FR3058561 B1 FR 3058561B1
Authority
FR
France
Prior art keywords
temperature
semiconductor element
healing
producing
highly resistive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1660682A
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English (en)
Other versions
FR3058561A1 (fr
Inventor
Oleg Kononchuk
Isabelle Bertrand
Luciana Capello
Marcel Broekaart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1660682A priority Critical patent/FR3058561B1/fr
Priority to EP17198392.7A priority patent/EP3319113B1/fr
Priority to TW106136638A priority patent/TWI742183B/zh
Priority to SG10201708819SA priority patent/SG10201708819SA/en
Priority to JP2017212630A priority patent/JP7088663B2/ja
Priority to CN201711068704.2A priority patent/CN108022840A/zh
Priority to KR1020170145981A priority patent/KR102408553B1/ko
Priority to US15/803,447 priority patent/US10510531B2/en
Publication of FR3058561A1 publication Critical patent/FR3058561A1/fr
Application granted granted Critical
Publication of FR3058561B1 publication Critical patent/FR3058561B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H10P14/6529—
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10P14/2905—
    • H10P14/3456—
    • H10P14/6322—
    • H10P14/65—
    • H10P14/6903—
    • H10P32/302—
    • H10P34/422—
    • H10P36/07—
    • H10P90/00—
    • H10P90/12—
    • H10P90/1906—
    • H10P90/1908—
    • H10P90/1914—
    • H10P95/90—
    • H10W10/181—
    • H10P90/1916—

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Formation Of Insulating Films (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un élément semi-conducteur, le procédé comportant une étape de traitement thermique rapide exposant un substrat comprenant un support présentant une résistivité supérieure à 1000 ohm. cm à une température crête susceptible de détériorer la résistivité du support. Selon l'invention, l'étape de traitement thermique rapide est suivie d'un traitement thermique de guérison exposant le substrat à une température de guérison comprise entre 800°C et 1250°C et présentant une vitesse de refroidissement inférieure à 5°C/sec lorsque la température de guérison est comprise entre 1250°C et 1150°C, inférieure à 20 °/sec lorsque la température de guérison est comprise entre 1150°C et 1100°C, et inférieure à 50°C/sec lorsque la température de guérison est comprise entre 1100°C et 800°C.
FR1660682A 2016-11-04 2016-11-04 Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif Expired - Fee Related FR3058561B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR1660682A FR3058561B1 (fr) 2016-11-04 2016-11-04 Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif
EP17198392.7A EP3319113B1 (fr) 2016-11-04 2017-10-25 Procédé de fabrication d'un élément semi-conducteur comprenant un substrat hautement résistif
TW106136638A TWI742183B (zh) 2016-11-04 2017-10-25 用於製作包含高電阻底材之半導體元件之方法
SG10201708819SA SG10201708819SA (en) 2016-11-04 2017-10-26 Method Of Fabrication Of A Semiconductor Element Comprising A Highly Resistive Substrate
JP2017212630A JP7088663B2 (ja) 2016-11-04 2017-11-02 高抵抗基板を含む半導体素子の作製方法
CN201711068704.2A CN108022840A (zh) 2016-11-04 2017-11-03 包括高电阻基板的半导体元件的制造方法
KR1020170145981A KR102408553B1 (ko) 2016-11-04 2017-11-03 고 저항성 기판을 포함하는 반도체 소자의 제조 방법
US15/803,447 US10510531B2 (en) 2016-11-04 2017-11-03 Method of fabrication of a semiconductor element comprising a highly resistive substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1660682A FR3058561B1 (fr) 2016-11-04 2016-11-04 Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif
FR1660682 2016-11-04

Publications (2)

Publication Number Publication Date
FR3058561A1 FR3058561A1 (fr) 2018-05-11
FR3058561B1 true FR3058561B1 (fr) 2018-11-02

Family

ID=57963300

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1660682A Expired - Fee Related FR3058561B1 (fr) 2016-11-04 2016-11-04 Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif

Country Status (8)

Country Link
US (1) US10510531B2 (fr)
EP (1) EP3319113B1 (fr)
JP (1) JP7088663B2 (fr)
KR (1) KR102408553B1 (fr)
CN (1) CN108022840A (fr)
FR (1) FR3058561B1 (fr)
SG (1) SG10201708819SA (fr)
TW (1) TWI742183B (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3037438B1 (fr) 2015-06-09 2017-06-16 Soitec Silicon On Insulator Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges
FR3106236B1 (fr) * 2020-01-15 2021-12-10 Soitec Silicon On Insulator Procédé de fabrication d’un capteur d’image
FR3126169B1 (fr) * 2021-08-12 2024-08-30 St Microelectronics Tours Sas Procédé de fabrication de composants radiofréquence
CN114156179A (zh) * 2021-10-29 2022-03-08 中国科学院上海微系统与信息技术研究所 一种改善绝缘层上硅晶圆表面粗糙度的方法
FR3149425B1 (fr) * 2023-06-05 2025-11-28 Soitec Silicon On Insulator Substrat comprenant une couche dielectrique enterree epaisse et procede de preparation d’un tel substrat

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JPS5928346A (ja) * 1982-08-10 1984-02-15 Toshiba Corp 半導体基板の処理方法
US4868133A (en) 1988-02-11 1989-09-19 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using RTA
US6544656B1 (en) 1999-03-16 2003-04-08 Shin-Etsu Handotai Co., Ltd. Production method for silicon wafer and silicon wafer
FR2838865B1 (fr) 2002-04-23 2005-10-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee
FR2860341B1 (fr) 2003-09-26 2005-12-30 Soitec Silicon On Insulator Procede de fabrication de structure multicouche a pertes diminuees
EP1677344B1 (fr) * 2003-10-21 2013-11-06 SUMCO Corporation Procede pour fabriquer une tranche de silicium avec resistivite elevee et procede pour fabriquer une tranche epitaxiale et une tranche soi
DE102004041378B4 (de) * 2004-08-26 2010-07-08 Siltronic Ag Halbleiterscheibe mit Schichtstruktur mit geringem Warp und Bow sowie Verfahren zu ihrer Herstellung
KR20080101654A (ko) 2007-05-18 2008-11-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체장치
US7820534B2 (en) * 2007-08-10 2010-10-26 Mitsubishi Electric Corporation Method of manufacturing silicon carbide semiconductor device
KR20090042375A (ko) * 2007-10-26 2009-04-30 주식회사 알.에프.텍 유에스비 플러그, 유에스비 플러그용 에이브이 소켓 및 이를 갖는 유에스비 커넥터 장치
US7932138B2 (en) * 2007-12-28 2011-04-26 Viatron Technologies Inc. Method for manufacturing thin film transistor
KR101007244B1 (ko) * 2008-04-10 2011-01-13 주식회사 비아트론 박막 트랜지스터 제조방법
JP5276863B2 (ja) * 2008-03-21 2013-08-28 グローバルウェーハズ・ジャパン株式会社 シリコンウェーハ
FR2933233B1 (fr) 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
JP4415062B1 (ja) * 2009-06-22 2010-02-17 富士フイルム株式会社 薄膜トランジスタ及び薄膜トランジスタの製造方法
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FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
KR102010752B1 (ko) 2009-12-04 2019-08-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 표시 장치
FR2973158B1 (fr) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator Procédé de fabrication d'un substrat de type semi-conducteur sur isolant pour applications radiofréquences
US20150037967A1 (en) * 2011-04-06 2015-02-05 Peter Wilshaw Controlling impurities in a wafer for an electronic circuit
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US9768056B2 (en) 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
JP2016082093A (ja) * 2014-10-17 2016-05-16 信越半導体株式会社 貼り合わせウェーハの製造方法
FR3029682B1 (fr) * 2014-12-04 2017-12-29 Soitec Silicon On Insulator Substrat semi-conducteur haute resistivite et son procede de fabrication
JP6344271B2 (ja) 2015-03-06 2018-06-20 信越半導体株式会社 貼り合わせ半導体ウェーハ及び貼り合わせ半導体ウェーハの製造方法
US9881832B2 (en) * 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
FR3037438B1 (fr) 2015-06-09 2017-06-16 Soitec Silicon On Insulator Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges
CN105977152B (zh) * 2016-05-09 2019-01-29 浙江大学 〈311〉直拉硅片的一种热处理方法

Also Published As

Publication number Publication date
JP7088663B2 (ja) 2022-06-21
EP3319113A1 (fr) 2018-05-09
TWI742183B (zh) 2021-10-11
FR3058561A1 (fr) 2018-05-11
JP2018107428A (ja) 2018-07-05
KR102408553B1 (ko) 2022-06-14
SG10201708819SA (en) 2018-06-28
US20180130698A1 (en) 2018-05-10
EP3319113B1 (fr) 2019-07-31
KR20180050239A (ko) 2018-05-14
TW201818474A (zh) 2018-05-16
US10510531B2 (en) 2019-12-17
CN108022840A (zh) 2018-05-11

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