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FR2860341B1 - Procede de fabrication de structure multicouche a pertes diminuees - Google Patents

Procede de fabrication de structure multicouche a pertes diminuees

Info

Publication number
FR2860341B1
FR2860341B1 FR0311347A FR0311347A FR2860341B1 FR 2860341 B1 FR2860341 B1 FR 2860341B1 FR 0311347 A FR0311347 A FR 0311347A FR 0311347 A FR0311347 A FR 0311347A FR 2860341 B1 FR2860341 B1 FR 2860341B1
Authority
FR
France
Prior art keywords
manufacturing
multilayer structure
lower multilayer
lowered lower
lowered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR0311347A
Other languages
English (en)
Other versions
FR2860341A1 (fr
Inventor
Jean Pierre Raskin
Dimitri Lederer
Francois Brunier
Sylvie Ponchaut
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Katholieke Universiteit Leuven
Soitec SA
Original Assignee
INIVERSITE CATHOLIQUE DE LOUVA
Katholieke Universiteit Leuven
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0311347A priority Critical patent/FR2860341B1/fr
Application filed by INIVERSITE CATHOLIQUE DE LOUVA, Katholieke Universiteit Leuven, Soitec SA filed Critical INIVERSITE CATHOLIQUE DE LOUVA
Priority to CNA2004800278168A priority patent/CN1856873A/zh
Priority to EP04769623A priority patent/EP1665368A1/fr
Priority to PCT/IB2004/003340 priority patent/WO2005031853A1/fr
Priority to JP2006527229A priority patent/JP2007507093A/ja
Priority to KR1020067005608A priority patent/KR100789527B1/ko
Priority to US10/572,799 priority patent/US20070032040A1/en
Priority to EP04761498A priority patent/EP1665367A2/fr
Priority to KR1020067005842A priority patent/KR20060118437A/ko
Priority to JP2006527512A priority patent/JP2007507100A/ja
Priority to CNB2004800280083A priority patent/CN100477152C/zh
Priority to PCT/BE2004/000137 priority patent/WO2005031842A2/fr
Publication of FR2860341A1 publication Critical patent/FR2860341A1/fr
Application granted granted Critical
Publication of FR2860341B1 publication Critical patent/FR2860341B1/fr
Priority to US11/389,469 priority patent/US7585748B2/en
Priority to JP2012014182A priority patent/JP5518911B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P3/00—Waveguides; Transmission lines of the waveguide type
    • H01P3/003—Coplanar lines
    • H01P3/006—Conductor backed coplanar waveguides
    • H10P14/20—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10P90/1916—
    • H10W10/011—
    • H10W10/10—
    • H10W10/181—
    • H10W44/216—
FR0311347A 2003-09-26 2003-09-26 Procede de fabrication de structure multicouche a pertes diminuees Expired - Lifetime FR2860341B1 (fr)

Priority Applications (14)

Application Number Priority Date Filing Date Title
FR0311347A FR2860341B1 (fr) 2003-09-26 2003-09-26 Procede de fabrication de structure multicouche a pertes diminuees
CNB2004800280083A CN100477152C (zh) 2003-09-26 2004-09-27 用于制作由半导体材料制成的多层结构的方法
PCT/IB2004/003340 WO2005031853A1 (fr) 2003-09-26 2004-09-27 Procede pour fabriquer une structure multicouche constituee de materiaux semi-conducteurs
JP2006527229A JP2007507093A (ja) 2003-09-26 2004-09-27 抵抗損を低減させた積層型半導体構造の製造方法
KR1020067005608A KR100789527B1 (ko) 2003-09-26 2004-09-27 반도체 재료로 제조되는 다층구조체 제조방법
US10/572,799 US20070032040A1 (en) 2003-09-26 2004-09-27 Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses
EP04761498A EP1665367A2 (fr) 2003-09-26 2004-09-27 Procede de fabrication d'une structure semiconductrice multicouche a pertes ohmiques reduites
KR1020067005842A KR20060118437A (ko) 2003-09-26 2004-09-27 저항손을 감소시키는 다층 반도체 구조의 제조 방법
CNA2004800278168A CN1856873A (zh) 2003-09-26 2004-09-27 制造具有降低的欧姆损耗的多层半导体结构的方法
EP04769623A EP1665368A1 (fr) 2003-09-26 2004-09-27 Procede pour fabriquer une structure multicouche constituee de materiaux semi-conducteurs
PCT/BE2004/000137 WO2005031842A2 (fr) 2003-09-26 2004-09-27 Procede de fabrication d'une structure semiconductrice multicouche a pertes ohmiques reduites
JP2006527512A JP2007507100A (ja) 2003-09-26 2004-09-27 半導体材料製の多層構造を製造するための方法
US11/389,469 US7585748B2 (en) 2003-09-26 2006-03-24 Process for manufacturing a multilayer structure made from semiconducting materials
JP2012014182A JP5518911B2 (ja) 2003-09-26 2012-01-26 半導体材料製の多層構造を製造するための方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0311347A FR2860341B1 (fr) 2003-09-26 2003-09-26 Procede de fabrication de structure multicouche a pertes diminuees

Publications (2)

Publication Number Publication Date
FR2860341A1 FR2860341A1 (fr) 2005-04-01
FR2860341B1 true FR2860341B1 (fr) 2005-12-30

Family

ID=34307223

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0311347A Expired - Lifetime FR2860341B1 (fr) 2003-09-26 2003-09-26 Procede de fabrication de structure multicouche a pertes diminuees

Country Status (7)

Country Link
US (1) US7585748B2 (fr)
EP (1) EP1665368A1 (fr)
JP (2) JP2007507100A (fr)
KR (1) KR100789527B1 (fr)
CN (1) CN100477152C (fr)
FR (1) FR2860341B1 (fr)
WO (1) WO2005031853A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11373856B2 (en) 2017-01-26 2022-06-28 Soitec Support for a semiconductor structure
US11462676B2 (en) 2017-03-31 2022-10-04 Soitec Method for adjusting the stress state of a piezoelectric film and acoustic wave device employing such a film
US12424995B2 (en) 2019-07-12 2025-09-23 Soitec Method for manufacturing a structure comprising a thin layer transferred onto a support provided with a charge trapping layer
US12445102B2 (en) 2019-03-29 2025-10-14 Soitec Method for preparing a thin layer of ferroelectric material
US12525483B2 (en) 2020-07-28 2026-01-13 Soitec Method for transferring a thin layer onto a support substrate provided with a charge-trapping layer

Families Citing this family (39)

* Cited by examiner, † Cited by third party
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FR2896618B1 (fr) * 2006-01-23 2008-05-23 Soitec Silicon On Insulator Procede de fabrication d'un substrat composite
FR2919427B1 (fr) * 2007-07-26 2010-12-03 Soitec Silicon On Insulator Structure a reservoir de charges.
US8535996B2 (en) * 2008-03-13 2013-09-17 Soitec Substrate having a charged zone in an insulating buried layer
JP2009231376A (ja) 2008-03-19 2009-10-08 Shin Etsu Handotai Co Ltd Ｓｏｉウェーハ及び半導体デバイスならびにｓｏｉウェーハの製造方法
FR2933235B1 (fr) * 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat bon marche et procede de fabrication associe
FR2933233B1 (fr) 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
FR2933234B1 (fr) * 2008-06-30 2016-09-23 S O I Tec Silicon On Insulator Tech Substrat bon marche a structure double et procede de fabrication associe
TWI484622B (zh) * 2009-09-08 2015-05-11 Soitec Silicon On Insulator 用以製造基材的方法
FR2953640B1 (fr) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
US9553013B2 (en) 2010-12-24 2017-01-24 Qualcomm Incorporated Semiconductor structure with TRL and handle wafer cavities
US9754860B2 (en) 2010-12-24 2017-09-05 Qualcomm Incorporated Redistribution layer contacting first wafer through second wafer
US9624096B2 (en) 2010-12-24 2017-04-18 Qualcomm Incorporated Forming semiconductor structure with device layers and TRL
KR101913322B1 (ko) * 2010-12-24 2018-10-30 퀄컴 인코포레이티드 반도체 소자들을 위한 트랩 리치 층
US8536021B2 (en) 2010-12-24 2013-09-17 Io Semiconductor, Inc. Trap rich layer formation techniques for semiconductor devices
US8481405B2 (en) 2010-12-24 2013-07-09 Io Semiconductor, Inc. Trap rich layer with through-silicon-vias in semiconductor devices
JP5673170B2 (ja) * 2011-02-09 2015-02-18 信越半導体株式会社 貼り合わせ基板、貼り合わせ基板の製造方法、半導体デバイス、及び半導体デバイスの製造方法
JP6118757B2 (ja) * 2014-04-24 2017-04-19 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6100200B2 (ja) 2014-04-24 2017-03-22 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
JP6102823B2 (ja) 2014-05-14 2017-03-29 信越半導体株式会社 Ｓｏｉ基板の評価方法
EP4120320A1 (fr) * 2015-03-03 2023-01-18 GlobalWafers Co., Ltd. Films de silicium polycristallin de piégeage de charge sur des substrats de silicium avec une contrainte de film commandable
JP6353814B2 (ja) * 2015-06-09 2018-07-04 信越半導体株式会社 貼り合わせｓｏｉウェーハの製造方法
FR3037438B1 (fr) 2015-06-09 2017-06-16 Soitec Silicon On Insulator Procede de fabrication d'un element semi-conducteur comprenant une couche de piegeage de charges
US9721969B2 (en) 2015-06-30 2017-08-01 Globalfoundries Singapore Pte. Ltd. Creation of wide band gap material for integration to SOI thereof
FR3058561B1 (fr) 2016-11-04 2018-11-02 Soitec Procede de fabrication d'un element semi-conducteur comprenant un substrat hautement resistif
KR102652250B1 (ko) 2018-07-05 2024-03-28 소이텍 집적 무선 주파수 디바이스를 위한 기판 및 이를 제조하기 위한 방법
FR3121548B1 (fr) 2021-03-30 2024-02-16 Soitec Silicon On Insulator Procede de preparation d’un substrat avance, notamment pour des applications photoniques
FR3113184B1 (fr) 2020-07-28 2022-09-16 Soitec Silicon On Insulator Procede de preparation d’un substrat support, et procede de report d’une couche mince sur ce substrat support
WO2022045087A1 (fr) * 2020-08-25 2022-03-03 株式会社村田製作所 Dispositif à ondes élastiques
FR3129029B1 (fr) 2021-11-09 2023-09-29 Soitec Silicon On Insulator Procede de preparation d’un substrat support muni d’une couche de piegeage de charges
FR3129028B1 (fr) 2021-11-09 2023-11-10 Soitec Silicon On Insulator Procede de preparation d’un substrat support muni d’une couche de piegeage de charges
FR3137493B1 (fr) 2022-06-29 2024-10-04 Soitec Silicon On Insulator Procede de fabrication d’une structure comportant une couche barriere a la diffusion d’especes atomiques
FR3137490B1 (fr) 2022-07-04 2024-05-31 Soitec Silicon On Insulator Procede de fabrication d’une structure comportant une couche barriere a la diffusion d’especes atomiques
EP4627621A1 (fr) 2022-11-29 2025-10-08 Soitec Support comprenant une couche de piegeage de charges, substrat composite comprenant un tel support et procedes de fabrication associes
WO2024115414A1 (fr) 2022-11-29 2024-06-06 Soitec Support comprenant une couche de piegeage de charges, substrat composite comprenant un tel support et procedes de fabrication associes
EP4627620A1 (fr) 2022-11-29 2025-10-08 Soitec Support comprenant une couche de piegeage de charges, substrat composite comprenant un tel support et procedes de fabrication associes
FR3145444B1 (fr) 2023-01-27 2025-11-21 Soitec Silicon On Insulator Structure comprenant une couche superficielle reportee sur un support muni d’une couche de piegeage de charges a contamination limitee et procede de fabrication
FR3146020B1 (fr) 2023-02-20 2025-07-18 Soitec Silicon On Insulator Support comprenant une couche de piégeage de charges, substrat composite comprenant un tel support et procédé de fabrication associés
WO2025103654A1 (fr) 2023-11-17 2025-05-22 Soitec Support comprenant une couche de piegeage de charges electriques pour un substrat composite et procede de selection d'un tel support
FR3155623A1 (fr) 2023-11-17 2025-05-23 Soitec Support comprenant une couche de piegeage de charges electriques pour un substrat composite et procede de selection d’un tel support.

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US20070032040A1 (en) 2003-09-26 2007-02-08 Dimitri Lederer Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11373856B2 (en) 2017-01-26 2022-06-28 Soitec Support for a semiconductor structure
US11462676B2 (en) 2017-03-31 2022-10-04 Soitec Method for adjusting the stress state of a piezoelectric film and acoustic wave device employing such a film
US12445102B2 (en) 2019-03-29 2025-10-14 Soitec Method for preparing a thin layer of ferroelectric material
US12424995B2 (en) 2019-07-12 2025-09-23 Soitec Method for manufacturing a structure comprising a thin layer transferred onto a support provided with a charge trapping layer
US12525483B2 (en) 2020-07-28 2026-01-13 Soitec Method for transferring a thin layer onto a support substrate provided with a charge-trapping layer

Also Published As

Publication number Publication date
US20060166451A1 (en) 2006-07-27
JP5518911B2 (ja) 2014-06-11
JP2012104855A (ja) 2012-05-31
CN100477152C (zh) 2009-04-08
JP2007507100A (ja) 2007-03-22
WO2005031853A1 (fr) 2005-04-07
US7585748B2 (en) 2009-09-08
FR2860341A1 (fr) 2005-04-01
EP1665368A1 (fr) 2006-06-07
KR100789527B1 (ko) 2007-12-28
CN1860603A (zh) 2006-11-08
KR20060069496A (ko) 2006-06-21

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