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FR3058561B1 - PROCESS FOR PRODUCING A SEMICONDUCTOR ELEMENT COMPRISING A HIGHLY RESISTIVE SUBSTRATE - Google Patents

PROCESS FOR PRODUCING A SEMICONDUCTOR ELEMENT COMPRISING A HIGHLY RESISTIVE SUBSTRATE Download PDF

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Publication number
FR3058561B1
FR3058561B1 FR1660682A FR1660682A FR3058561B1 FR 3058561 B1 FR3058561 B1 FR 3058561B1 FR 1660682 A FR1660682 A FR 1660682A FR 1660682 A FR1660682 A FR 1660682A FR 3058561 B1 FR3058561 B1 FR 3058561B1
Authority
FR
France
Prior art keywords
temperature
semiconductor element
healing
producing
highly resistive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1660682A
Other languages
French (fr)
Other versions
FR3058561A1 (en
Inventor
Oleg Kononchuk
Isabelle Bertrand
Luciana Capello
Marcel Broekaart
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR1660682A priority Critical patent/FR3058561B1/en
Priority to TW106136638A priority patent/TWI742183B/en
Priority to EP17198392.7A priority patent/EP3319113B1/en
Priority to SG10201708819SA priority patent/SG10201708819SA/en
Priority to JP2017212630A priority patent/JP7088663B2/en
Priority to KR1020170145981A priority patent/KR102408553B1/en
Priority to CN201711068704.2A priority patent/CN108022840A/en
Priority to US15/803,447 priority patent/US10510531B2/en
Publication of FR3058561A1 publication Critical patent/FR3058561A1/en
Application granted granted Critical
Publication of FR3058561B1 publication Critical patent/FR3058561B1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H10P14/6529—
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10P14/2905—
    • H10P14/3456—
    • H10P14/6322—
    • H10P14/65—
    • H10P14/6903—
    • H10P32/302—
    • H10P34/422—
    • H10P36/07—
    • H10P90/00—
    • H10P90/12—
    • H10P90/1906—
    • H10P90/1908—
    • H10P90/1914—
    • H10P95/90—
    • H10W10/181—
    • H10P90/1916—

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un élément semi-conducteur, le procédé comportant une étape de traitement thermique rapide exposant un substrat comprenant un support présentant une résistivité supérieure à 1000 ohm. cm à une température crête susceptible de détériorer la résistivité du support. Selon l'invention, l'étape de traitement thermique rapide est suivie d'un traitement thermique de guérison exposant le substrat à une température de guérison comprise entre 800°C et 1250°C et présentant une vitesse de refroidissement inférieure à 5°C/sec lorsque la température de guérison est comprise entre 1250°C et 1150°C, inférieure à 20 °/sec lorsque la température de guérison est comprise entre 1150°C et 1100°C, et inférieure à 50°C/sec lorsque la température de guérison est comprise entre 1100°C et 800°C.The invention relates to a method of manufacturing a semiconductor element, the method comprising a step of rapid heat treatment exposing a substrate comprising a support having a resistivity greater than 1000 ohm. cm at a peak temperature likely to deteriorate the resistivity of the support. According to the invention, the rapid heat treatment step is followed by a healing heat treatment exposing the substrate to a healing temperature of between 800°C and 1250°C and exhibiting a cooling rate of less than 5°C/ sec when the healing temperature is between 1250°C and 1150°C, less than 20°/sec when the healing temperature is between 1150°C and 1100°C, and less than 50°C/sec when the temperature healing temperature is between 1100°C and 800°C.

FR1660682A 2016-11-04 2016-11-04 PROCESS FOR PRODUCING A SEMICONDUCTOR ELEMENT COMPRISING A HIGHLY RESISTIVE SUBSTRATE Expired - Fee Related FR3058561B1 (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR1660682A FR3058561B1 (en) 2016-11-04 2016-11-04 PROCESS FOR PRODUCING A SEMICONDUCTOR ELEMENT COMPRISING A HIGHLY RESISTIVE SUBSTRATE
TW106136638A TWI742183B (en) 2016-11-04 2017-10-25 Method of fabrication of a semiconductor element comprising a highly resistive substrate
EP17198392.7A EP3319113B1 (en) 2016-11-04 2017-10-25 Method of fabrication of a semiconductor element comprising a highly resistive substrate
SG10201708819SA SG10201708819SA (en) 2016-11-04 2017-10-26 Method Of Fabrication Of A Semiconductor Element Comprising A Highly Resistive Substrate
JP2017212630A JP7088663B2 (en) 2016-11-04 2017-11-02 Method for manufacturing semiconductor devices including high resistance substrates
KR1020170145981A KR102408553B1 (en) 2016-11-04 2017-11-03 Method of fabrication of a semiconductor element comprising a highly resistive substrate
CN201711068704.2A CN108022840A (en) 2016-11-04 2017-11-03 The manufacture method of semiconductor element including high resistance substrate
US15/803,447 US10510531B2 (en) 2016-11-04 2017-11-03 Method of fabrication of a semiconductor element comprising a highly resistive substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1660682 2016-11-04
FR1660682A FR3058561B1 (en) 2016-11-04 2016-11-04 PROCESS FOR PRODUCING A SEMICONDUCTOR ELEMENT COMPRISING A HIGHLY RESISTIVE SUBSTRATE

Publications (2)

Publication Number Publication Date
FR3058561A1 FR3058561A1 (en) 2018-05-11
FR3058561B1 true FR3058561B1 (en) 2018-11-02

Family

ID=57963300

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1660682A Expired - Fee Related FR3058561B1 (en) 2016-11-04 2016-11-04 PROCESS FOR PRODUCING A SEMICONDUCTOR ELEMENT COMPRISING A HIGHLY RESISTIVE SUBSTRATE

Country Status (8)

Country Link
US (1) US10510531B2 (en)
EP (1) EP3319113B1 (en)
JP (1) JP7088663B2 (en)
KR (1) KR102408553B1 (en)
CN (1) CN108022840A (en)
FR (1) FR3058561B1 (en)
SG (1) SG10201708819SA (en)
TW (1) TWI742183B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3037438B1 (en) 2015-06-09 2017-06-16 Soitec Silicon On Insulator METHOD OF MANUFACTURING A SEMICONDUCTOR ELEMENT COMPRISING A LOAD TRAPPING LAYER
FR3106236B1 (en) * 2020-01-15 2021-12-10 Soitec Silicon On Insulator Manufacturing process of an image sensor
FR3126169B1 (en) * 2021-08-12 2024-08-30 St Microelectronics Tours Sas Manufacturing process of radiofrequency components
CN114156179A (en) * 2021-10-29 2022-03-08 中国科学院上海微系统与信息技术研究所 Method for improving surface roughness of silicon wafer on insulating layer
FR3149425B1 (en) * 2023-06-05 2025-11-28 Soitec Silicon On Insulator SUBSTRATE COMPRISING A THICK BURIED DIELECTRIC LAYER AND METHOD FOR PREPARING SUCH A SUBSTRATE

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EP1677344B1 (en) * 2003-10-21 2013-11-06 SUMCO Corporation Process for producing high resistivity silicon wafer, and process for producing epitaxial wafer and soi wafer
DE102004041378B4 (en) * 2004-08-26 2010-07-08 Siltronic Ag Semiconductor wafer with a layered structure with low warp and bow and process for its production
US7750345B2 (en) 2007-05-18 2010-07-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
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KR20090042375A (en) * 2007-10-26 2009-04-30 주식회사 알.에프.텍 USB plug, AV socket for USB plug and USB connector device having same
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US7932138B2 (en) * 2007-12-28 2011-04-26 Viatron Technologies Inc. Method for manufacturing thin film transistor
JP5276863B2 (en) * 2008-03-21 2013-08-28 グローバルウェーハズ・ジャパン株式会社 Silicon wafer
FR2933233B1 (en) 2008-06-30 2010-11-26 Soitec Silicon On Insulator GOOD RESISTANCE HIGH RESISTIVITY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
JP4415062B1 (en) * 2009-06-22 2010-02-17 富士フイルム株式会社 THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR
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CN105977152B (en) * 2016-05-09 2019-01-29 浙江大学 <311> A heat treatment method for Czochralski silicon wafers

Also Published As

Publication number Publication date
EP3319113A1 (en) 2018-05-09
JP2018107428A (en) 2018-07-05
SG10201708819SA (en) 2018-06-28
KR20180050239A (en) 2018-05-14
TW201818474A (en) 2018-05-16
EP3319113B1 (en) 2019-07-31
KR102408553B1 (en) 2022-06-14
JP7088663B2 (en) 2022-06-21
FR3058561A1 (en) 2018-05-11
CN108022840A (en) 2018-05-11
TWI742183B (en) 2021-10-11
US20180130698A1 (en) 2018-05-10
US10510531B2 (en) 2019-12-17

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