DE69720158D1 - Speicherschaltungen mit eingebautem Selbsttest - Google Patents

Speicherschaltungen mit eingebautem Selbsttest

Info

Publication number: DE69720158D1
Authority: DE; Germany
Prior art keywords: built; self; test; memory circuits; circuits
Prior art date: 1996-12-19
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Lifetime

Application number

DE69720158T

Other languages

English (en)

Other versions

DE69720158T2 (de

Inventor

Danny R Cline

Theo J Powell

Kuong H Hii

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Texas Instruments Inc

Original Assignee

Texas Instruments Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1996-12-19

Filing date

1997-12-19

Publication date

2003-04-30

1997-12-19 Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc

2003-04-30 Publication of DE69720158D1 publication Critical patent/DE69720158D1/de

2003-10-23 Application granted granted Critical

2003-10-23 Publication of DE69720158T2 publication Critical patent/DE69720158T2/de

2017-12-20 Anticipated expiration legal-status Critical

Status Expired - Lifetime legal-status Critical Current

Classifications

- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

DE69720158T 1996-12-19 1997-12-19 Speicherschaltungen mit eingebautem Selbsttest Expired - Lifetime DE69720158T2 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
US3350896P	1996-12-19	1996-12-19

Publications (2)

Publication Number	Publication Date
DE69720158D1 true DE69720158D1 (de)	2003-04-30
DE69720158T2 DE69720158T2 (de)	2003-10-23

Family

ID=21870800

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE69720158T Expired - Lifetime DE69720158T2 (de)	1996-12-19	1997-12-19	Speicherschaltungen mit eingebautem Selbsttest

Country Status (6)

Country	Link
US (1)	US5936900A (de)
EP (1)	EP0849743B1 (de)
JP (1)	JPH10199294A (de)
KR (1)	KR100679586B1 (de)
DE (1)	DE69720158T2 (de)
TW (1)	TW368657B (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US20020071325A1 (en) *	1996-04-30	2002-06-13	Hii Kuong Hua	Built-in self-test arrangement for integrated circuit memory devices
US6353563B1 (en)	1996-04-30	2002-03-05	Texas Instruments Incorporated	Built-in self-test arrangement for integrated circuit memory devices
JPH117761A (ja) *	1997-06-13	1999-01-12	Toshiba Corp	画像用メモリ
JP4183333B2 (ja) *	1999-03-23	2008-11-19	株式会社沖マイクロデザイン	半導体集積回路およびその試験方法
US6111801A (en) *	1999-04-30	2000-08-29	Stmicroelectronics, Inc.	Technique for testing wordline and related circuitry of a memory array
US6239634B1 (en)	1999-05-19	2001-05-29	Parthus Technologies	Apparatus and method for ensuring the correct start-up and locking of a delay locked loop
US6262608B1 (en)	1999-05-21	2001-07-17	Parthus Technologies Plc	Delay locked loop with immunity to missing clock edges
WO2001051940A1 (en) *	2000-01-14	2001-07-19	Parthus Technologies Plc	An algorithmic test pattern generator, with built-in-self-test (bist) capabilities, for functional testing of a circuit
JP2004013987A (ja) *	2002-06-06	2004-01-15	Toshiba Corp	半導体記憶装置
JP3544203B2 (ja)	2002-08-30	2004-07-21	沖電気工業株式会社	テスト回路、そのテスト回路を内蔵した半導体集積回路装置、及びそのテスト方法
JP3484181B1 (ja)	2002-09-02	2004-01-06	沖電気工業株式会社	半導体テスト回路
US20040062123A1 (en) *	2002-09-27	2004-04-01	Oki Electric Industry Co., Ltd.	Nonvolatile semiconductor memory device able to detect test mode
US7007211B1 (en)	2002-10-04	2006-02-28	Cisco Technology, Inc.	Testing self-repairing memory of a device
US7320100B2 (en)	2003-05-20	2008-01-15	Cray Inc.	Apparatus and method for memory with bit swapping on the fly and testing
US7184916B2 (en) *	2003-05-20	2007-02-27	Cray Inc.	Apparatus and method for testing memory cards
WO2005027349A1 (en) *	2003-09-08	2005-03-24	Infineon Technologies Ag	Reset-free delay-locked loop
US8250295B2 (en)	2004-01-05	2012-08-21	Smart Modular Technologies, Inc.	Multi-rank memory module that emulates a memory module having a different number of ranks
JP2006012046A (ja) *	2004-06-29	2006-01-12	Oki Electric Ind Co Ltd	システムｌｓｉ
KR100702300B1 (ko) *	2005-05-30	2007-03-30	주식회사 하이닉스반도체	테스트 제어 회로를 갖는 반도체 메모리 장치
US7324392B2 (en) *	2005-06-09	2008-01-29	Texas Instruments Incorporated	ROM-based memory testing
US20070033471A1 (en) *	2005-06-09	2007-02-08	Raguram Damodaran	Hardware Configuration of pBIST
JP2007064648A (ja) *	2005-08-29	2007-03-15	Nec Electronics Corp	半導体集積回路及びテスト方法
US7945823B2 (en) *	2006-03-02	2011-05-17	Netlogic Microsystems, Inc.	Programmable address space built-in self test (BIST) device and method for fault detection
US8001434B1 (en)	2008-04-14	2011-08-16	Netlist, Inc.	Memory board with self-testing capability
JP2008293652A (ja) *	2008-08-08	2008-12-04	Renesas Technology Corp	同期型半導体記憶装置およびそのテスト方法
US10607715B2 (en)	2017-06-13	2020-03-31	International Business Machines Corporation	Self-evaluating array of memory

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5249281A (en) *	1990-10-12	1993-09-28	Lsi Logic Corporation	Testable ram architecture in a microprocessor having embedded cache memory
JP3072531B2 (ja) *	1991-03-25	2000-07-31	安藤電気株式会社	集積回路試験装置のパターンメモリ回路
JP3474214B2 (ja) *	1992-10-22	2003-12-08	株式会社東芝	論理回路及びこの論理回路を備えたテスト容易化回路
US5617531A (en) *	1993-11-02	1997-04-01	Motorola, Inc.	Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
US5548553A (en) *	1994-12-12	1996-08-20	Digital Equipment Corporation	Method and apparatus for providing high-speed column redundancy
US5535164A (en) *	1995-03-03	1996-07-09	International Business Machines Corporation	BIST tester for multiple memories
US5689466A (en) *	1995-04-07	1997-11-18	National Semiconductor Corporation	Built in self test (BIST) for multiple RAMs
KR0152914B1 (ko) *	1995-04-21	1998-12-01	문정환	반도체 메모리장치
US5661729A (en) *	1995-04-28	1997-08-26	Song Corporation	Semiconductor memory having built-in self-test circuit
US5661732A (en) *	1995-05-31	1997-08-26	International Business Machines Corporation	Programmable ABIST microprocessor for testing arrays with two logical views
US5568437A (en) *	1995-06-20	1996-10-22	Vlsi Technology, Inc.	Built-in self test for integrated circuits having read/write memory
US5640509A (en) *	1995-10-03	1997-06-17	Intel Corporation	Programmable built-in self-test function for an integrated circuit
US5640404A (en) *	1996-08-05	1997-06-17	Vlsi Technology, Inc.	Limited probes device testing for high pin count digital devices
US5734661A (en) *	1996-09-20	1998-03-31	Micron Technology, Inc.	Method and apparatus for providing external access to internal integrated circuit test circuits

1997
- 1997-11-14 US US08/970,308 patent/US5936900A/en not_active Expired - Lifetime
- 1997-12-17 KR KR1019970069931A patent/KR100679586B1/ko not_active Expired - Lifetime
- 1997-12-19 DE DE69720158T patent/DE69720158T2/de not_active Expired - Lifetime
- 1997-12-19 EP EP97310337A patent/EP0849743B1/de not_active Expired - Lifetime
- 1997-12-19 JP JP9351611A patent/JPH10199294A/ja active Pending
1998
- 1998-03-23 TW TW086119248A patent/TW368657B/zh not_active IP Right Cessation

Also Published As

Publication number	Publication date
KR100679586B1 (ko)	2007-04-19
DE69720158T2 (de)	2003-10-23
US5936900A (en)	1999-08-10
TW368657B (en)	1999-09-01
EP0849743B1 (de)	2003-03-26
KR19980064254A (ko)	1998-10-07
EP0849743A2 (de)	1998-06-24
JPH10199294A (ja)	1998-07-31
EP0849743A3 (de)	1999-08-04

Publication	Publication Date	Title
DE69720158D1 (de)	2003-04-30	Speicherschaltungen mit eingebautem Selbsttest
DE69525421D1 (de)	2002-03-21	Integrierte Speicherschaltungsanordnung
DE69731810D1 (de)	2005-01-05	Halbleiter-Festwertspeicher
DE69220715D1 (de)	1997-08-14	Eingebaute Selbsttestschaltung
DE69923244D1 (de)	2005-02-24	Magnetoresistiven Speicheranordnungen
GB9715240D0 (en)	1997-09-24	Configuration memory integrated circuit
DE69714659D1 (de)	2002-09-19	Halbleiterspeicherbauteil mit Kondensator
DE69520512D1 (de)	2001-05-10	Halbleiterspeicher mit eingebautem Cachespeicher
DE69739934D1 (de)	2010-08-26	Integrierte Schaltung
DE69711794D1 (de)	2002-05-16	Logik-Auswahlschaltung
DE60001291D1 (de)	2003-03-06	Halbleiterspeicherschaltung mit eingebauter Selbstprüfung und Selbstreparatur
DE69419951D1 (de)	1999-09-16	Halbleiterspeicher mit eingebauter Einbrennprüfung
DE69705118D1 (de)	2001-07-12	Speichervorrichtungsfolgeschaltung
DE69706947D1 (de)	2001-10-31	Halbleiterspeicher
DE69832348D1 (de)	2005-12-22	Speicherschaltung
DE69817955D1 (de)	2003-10-16	Assoziativspeicher
DE69829092D1 (de)	2005-03-31	Festwertspeicher
DE50003281D1 (de)	2003-09-18	Schaltung mit eingebautem selbsttest
DE69726225D1 (de)	2003-12-24	Leseschaltung
DE69317944D1 (de)	1998-05-20	Integrierte Speicherschaltung
DE69718896D1 (de)	2003-03-13	Halbleiterspeicheranordnung mit Redundanz
DE69823074D1 (de)	2004-05-19	Speicherschaltung mit variabler Latenz
DE19781611T1 (de)	1999-03-18	Speichertestgerät
DE69828021D1 (de)	2005-01-13	Halbleiterspeicheranordnung mit mehreren Banken
DE69722837D1 (de)	2003-07-24	Speicheranordnung mit überlagerter Busstruktur

Legal Events

Date	Code	Title	Description
2004-04-22	8364	No opposition during term of opposition