DE1290967B - Electronic storage element - Google Patents

Description

The invention relates to an electronic storage element with two input AND stages, a downstream OR stage and two of these downstream Non-stages, with the output of the last non-stage and an and stage fed back and the setting of the memory element by a clock signal and the holding of the Storage element takes place by a negated clock signal.

Such storage elements are for example by the German Auslegeschrift 1119 911 has become known. It is also known such memory elements to be used in modified form in electronic stepping mechanisms (German Interpretation document 1155 484).

In the German Auslegeschrift 1155 484 it is already pointed out that that on the transition behavior of the complementary ones driving the storage elements Clock signals must meet certain requirements in order to work reliably to achieve the storage elements. With these storage elements, the rear Edge steepness of the complementary clock signals in defined, permanently assigned to one another There are limits. If this is not the case, this can be stored by the storage element Signal will be lost. To remedy this deficiency, is in the last-mentioned reference proposed to assign a further holding stage to the memory element, from the to the storing signal and is controlled by the output signal of the memory element, whereby the time of the valence change of the complementary clock signals is bridged. The holding stage can, for example, be designed as an under stage. That so far for example, two input undatages existing memory element is now required three input and stages. When creating large-scale digital systems with a large number of storage elements represents the additional holding stage of the storage element represents a considerable increase in effort.

The invention is based on the object by the additional To avoid the effort resulting from the holding stage.

According to the invention, this object is achieved in that the memory element driving negated clock signal before the disappearance of the affirmative, the memory element driving clock signal occurs.

The invention is shown schematically on the basis of one in the drawing Embodiment explained in more detail. It shows F i g. 1 the well-known electronic Memory element, FIG. FIG. 2 shows a signal diagram for the memory element according to FIG. 1.

The memory element according to FIG. 1 consists of two input and stages 1, 2, which control an or-not stage, which is followed by a non-stage 4. The output A is fed back to the input and stage 2. And level 1 represents the riser and the lower stage 2 represent the holding stage of the storage element Setting stage 1 acts a signal e to be stored, which when a clock signal occurs t is accepted into the storage element and occurs at output A of the same. At the holding stage 2 acts in addition to the feedback A, a negated clock signal i.

The memory element described is known in principle (references cited above), but has not been regarded as usable in this embodiment. However, the memory element works without jumps when it is triggered by clock signals t, i * of the form according to FIG. 2 a is controlled. Like the signal diagram according to FIG. 2 a, the negated clock signal i * is already corresponding to L when the clock signal t is still corresponding to L.

In FIG. 2 a are not those when the frequency change of the clock signals occurring switching times (due to transistors) are taken into account. In the F i g. 2 b this is the case, but only an enlarged section of the signal diagram according to FIG. 2 a is shown. The slash marks the "0" - and "L" areas indicated.

At time a , the clock signal t has reached the value corresponding to L, and since the signal e to be stored corresponding to L is present at this time, this input signal e is accepted by the memory element, and a signal A corresponding to L occurs at the output of the memory element until the time c on. Before the clock signal t corresponding to L disappears at time c, the negated clock signal 7 * corresponding to L already occurs beforehand at time b. The output signal A corresponding to L is already present and is now also held by the and stage 2 in addition to the and stage 1 from time b. The output signal A corresponding to L is held by the holding stage 2 until time d, at which the negated clock signal i * again becomes 0 and the clock signal t corresponds to L. Since the input signal e to be stored is 0 at this time and also subsequently , so the output signal A of the storage element is also 0 accordingly.

As in the signal diagram according to FIG. As can be seen from FIG. 2b, when the clock signal i * corresponding to L occurs while the clock signal t corresponding to L is present, an output signal A corresponding to L which is free of junction points is achieved. The output signal A is made up of the temporally overlapping output signals 1 ', 2' of the setting stage 1 and holding stage 2 according to FIG. 1 together.

As a clock signal generator, for example, one according to the patent 1222 972 can be used, which consists of at least two static memories with time elements exists, with the memory at the outputs, for example, at 90 ° to each other offset signals occur that control such a logic signal masking circuit, that at their outputs signals t, i * in the form according to FIG. 2 occur.

Claims (1)

Claim: Electronic storage element with two input and stages, a downstream OR stage and two of these downstream non-stages, where the output of the last non-level is fed back to an und level and the setting of the memory element by an affirmative clock signal and the holding of the memory element takes place by a negated clock signal, d a d u r c 1i indicates that the negated Clock signal before the disappearance of the affirmed clock signal that drives the memory element occurs.