[go: up one dir, main page]

MX2019015119A - Dispositivo de procesamiento de datos y metodo de procesamiento de datos. - Google Patents

Dispositivo de procesamiento de datos y metodo de procesamiento de datos.

Info

Publication number
MX2019015119A
MX2019015119A MX2019015119A MX2019015119A MX2019015119A MX 2019015119 A MX2019015119 A MX 2019015119A MX 2019015119 A MX2019015119 A MX 2019015119A MX 2019015119 A MX2019015119 A MX 2019015119A MX 2019015119 A MX2019015119 A MX 2019015119A
Authority
MX
Mexico
Prior art keywords
data processing
bits
processing device
processing method
group interleaving
Prior art date
Application number
MX2019015119A
Other languages
English (en)
Other versions
MX392428B (es
Inventor
Shinohara Yuji
Yamamoto Makiko
Ikegaya Ryoji
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of MX2019015119A publication Critical patent/MX2019015119A/es
Publication of MX392428B publication Critical patent/MX392428B/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
    • H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computational Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

La presente tecnología se refiere a un dispositivo de procesamiento de datos y un método de procesamiento de datos que puede garantizar una alta calidad de la comunicación en la transmisión de datos usando códigos de LDPC. En la intercalación en forma de grupos, un código de LDPC que tiene un código de longitud N de 64800 bitios, y una tasa r de codificación de 9/15 es intercalada en una unidad de un grupo de bitios de 360 bitios. En la intercalación en forma de grupos, una secuencia de grupos de bitios del código LDPC que han sido sometidos a la intercalación en forma de grupos se devuelve a una secuencia original. La presente tecnología puede ser aplicada a, por ejemplo, un caso en donde la transmisión de datos se realiza usando los códigos de LDPC.
MX2019015119A 2014-02-19 2015-02-05 Dispositivo de procesamiento de datos y metodo de procesamiento de datos. MX392428B (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014030014A JP2015156532A (ja) 2014-02-19 2014-02-19 データ処理装置、及び、データ処理方法
PCT/JP2015/053183 WO2015125614A1 (ja) 2014-02-19 2015-02-05 データ処理装置、及び、データ処理方法

Publications (2)

Publication Number Publication Date
MX2019015119A true MX2019015119A (es) 2020-02-12
MX392428B MX392428B (es) 2025-03-24

Family

ID=53878124

Family Applications (2)

Application Number Title Priority Date Filing Date
MX2019015119A MX392428B (es) 2014-02-19 2015-02-05 Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
MX2016010443A MX2016010443A (es) 2014-02-19 2015-02-05 Dispositivo de procesamiento de datos y metodo de procesamiento de datos.

Family Applications After (1)

Application Number Title Priority Date Filing Date
MX2016010443A MX2016010443A (es) 2014-02-19 2015-02-05 Dispositivo de procesamiento de datos y metodo de procesamiento de datos.

Country Status (6)

Country Link
US (3) US20170187392A1 (es)
JP (1) JP2015156532A (es)
KR (5) KR101752343B1 (es)
CA (1) CA2939481C (es)
MX (2) MX392428B (es)
WO (1) WO2015125614A1 (es)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2958240B1 (en) * 2013-02-08 2018-08-22 Saturn Licensing LLC Encoding and decoding of a rate 18/30 (3/5) ldpc code of length 64800
JP2015156532A (ja) 2014-02-19 2015-08-27 ソニー株式会社 データ処理装置、及び、データ処理方法
JP2015170912A (ja) * 2014-03-05 2015-09-28 ソニー株式会社 データ処理装置、及び、データ処理方法
JP2015179960A (ja) * 2014-03-19 2015-10-08 ソニー株式会社 データ処理装置、及び、データ処理方法
US10938608B2 (en) * 2015-11-19 2021-03-02 Sony Corporation Apparatus and method
JP6930374B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
JP6930375B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
JP6930377B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
JP6930376B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
US10354717B1 (en) * 2018-05-10 2019-07-16 Micron Technology, Inc. Reduced shifter memory system
DE102019200256B4 (de) * 2019-01-10 2020-07-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verschachteler
US11032023B1 (en) 2019-05-21 2021-06-08 Tarana Wireless, Inc. Methods for creating check codes, and systems for wireless communication using check codes
CN113708776B (zh) * 2020-05-20 2023-06-09 中国科学院上海高等研究院 基于ldpc码的编码方法、系统、介质及装置
CN113708777B (zh) * 2020-05-20 2023-06-13 中国科学院上海高等研究院 基于ldpc码的编码方法、系统、介质及装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7334181B2 (en) 2003-09-04 2008-02-19 The Directv Group, Inc. Method and system for providing short block length low density parity check (LDPC) codes
DE602006011240D1 (de) * 2005-06-21 2010-02-04 Samsung Electronics Co Ltd Vorrichtung und Methode zum Übermitteln/Empfangen von Daten in einem Mehrantennenkommunikationssystem unter Verwendung eines strukturierten Low Density Parity Check (LDPC) Codes
US8402337B2 (en) 2007-11-26 2013-03-19 Sony Corporation Data processing apparatus and data processing method as well as encoding apparatus and encoding method
EP2134051A1 (en) 2008-06-13 2009-12-16 THOMSON Licensing An adaptive QAM transmission scheme for improving performance on an AWGN channel
JP5664919B2 (ja) 2011-06-15 2015-02-04 ソニー株式会社 データ処理装置、及び、データ処理方法
KR20150005853A (ko) * 2013-07-05 2015-01-15 삼성전자주식회사 송신 장치 및 그의 신호 처리 방법
US20150082118A1 (en) * 2013-09-18 2015-03-19 Samsung Electronics Co., Ltd. Transmitting apparatus and puncturing method thereof
WO2015045897A1 (ja) * 2013-09-26 2015-04-02 ソニー株式会社 データ処理装置、及びデータ処理方法
US10396822B2 (en) * 2013-09-26 2019-08-27 Samsung Electronics Co., Ltd. Transmitting apparatus and signal processing method thereof
US10355714B2 (en) * 2013-10-04 2019-07-16 Samsung Electronics Co., Ltd. Transmitting apparatus and signal processing method thereof
JP2015156532A (ja) * 2014-02-19 2015-08-27 ソニー株式会社 データ処理装置、及び、データ処理方法
JP2015156534A (ja) * 2014-02-19 2015-08-27 ソニー株式会社 データ処理装置、及び、データ処理方法
JP2015170912A (ja) * 2014-03-05 2015-09-28 ソニー株式会社 データ処理装置、及び、データ処理方法

Also Published As

Publication number Publication date
US20180302107A1 (en) 2018-10-18
CA2939481C (en) 2021-09-14
CA2939481A1 (en) 2015-08-27
WO2015125614A1 (ja) 2015-08-27
KR101929407B1 (ko) 2018-12-14
KR102023155B1 (ko) 2019-09-20
KR20200140397A (ko) 2020-12-15
MX392428B (es) 2025-03-24
MX2016010443A (es) 2016-09-22
KR102189466B1 (ko) 2020-12-11
KR20170075815A (ko) 2017-07-03
KR20180133951A (ko) 2018-12-17
KR101752343B1 (ko) 2017-06-29
US10979080B2 (en) 2021-04-13
US20190372601A1 (en) 2019-12-05
KR20160121514A (ko) 2016-10-19
JP2015156532A (ja) 2015-08-27
KR102361969B1 (ko) 2022-02-14
US20170187392A1 (en) 2017-06-29
KR20190108194A (ko) 2019-09-23
US10425112B2 (en) 2019-09-24

Similar Documents

Publication Publication Date Title
MX2019015119A (es) Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
MX2019013109A (es) Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
MX2019015354A (es) Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
MX384170B (es) Dispositivo de procesamiento de datos y método de procesamiento de datos.
MX2019005297A (es) Dispositivo y metodo para procesar datos.
CL2019002276A1 (es) Método y sistemas para la compresión eficiente de lecturas de secuencias genómicas.
MX2016000458A (es) Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
MX2019010795A (es) Metodo de codificacion de video utilizando division de bloque de arbol binario.
MX2018006642A (es) Metodo de codificacion de datos tridimencionales, metodos de decodificacion de datos tridimensionales, dispositivo de codificacion de datos tridimensionales y dispositivo de decodificacion de datos tridimensionales.
MX372714B (es) Materiales tratados de substrato de metátesis y métodos para elaborar y usar los mismos.
MX2016000449A (es) Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
AR099619A1 (es) Polímero viscosificante para el tratamiento de una formación subterránea
MX2019015632A (es) Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
MX2016010164A (es) Aparato de transmision y metodo de modulacion del mismo.
MX371227B (es) Aparato de transmision y metodo de intercalacion del mismo.
BR112016027099A2 (pt) aparelho de transmissão
MX387085B (es) Entrelazador de bits para palabra codigo de revision de paridad de baja densidad que tiene una longitud de 16200 y un indice de codigo de 3/15 y mapeo de 64 simbolos, y metodo para entrelazar bits que utiliza el mismo.
PH12016500548A1 (en) Data transmission using optical codes
MX2019009589A (es) Transmisor y metodo de permutacion de paridad del mismo.
GB2512533A (en) Generating a code alphabet of symbols to generate codewords for words used with a program
MX373956B (es) Entrelazador de bits para palabra codigo de revision de paridad de baja densidad que tiene una longitud de 64800 y un indice de codigo de 5/15 y mapeo de 64 simbolos, y metodo para entrelazar bits que utiliza el mismo.
MX2016011779A (es) Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
MX373707B (es) Aparato de intercalado de paridad para codificar la informacion de señalizacion de longitud variable y metodo de intercalado de paridad que lo utiliza.
MX2016011965A (es) Aparato de transmision y metodo de intercalacion del mismo.
MX370107B (es) Aparato de transmision y metodo de intercalacion del mismo.