[go: up one dir, main page]

US20170187392A1 - Data processing device and data processing method - Google Patents

Data processing device and data processing method Download PDF

Info

Publication number
US20170187392A1
US20170187392A1 US15/118,331 US201515118331A US2017187392A1 US 20170187392 A1 US20170187392 A1 US 20170187392A1 US 201515118331 A US201515118331 A US 201515118331A US 2017187392 A1 US2017187392 A1 US 2017187392A1
Authority
US
United States
Prior art keywords
parity check
check matrix
code
ldpc code
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/118,331
Other languages
English (en)
Inventor
Ryoji IKEGAYA
Makiko YAMAMOTO
Yuji Shinohara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Saturn Licensing LLC
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAMAMOTO, MAKIKO, IKEGAYA, RYOJI, SHINOHARA, YUJI
Publication of US20170187392A1 publication Critical patent/US20170187392A1/en
Assigned to SATURN LICENSING LLC reassignment SATURN LICENSING LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SONY CORPORATION
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2792—Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2778—Interleaver using block-wise interleaving, e.g. the interleaving matrix is sub-divided into sub-matrices and the permutation is performed in blocks of sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/20—Modulator circuits; Transmitter circuits
    • H04L27/2032—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner
    • H04L27/2053—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases
    • H04L27/206—Modulator circuits; Transmitter circuits for discrete phase modulation, e.g. in which the phase of the carrier is modulated in a nominally instantaneous manner using more than one carrier, e.g. carriers with different phases using a pair of orthogonal carriers, e.g. quadrature carriers

Definitions

  • the present technology relates to a data processing device and a data processing method, and more particularly, to a data processing device and a data processing method which can ensure high communication quality in data transmission using, for example, an LDPC code.
  • a low density parity check (LDPC) code has a high error correction capability and has been widely adopted in transmission systems for digital broadcasting, for example, Digital Video Broadcasting (DVB)-S.2, DVB-T.2, and DVB-C.2 used in Europe, and Advanced Television Systems Committee (ATSC) 3.0 used in the U.S. (for example, see Non-Patent Document 1).
  • DVD Digital Video Broadcasting
  • DVB-T.2 DVB-T.2
  • DVB-C.2 used in Europe
  • ATSC Advanced Television Systems Committee 3.0 used in the U.S.
  • the recent study shows that the performance of an LDPC code becomes closer to a Shannon limit as the code length thereof becomes larger, similar to a turbo code.
  • the LDPC code has the property that the shortest distance is proportional to the code length. Therefore, the LDPC code has the advantages that block error probability characteristics are excellent and a so-called error floor phenomenon which is observed in the decoding characteristics of, for example, a turbo code rarely occurs.
  • an LDPC code serves as a symbol (changes to a symbol) of quadrature modulation (digital modulation), such as quadrature phase shift keying (QPSK), and the symbol is mapped to a signal point of the quadrature modulation and is transmitted.
  • quadrature modulation digital modulation
  • QPSK quadrature phase shift keying
  • the present technology has been made in view of the above-mentioned problems and an objective of the present technology is to ensure high communication quality in data transmission using LDPC codes.
  • a first data processing device/method includes: a coding unit/step that performs LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15; a group-wise interleaving unit/step that performs group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits; and a mapping unit/step that maps the LDPC code to any one of four signal points which are determined by a modulation method in a unit of 2 bits.
  • an (i+1)-th bit group from a head of the LDPC code is set as a bit group i and a sequence of bit groups 0 to 179 of the 64800-bit LDPC code is interleaved into a sequence of the following bit groups.
  • the LDPC code includes information bits and parity bits.
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table indicates positions of elements “1” in the information matrix portion for every 360 columns and includes the following.
  • the LDPC coding is performed on the basis of the parity check matrix of the LDPC code having a code length N of 64800 bits and a coding rate r of 9/15.
  • the group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits is performed.
  • the LDPC code is mapped to any one of four signal points which are determined by the modulation method in a unit of 2 bits.
  • the (i+1)-th bit group from the head of the LDPC code is set as the bit group i and a sequence of bit groups 0 to 179 of the 64800-bit LDPC code is interleaved into a sequence of the following bit groups.
  • the LDPC code includes the information bits and the parity bits.
  • the parity check matrix includes the information matrix portion corresponding to the information bits and the parity matrix portion corresponding to the parity bits.
  • the information matrix portion is represented by the parity check matrix initial value table.
  • the parity check matrix initial value table indicates the positions of the elements “1” in the information matrix portion for every 360 columns and includes the following.
  • a second data processing device/method includes: a group-wise deinterleaving unit/step that returns a sequence of an LDPC code, which has been subjected to group-wise interleaving and is obtained from data transmitted from a transmitting device, to an original sequence.
  • the transmitting device includes: a coding unit that performs LDPC coding on the basis of a parity check matrix of the LDPC code having a code length N of 64800 bits and a coding rate r of 9/15; a group-wise interleaving unit that performs the group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits; and a mapping unit that maps the LDPC code to any one of four signal points which are determined by a modulation method in a unit of 2 bits.
  • an (i+1)-th bit group from a head of the LDPC code is set as a bit group i and a sequence of bit groups 0 to 179 of the 64800-hit LDPC code is interleaved into a sequence of the following bit groups.
  • the LDPC code includes information bits and parity bits.
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table indicates positions of elements “1” in the information matrix portion for every 360 columns and includes the following.
  • the transmitting device includes: the coding unit that performs LDPC coding on the basis of the parity check matrix of the LDPC code having a code length N of 64800 bits and a coding rate r of 9/15; the group-wise interleaving unit that performs the group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits; and the mapping unit that maps the LDPC code to anyone of four signal points which are determined by the modulation method in a unit of 2 bits.
  • the (i+1)-th bit group from the head of the LDPC code is set as the bit group i and a sequence of bit groups 0 to 179 of the 64800-bit LDPC code is interleaved into a sequence of the following bit groups.
  • the LDPC code includes the information bits and the parity bits.
  • the parity check matrix includes the information matrix portion corresponding to the information bits and the parity matrix portion corresponding to the parity bits.
  • the information matrix portion is represented by the parity check matrix initial value table.
  • the parity check matrix initial value table indicates positions of elements “1” in the information matrix portion for every 360 columns and includes the following. A sequence of the bit groups of the LDPC code, which has been subjected to the group-wise interleaving and is obtained from the data transmitted from the transmitting device, is returned to the original sequence.
  • a third data processing device/method includes: a coding unit/step that performs LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15; a group-wise interleaving unit/step that performs group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits; and a mapping unit/step that maps the LDPC code to any one of 16 signal points which are determined by a modulation method in a unit of 4 bits.
  • an (i+1)-th bit group from a head of the LDPC code is set as a bit group i and a sequence of bit groups 0 to 179 of the 64800-bit LDPC code is interleaved into a sequence of the following bit groups.
  • the LDPC code includes information bits and parity bits.
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table indicates positions of elements “1” in the information matrix portion for every 360 columns and includes the following.
  • the LDPC coding is performed on the basis of the parity check matrix of the LDPC code having a code length N of 64800 bits and a coding rate r of 9/15.
  • the group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits is performed.
  • the LDPC code is mapped to any one of 16 signal points which are determined by the modulation method in a unit of 4 bits.
  • the (i+1)-th bit group from the head of the LDPC code is set as the bit group i and a sequence of bit groups 0 to 179 of the 64800-bit LDPC code is interleaved into a sequence of the following bit groups.
  • the LDPC code includes the information bits and the parity bits.
  • the parity check matrix includes the information matrix portion corresponding to the information bits and the parity matrix portion corresponding to the parity bits.
  • the information matrix portion is represented by the parity check matrix initial value table.
  • the parity check matrix initial value table indicates the positions of the elements “1” in the information matrix portion for every 360 columns and includes the following.
  • a fourth data processing device/method to the present technology includes a group-wise deinterleaving unit/step that returns a sequence of an LDPC code, which has been subjected to group-wise interleaving and is obtained from data transmitted from a transmitting device, to an original sequence.
  • the transmitting device includes: a coding unit that performs LDPC coding on the basis of a parity check matrix of the LDPC code having a code length N of 64800 bits and a coding rate r of 9/15; a group-wise interleaving unit that performs the group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits; and a mapping unit that maps the LDPC code to any one of 16 signal points which are determined by a modulation method in a unit of 4 bits.
  • an (i+1)-th bit group from a head of the LDPC code is set as a bit group i and a sequence of bit groups 0 to 179 of the 64800-bit LDPC code is interleaved into a sequence of the following bit groups.
  • the LDPC code includes information bits and parity bits.
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table indicates positions of elements “1” in the information matrix portion for every 360 columns and includes the following.
  • the transmitting device includes: the coding unit that performs LDPC coding on the basis of the parity check matrix of the LDPC code having a code length N of 64800 bits and a coding rater of 9/15; the group-wise interleaving unit that performs the group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits; and the mapping unit that maps the LDPC code to any one of 16 signal points which are determined by the modulation method in a unit of 4 bits.
  • the (i+1)-th bit group from the head of the LDPC code is set as the bit group i and a sequence of bit groups 0 to 179 of the 64800-bit LDPC code is interleaved into a sequence of the following bit groups.
  • the LDPC code includes the information bits and the parity bits.
  • the parity check matrix includes the information matrix portion corresponding to the information bits and the parity matrix portion corresponding to the parity bits.
  • the information matrix portion is represented by the parity check matrix initial value table.
  • the parity check matrix initial value table indicates positions of elements “1” in the information matrix portion for every 360 columns and includes the following. A sequence of the bit groups of the LDPC code, which has been subjected to the group-wise interleaving and is obtained from the data transmitted from the transmitting device, is returned to the original sequence.
  • a fifth data processing device/method according to the present technology includes: a coding unit/step that performs
  • LDPC coding on the basis of a parity check matrix of an LDPC code having a code length N of 64800 bits and a coding rate r of 9/15; a group-wise interleaving unit/step that performs group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits; and a mapping unit/step that maps the LDPC code to any one of 64 signal points which are determined by a modulation method in a unit of 6 bits.
  • an (i+1)-th bit group from a head of the LDPC code is set as a bit group i and a sequence of bit groups 0 to 179 of the 64800-bit LDPC code is interleaved into a sequence of the following bit groups.
  • the LDPC code includes information bits and parity bits.
  • the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits.
  • the information matrix portion is represented by a parity check matrix initial value table.
  • the parity check matrix initial value table indicates positions of elements “1” in the information matrix portion for every 360 columns and includes the following.
  • the LDPC coding is performed on the basis of the parity check matrix of the LDPC code having a code length N of 64800 bits and a coding rate r of 9/15.
  • the group-wise interleaving which interleaves the LDPC code in a unit of a bit group of 360 bits is performed.
  • the LDPC code is mapped to any one of 64 signal points which are determined by the modulation method in a unit of 6 bits.
  • the (i+1)-th bit group from the head of the LDPC code is set as the bit group i and a sequence of bit groups 0 to 179 of the 64800-bit LDPC code is interleaved into a sequence of the following bit groups.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computational Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
US15/118,331 2014-02-19 2015-02-05 Data processing device and data processing method Abandoned US20170187392A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2014030014A JP2015156532A (ja) 2014-02-19 2014-02-19 データ処理装置、及び、データ処理方法
JP2014-030014 2014-02-19
PCT/JP2015/053183 WO2015125614A1 (ja) 2014-02-19 2015-02-05 データ処理装置、及び、データ処理方法

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2015/053183 A-371-Of-International WO2015125614A1 (ja) 2014-02-19 2015-02-05 データ処理装置、及び、データ処理方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/945,361 Continuation US10425112B2 (en) 2014-02-19 2018-04-04 Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio

Publications (1)

Publication Number Publication Date
US20170187392A1 true US20170187392A1 (en) 2017-06-29

Family

ID=53878124

Family Applications (3)

Application Number Title Priority Date Filing Date
US15/118,331 Abandoned US20170187392A1 (en) 2014-02-19 2015-02-05 Data processing device and data processing method
US15/945,361 Active US10425112B2 (en) 2014-02-19 2018-04-04 Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio
US16/541,658 Active US10979080B2 (en) 2014-02-19 2019-08-15 Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio

Family Applications After (2)

Application Number Title Priority Date Filing Date
US15/945,361 Active US10425112B2 (en) 2014-02-19 2018-04-04 Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio
US16/541,658 Active US10979080B2 (en) 2014-02-19 2019-08-15 Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio

Country Status (6)

Country Link
US (3) US20170187392A1 (es)
JP (1) JP2015156532A (es)
KR (5) KR101752343B1 (es)
CA (1) CA2939481C (es)
MX (2) MX392428B (es)
WO (1) WO2015125614A1 (es)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180337693A1 (en) * 2014-03-19 2018-11-22 Saturn Licensing Llc Data processing device and data processing method
US10164661B2 (en) * 2014-03-05 2018-12-25 Saturn Licensing Llc Data processing device and data processing method
US10425112B2 (en) * 2014-02-19 2019-09-24 Saturn Licensing Llc Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio
US10938608B2 (en) * 2015-11-19 2021-03-02 Sony Corporation Apparatus and method
CN113708777A (zh) * 2020-05-20 2021-11-26 中国科学院上海高等研究院 基于ldpc码的编码方法、系统、介质及装置

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2958240B1 (en) * 2013-02-08 2018-08-22 Saturn Licensing LLC Encoding and decoding of a rate 18/30 (3/5) ldpc code of length 64800
JP6930374B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
JP6930375B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
JP6930377B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
JP6930376B2 (ja) * 2017-10-31 2021-09-01 ソニーグループ株式会社 送信装置及び送信方法
US10354717B1 (en) * 2018-05-10 2019-07-16 Micron Technology, Inc. Reduced shifter memory system
DE102019200256B4 (de) * 2019-01-10 2020-07-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verschachteler
US11032023B1 (en) 2019-05-21 2021-06-08 Tarana Wireless, Inc. Methods for creating check codes, and systems for wireless communication using check codes
CN113708776B (zh) * 2020-05-20 2023-06-09 中国科学院上海高等研究院 基于ldpc码的编码方法、系统、介质及装置

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150039973A1 (en) * 2013-07-05 2015-02-05 Samsung Electronics Co., Ltd. Transmitter apparatus and signal processing method thereof

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7334181B2 (en) 2003-09-04 2008-02-19 The Directv Group, Inc. Method and system for providing short block length low density parity check (LDPC) codes
DE602006011240D1 (de) * 2005-06-21 2010-02-04 Samsung Electronics Co Ltd Vorrichtung und Methode zum Übermitteln/Empfangen von Daten in einem Mehrantennenkommunikationssystem unter Verwendung eines strukturierten Low Density Parity Check (LDPC) Codes
US8402337B2 (en) 2007-11-26 2013-03-19 Sony Corporation Data processing apparatus and data processing method as well as encoding apparatus and encoding method
EP2134051A1 (en) 2008-06-13 2009-12-16 THOMSON Licensing An adaptive QAM transmission scheme for improving performance on an AWGN channel
JP5664919B2 (ja) 2011-06-15 2015-02-04 ソニー株式会社 データ処理装置、及び、データ処理方法
US20150082118A1 (en) * 2013-09-18 2015-03-19 Samsung Electronics Co., Ltd. Transmitting apparatus and puncturing method thereof
WO2015045897A1 (ja) * 2013-09-26 2015-04-02 ソニー株式会社 データ処理装置、及びデータ処理方法
US10396822B2 (en) * 2013-09-26 2019-08-27 Samsung Electronics Co., Ltd. Transmitting apparatus and signal processing method thereof
US10355714B2 (en) * 2013-10-04 2019-07-16 Samsung Electronics Co., Ltd. Transmitting apparatus and signal processing method thereof
JP2015156532A (ja) * 2014-02-19 2015-08-27 ソニー株式会社 データ処理装置、及び、データ処理方法
JP2015156534A (ja) * 2014-02-19 2015-08-27 ソニー株式会社 データ処理装置、及び、データ処理方法
JP2015170912A (ja) * 2014-03-05 2015-09-28 ソニー株式会社 データ処理装置、及び、データ処理方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150039973A1 (en) * 2013-07-05 2015-02-05 Samsung Electronics Co., Ltd. Transmitter apparatus and signal processing method thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10425112B2 (en) * 2014-02-19 2019-09-24 Saturn Licensing Llc Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio
US10979080B2 (en) 2014-02-19 2021-04-13 Saturn Licensing Llc Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio
US10164661B2 (en) * 2014-03-05 2018-12-25 Saturn Licensing Llc Data processing device and data processing method
US20190028122A1 (en) * 2014-03-05 2019-01-24 Saturn Licensing Llc Data processing device and data processing method
US10707903B2 (en) * 2014-03-05 2020-07-07 Saturn Licensing Llc Data processing device and data processing method
US11271595B2 (en) 2014-03-05 2022-03-08 Saturn Licensing Llc Data processing device and data processing method
US20180337693A1 (en) * 2014-03-19 2018-11-22 Saturn Licensing Llc Data processing device and data processing method
US10659080B2 (en) * 2014-03-19 2020-05-19 Saturn Licensing Llc Data processing device and data processing method
US11239863B2 (en) 2014-03-19 2022-02-01 Saturn Licensing Llc Data processing device and data processing method
US10938608B2 (en) * 2015-11-19 2021-03-02 Sony Corporation Apparatus and method
CN113708777A (zh) * 2020-05-20 2021-11-26 中国科学院上海高等研究院 基于ldpc码的编码方法、系统、介质及装置

Also Published As

Publication number Publication date
US20180302107A1 (en) 2018-10-18
CA2939481C (en) 2021-09-14
CA2939481A1 (en) 2015-08-27
WO2015125614A1 (ja) 2015-08-27
KR101929407B1 (ko) 2018-12-14
KR102023155B1 (ko) 2019-09-20
KR20200140397A (ko) 2020-12-15
MX392428B (es) 2025-03-24
MX2016010443A (es) 2016-09-22
MX2019015119A (es) 2020-02-12
KR102189466B1 (ko) 2020-12-11
KR20170075815A (ko) 2017-07-03
KR20180133951A (ko) 2018-12-17
KR101752343B1 (ko) 2017-06-29
US10979080B2 (en) 2021-04-13
US20190372601A1 (en) 2019-12-05
KR20160121514A (ko) 2016-10-19
JP2015156532A (ja) 2015-08-27
KR102361969B1 (ko) 2022-02-14
KR20190108194A (ko) 2019-09-23
US10425112B2 (en) 2019-09-24

Similar Documents

Publication Publication Date Title
US11711097B2 (en) Data processing device and data processing method
US10979080B2 (en) Data processing device and data processing method using low density parity check encoding for decreasing signal-to-noise power ratio
US11509331B2 (en) Data processing device and data processing method
US20220263521A1 (en) Data processing device and data processing method
US10707903B2 (en) Data processing device and data processing method
US11601142B2 (en) Data processing device and data processing method
US11070233B2 (en) Data processing device and data processing method
US20160211868A1 (en) Data processing device and data processing method
US10992321B2 (en) Data processing device and data processing method
US11239863B2 (en) Data processing device and data processing method
US20160233890A1 (en) Data processing device and data processing method
US20160197625A1 (en) Data processing device and data processing method
US20190109602A1 (en) Data processing device and data processing method
US20170187393A1 (en) Data processing device and data processing method

Legal Events

Date Code Title Description
AS Assignment

Owner name: SONY CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:IKEGAYA, RYOJI;YAMAMOTO, MAKIKO;SHINOHARA, YUJI;SIGNING DATES FROM 20160518 TO 20160520;REEL/FRAME:039655/0845

AS Assignment

Owner name: SATURN LICENSING LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SONY CORPORATION;REEL/FRAME:044171/0491

Effective date: 20171004

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION