F

FPGA

A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector

An implementation of Simon Says in Verilog for Xilinx FPGA systems

BProC (Basic Processor Compiler) is a small customizable instruction set compiler for basic processor design, intended for educational purposes.

Verible build container.

USB 2.0 HS programmer for Lattice FPGA with JTAG or SPI.

MSc Thesis - Development of an Embedded Image Processor Architecture on FPGA

PyTCL allows control EDA tools directly from Python that use TCL.

HACK CPU from course nand2tetris written in verilog with vga and ps/2 keyboard.

Implementation of Intel8080 cpu written in verilog running spaceinvaders.

Open source Logic Analyzer based on LiteX SoC

The soft core for the Ice Sea VR headset. Designed to be run on the FPGA of the headset mainboard

Simple SDRAM test for Cyclone FPGA in VHDL

Using Yosys to synthesize a bitstream for a Lattice MachXO3 board

VHDL generator for Gowin pROM IP Core

Z80 @10 MHz PoC for Altera Cyclone II and Cyclone IV (DE0-Nano board) FPGAs

Running legacy Xilinx ISE FPGA software on a MacOS system (including Apple Silicon) using Docker.

CMake scripts for building FPGA/ASIC projects.

AXIoE is a packet format and network protocol for executing ARM(R) AMBA(R) 4 AXI standard bus style memory transactions on a remote device connected through an Ethernet network.